| /Zephyr-Core-3.6.0/drivers/bbram/ |
| D | bbram_stm32.c | 4 * SPDX-License-Identifier: Apache-2.0
22 #define STM32_BKP_REG_OFFSET (TAMP_BASE + offsetof(TAMP_TypeDef, BKP0R) - RTC_BASE)
26 #define STM32_BKP_REG_INDEX(offset) ((offset) >> 2) argument
27 #define STM32_BKP_REG_BYTE_INDEX(offset) ((offset)&0x3UL) argument
28 #define STM32_BKP_REG(i) (((volatile uint32_t *)config->base_addr)[(i)])
39 static int bbram_stm32_read(const struct device *dev, size_t offset, size_t size, uint8_t *data) in bbram_stm32_read() argument
41 const struct bbram_stm32_config *config = dev->config; in bbram_stm32_read()
42 uint32_t reg, begin, to_copy; in bbram_stm32_read() local
44 if (size < 1 || offset + size > config->size) { in bbram_stm32_read()
45 return -EFAULT; in bbram_stm32_read()
[all …]
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| /Zephyr-Core-3.6.0/drivers/flash/ |
| D | flash_sam0.c | 4 * SPDX-License-Identifier: Apache-2.0
22 BUILD_ASSERT((FLASH_WRITE_BLK_SZ % sizeof(uint32_t)) == 0, "unsupported write-block-size");
84 struct flash_sam0_data *ctx = dev->data; in flash_sam0_sem_take()
86 k_sem_take(&ctx->sem, K_FOREVER); in flash_sam0_sem_take()
93 struct flash_sam0_data *ctx = dev->data; in flash_sam0_sem_give()
95 k_sem_give(&ctx->sem); in flash_sam0_sem_give()
99 static int flash_sam0_valid_range(off_t offset, size_t len) in flash_sam0_valid_range() argument
101 if (offset < 0) { in flash_sam0_valid_range()
102 LOG_WRN("0x%lx: before start of flash", (long)offset); in flash_sam0_valid_range()
103 return -EINVAL; in flash_sam0_valid_range()
[all …]
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| D | flash_rpi_pico.c | 5 * SPDX-License-Identifier: Apache-2.0
44 * github.com/raspberrypi/pico-bootrom/blob/master/bootrom/program_flash_generic.c
46 * github.com/raspberrypi/pico-sdk/blob/master/src/rp2_common/hardware_flash/flash.c
82 io_rw_32 *reg = (io_rw_32 *) (IO_QSPI_BASE + IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET); in __no_inline_not_in_flash_func() local
83 *reg = (*reg & ~IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS) in __no_inline_not_in_flash_func()
85 (void) *reg; in __no_inline_not_in_flash_func()
97 const uint max_in_flight = 16 - 2; in __no_inline_not_in_flash_func()
106 tx_level = ssi_hw->txflr; in __no_inline_not_in_flash_func()
107 rx_level = ssi_hw->rxflr; in __no_inline_not_in_flash_func()
110 ssi->dr0 = (uint32_t) (tx ? *tx++ : 0); in __no_inline_not_in_flash_func()
[all …]
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| /Zephyr-Core-3.6.0/soc/arm/microchip_mec/mec172x/reg/ |
| D | mec172x_pcr.h | 4 * SPDX-License-Identifier: Apache-2.0
53 * CLK_REQ bits are read-only. The peripheral sets its CLK_REQ if it requires
68 * Execute Cortex-M4 WFI sequence. DSB(), ISB(), WFI(), NOP()
69 * Cortex-M4 will assert sleep signal to PCR block.
105 * Divides 96MHz clock to ARM Cortex-M4 core including
121 /* PCR Oscillator ID register (Read-Only) */
153 * Sleep Enable Reg 0 (Offset +30h)
154 * Clock Required Reg 0 (Offset +50h)
155 * Reset Enable Reg 0 (Offset +70h)
162 * Sleep Enable Reg 1 (Offset +34h)
[all …]
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| /Zephyr-Core-3.6.0/drivers/sensor/tmp116/ |
| D | tmp116.c | 4 * SPDX-License-Identifier: Apache-2.0
27 static int tmp116_reg_read(const struct device *dev, uint8_t reg, in tmp116_reg_read() argument
30 const struct tmp116_dev_config *cfg = dev->config; in tmp116_reg_read()
32 if (i2c_burst_read_dt(&cfg->bus, reg, (uint8_t *)val, 2) in tmp116_reg_read()
34 return -EIO; in tmp116_reg_read()
42 static int tmp116_reg_write(const struct device *dev, uint8_t reg, in tmp116_reg_write() argument
45 const struct tmp116_dev_config *cfg = dev->config; in tmp116_reg_write()
46 uint8_t tx_buf[3] = {reg, val >> 8, val & 0xFF}; in tmp116_reg_write()
48 return i2c_write_dt(&cfg->bus, tx_buf, sizeof(tx_buf)); in tmp116_reg_write()
51 static bool check_eeprom_bounds(const struct device *dev, off_t offset, in check_eeprom_bounds() argument
[all …]
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| /Zephyr-Core-3.6.0/dts/bindings/mtd/ |
| D | fixed-partitions.yaml | 9 compatible = "fixed-partitions";
10 #address-cells = <1>;
11 #size-cells = <1>;
15 reg = <0x00000000 0x0000C000>;
18 label = "image-0";
19 reg = <0x0000C000 0x00076000>;
22 label = "image-1";
23 reg = <0x00082000 0x00076000>;
37 reg = <0x000f8000 0x00008000>;
43 The fixed-partitions node should be a child of the flash
[all …]
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| /Zephyr-Core-3.6.0/include/zephyr/dt-bindings/reset/ |
| D | gd32-common.h | 4 * SPDX-License-Identifier: Apache-2.0
11 * Encode RCU register offset and configuration bit.
13 * - 0..5: bit number
14 * - 6..14: offset
15 * - 15: reserved
17 * @param reg RCU register name (expands to GD32_{reg}_OFFSET)
20 #define GD32_RESET_CONFIG(reg, bit) \ argument
21 (((GD32_ ## reg ## _OFFSET) << 6U) | (bit))
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| /Zephyr-Core-3.6.0/include/zephyr/dt-bindings/clock/ |
| D | gd32-clocks-common.h | 4 * SPDX-License-Identifier: Apache-2.0
11 * Encode RCU register offset and configuration bit.
13 * - 0..5: bit number
14 * - 6..14: offset
15 * - 15: reserved
17 * @param reg RCU register name (expands to GD32_{reg}_OFFSET)
20 #define GD32_CLOCK_CONFIG(reg, bit) \ argument
21 (((GD32_ ## reg ## _OFFSET) << 6U) | (bit))
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| D | stm32f1_clock.h | 4 * SPDX-License-Identifier: Apache-2.0
42 * - reg (1/2/3) [ 0 : 7 ]
43 * - shift (0..31) [ 8 : 12 ]
44 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
45 * - val (0..7) [ 16 : 18 ]
47 * @param reg RCC_CFGRx register offset
52 #define STM32_CLOCK(val, mask, shift, reg) \ argument
53 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
58 /** @brief RCC_CFGR2 register offset */
61 /** @brief RCC_BDCR register offset */
|
| D | stm32f4_clock.h | 4 * SPDX-License-Identifier: Apache-2.0
53 * - reg (1/2/3) [ 0 : 7 ]
54 * - shift (0..31) [ 8 : 12 ]
55 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
56 * - val (0..7) [ 16 : 18 ]
58 * @param reg RCC_CFGRx register offset
63 #define STM32_CLOCK(val, mask, shift, reg) \ argument
64 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \
69 /** @brief RCC_CFGR register offset */
71 /** @brief RCC_BDCR register offset */
|
| /Zephyr-Core-3.6.0/tests/drivers/smbus/smbus_emul/src/ |
| D | emul.c | 4 * SPDX-License-Identifier: Apache-2.0
38 uint8_t offset; member
51 sys_slist_prepend(&peripherals, &peripheral->node); in emul_register_smbus_peripheral()
59 if (peripheral->addr == addr) { in emul_get_smbus_peripheral()
72 if (peripheral->smbalert && !peripheral->smbalert_handled) { in peripheral_handle_smbalert()
82 LOG_DBG("Return own address: 0x%02x", found->addr); in peripheral_handle_smbalert()
84 io_area[PCH_SMBUS_HD0] = found->addr; in peripheral_handle_smbalert()
85 found->smbalert_handled = true; in peripheral_handle_smbalert()
95 if (peripheral->host_notify) { in peripheral_handle_host_notify()
97 io_area[PCH_SMBUS_NDA] = peripheral->addr << 1; in peripheral_handle_host_notify()
[all …]
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| /Zephyr-Core-3.6.0/dts/x86/intel/ |
| D | raptor_lake_p.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/pcie/pcie.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "intel,raptor-lake";
20 d-cache-line-size = <64>;
21 reg = <0>;
[all …]
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| D | elkhart_lake.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,elkhart-lake";
20 d-cache-line-size = <64>;
21 reg = <0>;
28 reg = <0x0 DT_DRAM_SIZE>;
[all …]
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| D | alder_lake.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "intel,alder-lake";
21 d-cache-line-size = <64>;
22 reg = <0>;
[all …]
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| D | raptor_lake_s.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pcie/pcie.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,raptor-lake";
20 d-cache-line-size = <64>;
21 reg = <0>;
[all …]
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| /Zephyr-Core-3.6.0/dts/bindings/pwm/ |
| D | intel,blinky-pwm.yaml | 3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "intel,blinky-pwm"
9 include: [pwm-controller.yaml, base.yaml]
12 reg:
15 reg-offset:
18 description: PWM control register offset from base
20 clock-frequency:
25 max-pins:
30 "#pwm-cells":
33 pwm-cells:
[all …]
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| /Zephyr-Core-3.6.0/dts/bindings/dma/ |
| D | nxp,mcux-edma.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mcux-edma"
8 include: dma-controller.yaml
11 reg:
20 dma-channels:
23 dma-requests:
26 dmamux-reg-offset:
30 The offset value for obtaining DMAMUX register index from DMAMUX channel.
33 channel-gap:
47 irq-shared-offset:
[all …]
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| /Zephyr-Core-3.6.0/boards/xtensa/nxp_adsp_rt595/ |
| D | nxp_adsp_rt595.dts | 3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "cdns,tensilica-xtensa-lx6";
21 reg = <0>;
26 #address-cells = <1>;
27 #size-cells = <1>;
29 compatible = "mmio-sram";
31 reg = <0x0 DT_SIZE_K(512)>;
[all …]
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| /Zephyr-Core-3.6.0/drivers/mfd/ |
| D | mfd_npm1300.c | 3 * SPDX-License-Identifier: Apache-2.0
57 uint8_t offset; member
76 k_work_submit(&data->work); in gpio_callback()
82 const struct mfd_npm1300_config *config = data->dev->config; in work_callback()
87 ret = mfd_npm1300_reg_read_burst(data->dev, MAIN_BASE, 0U, buf, sizeof(buf)); in work_callback()
89 k_work_submit(&data->work); in work_callback()
94 int offset = event_reg[i].offset + MAIN_OFFSET_CLR; in work_callback() local
96 if ((buf[offset] & event_reg[i].mask) != 0U) { in work_callback()
97 gpio_fire_callbacks(&data->callbacks, data->dev, BIT(i)); in work_callback()
99 ret = mfd_npm1300_reg_write(data->dev, MAIN_BASE, offset, in work_callback()
[all …]
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| /Zephyr-Core-3.6.0/drivers/ethernet/ |
| D | eth_smsc911x_priv.h | 1 /* SPDX-License-Identifier: Apache-2.0 */
4 * Copyright (c) 2018-2019 Linaro Limited
10 * http://www.apache.org/licenses/LICENSE-2.0
25 /* This file is the re-implementation of mps2_ethernet_api and Selftest's
27 * MPS2 Selftest:https://silver.arm.com/browse/VEI10 ->
28 * \ISCM-1-0\AN491\software\Selftest\v2m_mps2\
44 (((val) >> (lsb)) & ((1 << ((msb) - (lsb) + 1)) - 1))
46 #define SMSC9220_BFIELD(reg, bfield) BFIELD(SMSC9220->reg, reg ## _ ## bfield) argument
53 /* Receive FIFO Ports (offset 0x0) */
56 /* Transmit FIFO Ports (offset 0x20) */
[all …]
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| /Zephyr-Core-3.6.0/arch/arc/include/ |
| D | swap_macros.h | 1 /* swap_macros.h - helper macros for context switch */
6 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/arch/arc/tool-compat.h>
17 #include <zephyr/arch/arc/asm-compat/assembler.h>
280 * _kernel.current. r3 is a scratch reg.
362 * need two temp reg to do this
367 and MACRO_ARG(reg1), MACRO_ARG(reg1), ((1 << ARC_N_IRQ_START_LEVEL) - 1)
378 * the result will be in reg (a reg)
380 .macro _get_cpu_id, reg
381 LRR MACRO_ARG(reg), [_ARC_V2_IDENTITY]
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| /Zephyr-Core-3.6.0/drivers/pinctrl/ |
| D | pfc_rcar.c | 2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
45 uint32_t offset; member
95 uint16_t reg_offs = PFC_RCAR_IPSR + rcar_func->bank * sizeof(uint32_t); in pfc_rcar_set_ipsr()
98 val &= ~(0xFU << rcar_func->shift); in pfc_rcar_set_ipsr()
99 val |= (rcar_func->func << rcar_func->shift); in pfc_rcar_set_ipsr()
103 static uint32_t pfc_rcar_get_drive_reg(uint16_t pin, uint8_t *offset, in pfc_rcar_get_drive_reg() argument
108 while (drive_regs->reg != 0U) { in pfc_rcar_get_drive_reg()
109 for (size_t i = 0U; i < ARRAY_SIZE(drive_regs->fields); i++) { in pfc_rcar_get_drive_reg()
110 if (drive_regs->fields[i].pin == pin) { in pfc_rcar_get_drive_reg()
[all …]
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| /Zephyr-Core-3.6.0/boards/shields/ssd1306/ |
| D | ssd1306_128x32.overlay | 4 * SPDX-License-Identifier: Apache-2.0
18 reg = <0x3c>;
21 segment-offset = <0>;
22 page-offset = <0>;
23 display-offset = <0>;
24 multiplex-ratio = <31>;
25 segment-remap;
26 com-invdir;
27 com-sequential;
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| D | sh1106_128x64.overlay | 4 * SPDX-License-Identifier: Apache-2.0
18 reg = <0x3c>;
21 segment-offset = <2>;
22 page-offset = <0>;
23 display-offset = <0>;
24 multiplex-ratio = <63>;
25 segment-remap;
26 com-invdir;
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| D | ssd1306_128x64.overlay | 4 * SPDX-License-Identifier: Apache-2.0
18 reg = <0x3c>;
21 segment-offset = <0>;
22 page-offset = <0>;
23 display-offset = <0>;
24 multiplex-ratio = <63>;
25 segment-remap;
26 com-invdir;
|
