| /Zephyr-latest/dts/bindings/sdhc/ |
| D | nxp,imx-usdhc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,imx-usdhc"
8 include: [sdhc.yaml, pinctrl-device.yaml]
14 data-timeout:
20 read-watermark:
24 Number of words used as read watermark level in FIFO queue for USDHC
26 write-watermark:
30 Number of words used as write watermark level in FIFO queue for USDHC
41 pwr-gpios:
42 type: phandle-array
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| /Zephyr-latest/tests/posix/common/src/ |
| D | clock.c | 5 * SPDX-License-Identifier: Apache-2.0
15 #define CLOCK_INVALID -1
19 /* Set a particular time. In this case, the output of: `date +%s -d 2018-01-01T15:45:01Z` */
33 return ts->tv_sec * NSEC_PER_SEC + ts->tv_nsec; in ts_to_ns()
38 ts->tv_sec = tv->tv_sec; in tv_to_ts()
39 ts->tv_nsec = tv->tv_usec * NSEC_PER_USEC; in tv_to_ts()
55 _decl_op(int64_t, tp_diff, -); /* a - b */
57 /* lo <= (a - b) < hi */
72 zassert_equal(clock_gettime(CLOCK_INVALID, &ts), -1); in ZTEST()
78 zassert_equal(clock_gettime(clocks[0], NULL), -1); in ZTEST()
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| /Zephyr-latest/tests/boards/frdm_k64f/i2c/src/ |
| D | i2c.c | 4 * SPDX-License-Identifier: Apache-2.0
60 /* Enable FIFO mode with a watermark of 16 */ in fxos8700_fifo_cfg()
96 /* Read 3 axis 14 bit (2 byte) data */
227 zassert_true(signaled > 0, "expected signaled to be non-zero"); in test_i2c_fxos8700_transfer_signal()
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| /Zephyr-latest/drivers/sensor/adi/adxl345/ |
| D | adxl345.c | 4 * SPDX-License-Identifier: Apache-2.0
23 return device_is_ready(bus->i2c.bus); in adxl345_bus_is_ready_i2c()
29 const struct adxl345_dev_config *cfg = dev->config; in adxl345_reg_access_i2c()
32 return i2c_burst_read_dt(&cfg->bus.i2c, reg_addr, data, length); in adxl345_reg_access_i2c()
34 return i2c_burst_write_dt(&cfg->bus.i2c, reg_addr, data, length); in adxl345_reg_access_i2c()
42 return spi_is_ready_dt(&bus->spi); in adxl345_bus_is_ready_spi()
48 const struct adxl345_dev_config *cfg = dev->config; in adxl345_reg_access_spi()
60 ret = spi_transceive_dt(&cfg->bus.spi, &tx, &rx); in adxl345_reg_access_spi()
63 ret = spi_write_dt(&cfg->bus.spi, &tx); in adxl345_reg_access_spi()
72 const struct adxl345_dev_config *cfg = dev->config; in adxl345_reg_access()
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| /Zephyr-latest/drivers/sensor/st/lsm6dsv16x/ |
| D | lsm6dsv16x_rtio_stream.c | 1 /* ST Microelectronics LSM6DSV16X 6-axis IMU sensor driver
6 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/sensor/lsm6dsv16x.h>
25 struct lsm6dsv16x_data *lsm6dsv16x = dev->data; in lsm6dsv16x_config_fifo()
26 const struct lsm6dsv16x_config *config = dev->config; in lsm6dsv16x_config_fifo()
27 stmdev_ctx_t *ctx = (stmdev_ctx_t *)&config->ctx; in lsm6dsv16x_config_fifo()
47 xl_batch = config->accel_batch; in lsm6dsv16x_config_fifo()
48 gy_batch = config->gyro_batch; in lsm6dsv16x_config_fifo()
49 temp_batch = config->temp_batch; in lsm6dsv16x_config_fifo()
52 fifo_wtm = config->fifo_wtm; in lsm6dsv16x_config_fifo()
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| /Zephyr-latest/drivers/sensor/tdk/icm42688/ |
| D | icm42688_common.c | 6 * SPDX-License-Identifier: Apache-2.0
24 const struct icm42688_dev_cfg *dev_cfg = dev->config; in icm42688_reset()
26 /* start up time for register read/write after POR is 1ms and supply ramp time is 3ms */ in icm42688_reset()
29 /* perform a soft reset to ensure a clean slate, reset bit will auto-clear */ in icm42688_reset()
30 res = icm42688_spi_single_write(&dev_cfg->spi, REG_DEVICE_CONFIG, BIT_SOFT_RESET); in icm42688_reset()
41 res = icm42688_spi_read(&dev_cfg->spi, REG_INT_STATUS, &value, 1); in icm42688_reset()
49 return -EINVAL; in icm42688_reset()
52 res = icm42688_spi_read(&dev_cfg->spi, REG_WHO_AM_I, &value, 1); in icm42688_reset()
59 return -EINVAL; in icm42688_reset()
67 const bool accel_enabled = cfg->accel_pwr_mode != ICM42688_DT_ACCEL_OFF; in icm42688_compute_fifo_wm()
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| /Zephyr-latest/drivers/dai/nxp/sai/ |
| D | sai.c | 4 * SPDX-License-Identifier: Apache-2.0
53 cfg = dev->config; in sai_mclk_config()
54 data = dev->data; in sai_mclk_config()
56 mclk_config.mclkOutputEnable = cfg->mclk_is_output; in sai_mclk_config()
65 ret = get_mclk_rate(&cfg->clk_data, bclk_source, &mclk_rate); in sai_mclk_config()
73 LOG_DBG("target MCLK is %u", bespoke->mclk_rate); in sai_mclk_config()
79 mclk_config.mclkHz = bespoke->mclk_rate; in sai_mclk_config()
82 SAI_SetMasterClockConfig(UINT_TO_I2S(data->regmap), &mclk_config); in sai_mclk_config()
84 set_msel(data->regmap, msel); in sai_mclk_config()
96 data = dev->data; in sai_isr()
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | sensor.h | 10 * SPDX-License-Identifier: Apache-2.0
42 * and can be obtained using the formula val1 + val2 * 10^(-6). Negative
47 * -0.5: val1 = 0, val2 = -500000
48 * -1.0: val1 = -1, val2 = 0
49 * -1.5: val1 = -1, val2 = -500000
54 /** Fractional part of the value (in one-millionth parts). */
101 /** Illuminance in infra-red spectrum, in lux. */
112 /** 1.0 micro-meters Particulate Matter, in ug/m^3 */
114 /** 2.5 micro-meters Particulate Matter, in ug/m^3 */
116 /** 10 micro-meters Particulate Matter, in ug/m^3 */
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| /Zephyr-latest/include/zephyr/net/ |
| D | socket.h | 9 * Copyright (c) 2017-2018 Linaro Limited
12 * SPDX-License-Identifier: Apache-2.0
66 /** zsock_recv: Read data without removing it from socket input queue */
75 /** zsock_recv/zsock_send: Override operation to non-blocking */
85 /* Well-known values, e.g. from Linux man 2 shutdown:
118 /** Write-only socket option to set hostname. It accepts a string containing
129 /** Read-only socket option to read a ciphersuite chosen during TLS handshake.
134 /** Write-only socket option to set peer verification level for TLS connection.
137 * - 0 - none
138 * - 1 - optional
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| /Zephyr-latest/drivers/sensor/adi/adxl372/ |
| D | adxl372.c | 4 * SPDX-License-Identifier: Apache-2.0
25 * @param dev - The device structure.
26 * @param axis_reg_h - The high part of the activity register.
27 * @param act - The activity config structure.
36 struct adxl372_data *data = dev->data; in adxl372_set_activity_threshold()
38 ret = data->hw_tf->write_reg(dev, axis_reg_h++, act->thresh >> 3); in adxl372_set_activity_threshold()
47 val = (act->thresh << 5) | (act->referenced << 1) | act->enable; in adxl372_set_activity_threshold()
50 val = (act->thresh << 5) | act->enable; in adxl372_set_activity_threshold()
53 return data->hw_tf->write_reg(dev, axis_reg_h, val); in adxl372_set_activity_threshold()
57 * Set the threshold for activity detection for all 3-axis
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| /Zephyr-latest/drivers/adc/ |
| D | adc_mcux_lpadc.c | 2 * Copyright 2023-2024 NXP
6 * Copyright (c) 2017-2018, NXP
9 * SPDX-License-Identifier: Apache-2.0
65 const struct mcux_lpadc_config *config = dev->config; in mcux_lpadc_acquisition_time_setup()
88 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &adc_freq_hz)) { in mcux_lpadc_acquisition_time_setup()
90 return -EINVAL; in mcux_lpadc_acquisition_time_setup()
101 cmd->sampleTimeMode = kLPADC_SampleTimeADCK3; in mcux_lpadc_acquisition_time_setup()
103 cmd->sampleTimeMode = kLPADC_SampleTimeADCK5; in mcux_lpadc_acquisition_time_setup()
105 cmd->sampleTimeMode = kLPADC_SampleTimeADCK7; in mcux_lpadc_acquisition_time_setup()
107 cmd->sampleTimeMode = kLPADC_SampleTimeADCK11; in mcux_lpadc_acquisition_time_setup()
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| /Zephyr-latest/drivers/ieee802154/ |
| D | ieee802154_kw41z.c | 1 /* ieee802154_kw41z.c - NXP KW41Z driver */
6 * SPDX-License-Identifier: Apache-2.0
35 * For non-invasive tracing of IRQ events. Sometimes the print logs
65 ZLL->EVENT_TMR >> ZLL_EVENT_TMR_EVENT_TMR_SHIFT; \
92 #define KW41Z_OUTPUT_POWER_MIN (-31)
127 1, /* -31.1 dBm: -31 */
128 2, 2, 2, 2, 2, 2, 2, /* -25.0 dBm: -30, -29, -28, -27, -26, -25 */
129 4, 4, 4, 4, 4, /* -19.0 dBm: -24, -23, -22, -21, -20, -19 */
130 6, 6, 6, /* -15.6 dBm: -18, -17, -16 */
131 8, 8, /* -13.1 dBm: -15, -14 */
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| /Zephyr-latest/subsys/bluetooth/controller/ll_sw/openisa/hal/RV32M1/radio/ |
| D | radio.c | 2 * Copyright (c) 2016 - 2019 Nordic Semiconductor ASA
4 * Copyright 2019 - 2020 NXP
6 * SPDX-License-Identifier: Apache-2.0
43 #define RADIO_AESCCM_HDR_MASK 0xE3 /* AES-CCM: NESN, SN, MD bits masked to 0 */
44 #define RADIO_PDU_LEN_MAX (BIT(8) - 1)
46 ((bytes) * 8 >> (__builtin_ffs(bits_per_usec) - 1))
52 #define RX_WTMRK 5 /* (AA + PDU header) - 1 */
138 uint8_t bytes[CAU3_AES_BLOCK_SIZE - 1 - 2];
139 } nonce; /* used by the B0 format but not in-situ */
157 uint32_t tmr = GENFSK->EVENT_TMR & GENFSK_EVENT_TMR_EVENT_TMR_MASK; in tmp_cb()
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