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/Zephyr-latest/boards/gd/gd32f350r_eval/
Dgd32f350r_eval.dts3 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "gd32f350r_eval-pinctrl.dtsi"
13 compatible = "gd,gd32f350r-eval";
19 zephyr,shell-uart = &usart0;
20 zephyr,flash-controller = &fmc;
30 current-speed = <115200>;
31 pinctrl-0 = <&usart0_default>;
32 pinctrl-names = "default";
37 /* Set ADC0 clock source to RCU_ADCCK_APB2_DIV4. */
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/Zephyr-latest/dts/bindings/adc/
Dgd,gd32-adc.yaml2 # SPDX-License-Identifier: Apache-2.0
11 # To cover this cases, adc_gd32 driver use node-label 'adc0', 'adc1' and
14 # Sorry for the restriction, But new added gd32 adc node-label must be 'adc0',
17 compatible: "gd,gd32-adc"
19 include: [adc-controller.yaml, reset-device.yaml, pinctrl-device.yaml]
31 rcu-clock-source:
34 Some GD32 ADC have additional clock source, like IRC14M or IRC28M.
35 This property used to select the clock and related prescaler, valid
36 values defined at 'dts-bindings/adc/gd32xxx.h' headers.
46 "#io-channel-cells":
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/Zephyr-latest/dts/arm/gd/gd32f3x0/
Dgd32f3x0.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/adc/gd32f3x0.h>
12 #include <zephyr/dt-bindings/clock/gd32f3x0-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32f3x0.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 clock-frequency = <DT_FREQ_M(108)>;
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/Zephyr-latest/doc/releases/
Drelease-notes-3.2.rst13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
151 * STM32 LPTIM domain clock should now be configured using devicetree.
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
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