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/Zephyr-latest/arch/sparc/core/
Dsw_trap_set_pil.S20 * - %l0: psr
29 /* %l5: new %psr */
34 wr %l5, %psr
Dswitch.S46 rd %psr, %o4
50 andn %o4, PSR_ET, %g1 /* %g1 = psr with traps disabled */
51 wr %g1, %psr /* disable traps */
90 wr %g1, %psr /* restore cwp */
138 ld [%o0 + _thread_offset_to_psr], %g1 /* %g1 = new thread psr */
140 andn %g1, PSR_CWP, %g1 /* psr without cwp */
141 or %g1, %g3, %g1 /* psr with new cwp */
142 wr %g1, %psr /* restore status register and ET */
Dinterrupt_trap.S22 * %l0: psr (set by trap code)
98 std %l0, [%sp + ISF_PSR_OFFSET] /* psr pc */
143 wr %l6, PSR_ET, %psr
204 wr %l6, %l5, %psr
261 ldd [%fp + ISF_PSR_OFFSET], %l0 /* psr, pc */
272 * Install the PSR we got from the interrupt context. Current PSR.CWP
273 * is preserved. Keep PSR.ET=0 until we do "rett".
275 rd %psr, %l3
279 mov %l0, %psr
323 * Restore %psr since we may have trashed condition codes. PSR.ET is
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Dthread.c47 thread->callee_saved.psr = PSR_S | PSR_PS | PSR_ET; in arch_new_thread()
52 thread->callee_saved.psr |= PSR_EF; in arch_new_thread()
56 thread->callee_saved.psr |= PSR_EF; in arch_new_thread()
Dfatal.c28 * psr: f30000c7 wim: 00000008 tbr: 40000020 y: 00000000
46 * representing the current trap type. psr is read immediately
63 * psr bits 11..8 is the processor interrupt (priority) level. 0
69 * the current window pointer (psr bits 4..0) which results in %o
165 "psr: %08x wim: %08x tbr: %08x y: %08x", in print_special_registers()
166 esf->psr, esf->wim, esf->tbr, esf->y in print_special_registers()
Dwindow_trap.S87 * %l0: psr
99 /* Uses g3=psr, g4=1, g2=wim, g1,g5=scratch */
149 /* We can not restore %psr from %l0 because we may be in any window. */
150 wr %g3, %psr
Dfault_trap.S21 * %l0: psr (set by trap code)
93 std %l0, [%sp + 96 + __struct_arch_esf_psr_OFFSET] /* psr pc */
100 wr %o2, PSR_ET, %psr
Dtrap_table_svt.S16 * - Provides handler with PSR in l0, TBR in l6
38 rd %psr, %l0
Dtrap_table_mvt.S17 rd %psr, %l0; \
23 rd %psr, %l0; \
29 rd %psr, %l0; \
Dreset_trap.S30 wr PSR_PIL | PSR_S | PSR_PS | PSR_ET, %psr
/Zephyr-latest/drivers/timer/
Drv32m1_lptmr_timer.c76 uint32_t csr, psr, sircdiv; /* LPTMR registers */ in sys_clock_driver_init() local
123 psr = SYSTEM_TIMER_INSTANCE->PSR; in sys_clock_driver_init()
124 psr &= ~LPTMR_PSR_PCS_MASK; in sys_clock_driver_init()
125 psr |= (LPTMR_PSR_PBYP(1) | LPTMR_PSR_PCS(PCS_SOURCE_SIRCDIV3)); in sys_clock_driver_init()
126 SYSTEM_TIMER_INSTANCE->PSR = psr; in sys_clock_driver_init()
/Zephyr-latest/arch/sparc/core/offsets/
Doffsets.c21 GEN_OFFSET_SYM(_callee_saved_t, psr);
37 GEN_OFFSET_STRUCT(arch_esf, psr);
/Zephyr-latest/include/zephyr/arch/sparc/
Dexception.h20 uint32_t psr; member
Dthread.h34 uint32_t psr; member
/Zephyr-latest/dts/bindings/i2c/
Dite,enhance-i2c.yaml18 SCL cycle = 2 * (psr + prescale_tweak + 2) *
/Zephyr-latest/drivers/i2c/
Di2c_ite_enhance.c299 uint32_t clk_div, psr, pll_clock, psr_h, psr_l; in i2c_enhanced_port_set_frequency() local
305 * Let psr(Prescale) = IT8XXX2_I2C_PSR(p_ch) in i2c_enhanced_port_set_frequency()
306 * Then, 1 SCL cycle = 2 x (psr + 2) x SMBus clock cycle in i2c_enhanced_port_set_frequency()
310 * 1 / freq = 2 x (psr + 2) x (1 / (pll_clock / clk_div)) in i2c_enhanced_port_set_frequency()
311 * psr = ((pll_clock / clk_div) x (1 / freq) x (1 / 2)) - 2 in i2c_enhanced_port_set_frequency()
316 /* Calculate PSR value */ in i2c_enhanced_port_set_frequency()
317 psr = (pll_clock / (clk_div * (2U * freq_hz))) - 2U; in i2c_enhanced_port_set_frequency()
318 /* Set psr value under 0xFD */ in i2c_enhanced_port_set_frequency()
319 if (psr > 0xFD) { in i2c_enhanced_port_set_frequency()
320 psr = 0xFD; in i2c_enhanced_port_set_frequency()
[all …]
/Zephyr-latest/drivers/sensor/infineon/dps310/
Ddps310.c439 float psr = ((float)psr_raw) / IFX_DPS310_SF_PSR; in dps310_scale_pressure() local
445 psr_final += psr * (comp->c10 + psr * (comp->c20 + psr * comp->c30)); in dps310_scale_pressure()
447 psr_final += tmp * psr * (comp->c11 + psr * comp->c21); in dps310_scale_pressure()
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/openisa/hal/RV32M1/
Dcntr.c56 LPTMR1->PSR = (LPTMR_PSR_PBYP(1) | LPTMR_PSR_PCS(PCS_SOURCE_RTC)); in cntr_init()
/Zephyr-latest/drivers/display/
Duc81xx.c198 uint8_t psr = in uc81xx_set_profile() local
237 psr |= UC81XX_PSR_REG; in uc81xx_set_profile()
242 LOG_DBG("PSR: %#hhx", psr); in uc81xx_set_profile()
243 if (uc81xx_write_cmd_uint8(dev, UC81XX_CMD_PSR, psr)) { in uc81xx_set_profile()
/Zephyr-latest/arch/arm/include/cortex_m/
Dexception.h263 /* Adjust stack alignment after PSR bit[9] detected */ in z_arm_set_fault_sp()
/Zephyr-latest/include/zephyr/xen/public/
Darch-arm.h353 /* PSR bits (CPSR, SPSR) */
/Zephyr-latest/arch/arm/core/cortex_m/
Dswap_helper.S475 * r0 - r1 - r2 - r3 - r12 - LR - PC - PSR
/Zephyr-latest/drivers/can/
Dcan_mcan.c600 /* Reading the lower byte of the PSR register clears the protocol last in can_mcan_read_psr()
602 * used whenever the PSR register is read. in can_mcan_read_psr()
/Zephyr-latest/drivers/ieee802154/
Dieee802154_dw1000_regs.h148 /* Bit mask to access Transmit Preamble Symbol Repetitions (PSR). */
152 /* Bit mask to access Transmit Preamble Symbol Repetitions (PSR). */
Dieee802154_dw1000.c1495 * PSR: preamble symbol repetitions in dwt_configure_rf_phy()