Searched full:pd2 (Results 1 – 25 of 49) sorted by relevance
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195 …l _U_(0x1) /**< \brief (PM_STDBYCFG) PD0 is forced ACTIVE. PD1 and PD2 power domains switc…196 …l _U_(0x2) /**< \brief (PM_STDBYCFG) PD0 and PD1 are forced ACTIVE. PD2 power domain switch…220 #define PM_STDBYCFG_LINKPD_PD12_Val _U_(0x2) /**< \brief (PM_STDBYCFG) PD1 and PD2 power do…
81 #define PIN_PD2 ( 98) /**< Pin Number for PD2 */160 #define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */239 #define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */412 #define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A…757 #define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux …919 #define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux…
81 #define PIN_PD2 ( 98) /**< Pin Number for PD2 */160 #define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */239 #define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */412 #define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A…791 #define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux …1045 #define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux…
81 #define PIN_PD2 ( 98) /**< Pin Number for PD2 */160 #define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */239 #define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */401 #define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A…784 #define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux …946 #define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux…
81 #define PIN_PD2 ( 98) /**< Pin Number for PD2 */160 #define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */239 #define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */412 #define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A…795 #define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux …957 #define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux…
81 #define PIN_PD2 ( 98) /**< Pin Number for PD2 */160 #define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */239 #define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */412 #define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A…804 #define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux …1058 #define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux…
81 #define PIN_PD2 ( 98) /**< Pin Number for PD2 */160 #define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */239 #define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */401 #define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A…793 #define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux …1047 #define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux…
81 #define PIN_PD2 ( 98) /**< Pin Number for PD2 */160 #define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */239 #define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */398 #define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A…755 #define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux …995 #define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux…
81 #define PIN_PD2 ( 98) /**< Pin Number for PD2 */160 #define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */239 #define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */398 #define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A…810 #define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux …1118 #define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux…
81 #define PIN_PD2 ( 98) /**< Pin Number for PD2 */160 #define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */239 #define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */398 #define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A…768 #define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux …1008 #define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux…
81 #define PIN_PD2 ( 98) /**< Pin Number for PD2 */160 #define PIO_PD2 (_U_(1) << 2) /**< PIO Mask for PD2 */239 #define PIO_PD2_IDX ( 98) /**< PIO Index Number for PD2 */398 #define PIN_PD2A_GMAC_GTX0 _L_(98) /**< GMAC signal: GTX0 on PD2 mux A…823 #define PIN_PD2B_PWM1_PWML1 _L_(98) /**< PWM1 signal: PWML1 on PD2 mux …1131 #define PIN_PD2D_USART0_DSR0 _L_(98) /**< USART0 signal: DSR0 on PD2 mux…
