Searched full:pb07 (Results 1 – 25 of 64) sorted by relevance
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100 #define PIN_PB07 39 /**< \brief Pin Number for PB07 */101 #define GPIO_PB07 _UL_(1 << 7) /**< \brief GPIO Mask for PB07 */233 #define PIN_PB07D_TC0_A0 _L_(39) /**< \brief TC0 signal: A0 on PB07 mux D */441 #define PIN_PB07A_USART3_CTS _L_(39) /**< \brief USART3 signal: CTS on PB07 mux A */553 #define PIN_PB07C_GLOC_IN5 _L_(39) /**< \brief GLOC signal: IN5 on PB07 mux C */796 #define PIN_PB07G_CATB_SENSE27 _L_(39) /**< \brief CATB signal: SENSE27 on PB07 mux G */881 #define PIN_PB07F_LCDCA_SEG21 _L_(39) /**< \brief LCDCA signal: SEG21 on PB07 mux F */
110 #define PIN_PB07 39 /**< \brief Pin Number for PB07 */111 #define GPIO_PB07 _UL_(1 << 7) /**< \brief GPIO Mask for PB07 */283 #define PIN_PB07D_TC0_A0 _L_(39) /**< \brief TC0 signal: A0 on PB07 mux D */499 #define PIN_PB07A_USART3_CTS _L_(39) /**< \brief USART3 signal: CTS on PB07 mux A */631 #define PIN_PB07C_GLOC_IN5 _L_(39) /**< \brief GLOC signal: IN5 on PB07 mux C */926 #define PIN_PB07G_CATB_SENSE27 _L_(39) /**< \brief CATB signal: SENSE27 on PB07 mux G */
100 #define PIN_PB07 39 /**< \brief Pin Number for PB07 */101 #define GPIO_PB07 _UL_(1 << 7) /**< \brief GPIO Mask for PB07 */361 #define PIN_PB07D_TC0_A0 _L_(39) /**< \brief TC0 signal: A0 on PB07 mux D */706 #define PIN_PB07A_USART3_CTS _L_(39) /**< \brief USART3 signal: CTS on PB07 mux A */902 #define PIN_PB07C_GLOC_IN5 _L_(39) /**< \brief GLOC signal: IN5 on PB07 mux C */1341 #define PIN_PB07G_CATB_SENSE27 _L_(39) /**< \brief CATB signal: SENSE27 on PB07 mux G */1482 #define PIN_PB07F_LCDCA_SEG21 _L_(39) /**< \brief LCDCA signal: SEG21 on PB07 mux F */
110 #define PIN_PB07 39 /**< \brief Pin Number for PB07 */111 #define GPIO_PB07 _UL_(1 << 7) /**< \brief GPIO Mask for PB07 */411 #define PIN_PB07D_TC0_A0 _L_(39) /**< \brief TC0 signal: A0 on PB07 mux D */764 #define PIN_PB07A_USART3_CTS _L_(39) /**< \brief USART3 signal: CTS on PB07 mux A */980 #define PIN_PB07C_GLOC_IN5 _L_(39) /**< \brief GLOC signal: IN5 on PB07 mux C */1471 #define PIN_PB07G_CATB_SENSE27 _L_(39) /**< \brief CATB signal: SENSE27 on PB07 mux G */
107 #define PIN_PB07 39 /**< \brief Pin Number for PB07 */108 #define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */591 #define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */1478 #define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */1511 #define PIN_PB07B_SDADC_INP2 _L_(39) /**< \brief SDADC signal: INP2 on PB07 mux B */1682 #define PIN_PB07I_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux I */1828 #define PIN_PB07D_SERCOM7_PAD2 _L_(39) /**< \brief SERCOM7 signal: PAD2 on PB07 mux D */1852 #define PIN_PB07C_SERCOM7_PAD3 _L_(39) /**< \brief SERCOM7 signal: PAD3 on PB07 mux C */
107 #define PIN_PB07 39 /**< \brief Pin Number for PB07 */108 #define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */426 #define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */1221 #define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */1254 #define PIN_PB07B_SDADC_INP2 _L_(39) /**< \brief SDADC signal: INP2 on PB07 mux B */1413 #define PIN_PB07I_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux I */
105 #define PIN_PB07 39 /**< \brief Pin Number for PB07 */106 #define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */361 #define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */1136 #define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */1500 #define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */1628 #define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */1685 #define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */
105 #define PIN_PB07 39 /**< \brief Pin Number for PB07 */106 #define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */361 #define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */1170 #define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */1534 #define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */1662 #define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */1719 #define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */
105 #define PIN_PB07 39 /**< \brief Pin Number for PB07 */106 #define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */361 #define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */1189 #define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */1553 #define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */1681 #define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */1738 #define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */
