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/Zephyr-latest/dts/bindings/ethernet/
Dxlnx,gem.yaml3 # SPDX-License-Identifier: Apache-2.0
10 include: ethernet-controller.yaml
19 clock-frequency:
27 which it will be adjusted at run-time. Therefore, the value of this
29 respective GEM's TX clock - by default, this is the IO PLL.
31 mdc-divider:
42 init-mdio-phy:
45 Activates the management of a PHY associated with the controller in-
46 stance. If this parameter is activated at the board level, the de-
47 fault values of the associated parameters mdio-phy-address, phy-poll-
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Dsnps,dwcxgmac.yaml2 # SPDX - License - Identifier : Apache - 2.0
9 - name: reset-device.yaml
10 - name: ethernet-controller.yaml
17 max-frame-size:
21 Maximum ethernet frame size. The current ethernet frame sizes
23 means that normally xgmac will reject any frame above max-frame-size
25 IEEE 802.3 ethernet frame:
26 Ethernet Frame [ 14 MAC HEADER | 1500 MTU | 4 FCS ] = 1518 bytes
27 max-speed:
30 - 10
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/Zephyr-latest/drivers/dai/intel/ssp/
Ddai-params-intel-ipc3.h4 * SPDX-License-Identifier: Apache-2.0
22 #define DAI_INTEL_IPC3_SSP_FMT_NB_NF (0 << 8) /**< normal bit clock + frame */
27 #define DAI_INTEL_IPC3_SSP_FMT_CBP_CFP (0 << 12) /**< codec bclk provider & frame provider */
28 #define DAI_INTEL_IPC3_SSP_FMT_CBC_CFP (2 << 12) /**< codec bclk consumer & frame provider */
29 #define DAI_INTEL_IPC3_SSP_FMT_CBP_CFC (3 << 12) /**< codec bclk provider & frame consumer */
30 #define DAI_INTEL_IPC3_SSP_FMT_CBC_CFC (4 << 12) /**< codec bclk consumer & frame consumer */
38 * DAI_CONFIG flags. The 4 LSB bits are used for the commands, HW_PARAMS, HW_FREE and PAUSE
47 /**< DAI_CONFIG sent during pause trigger. Only available ABI 3.20 onwards */
53 * pipeline stop/pause and DAI DMA stop/pause should happen in two steps. This change is only
100 /* SSP Configuration Request - SOF_DAI_SSP_CONFIG */
/Zephyr-latest/drivers/ethernet/
Deth_xlnx_gem_priv.h7 * SPDX-License-Identifier: Apache-2.0
26 /* Receive Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-2. */
30 * [31 .. 02] Mask for effective buffer address -> excludes [1..0]
47 * [23 .. 22] These bits have different semantics depending on whether RX check-
54 * [15] End-of-frame bit
55 * [14] Start-of-frame bit
57 * [12 .. 00] Data length of received frame
78 /* Transmit Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-3. */
85 * [27] TX frame corruption due to AHB/AXI error, HRESP errors or buffers
86 * exhausted mid-frame
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Deth_lan9250.c1 /* LAN9250 Stand-alone Ethernet Controller with SPI
5 * SPDX-License-Identifier: Apache-2.0
26 const struct lan9250_config *config = dev->config; in lan9250_write_sys_reg()
43 return spi_write_dt(&config->spi, &tx); in lan9250_write_sys_reg()
48 const struct lan9250_config *config = dev->config; in lan9250_read_sys_reg()
72 return spi_transceive_dt(&config->spi, &tx, &rx); in lan9250_read_sys_reg()
89 return -EIO; in lan9250_wait_ready()
141 return -EIO; in lan9250_wait_mac_ready()
155 * https://github.com/microchip-pic-avr-solutions/ethernet-lan9250/ in lan9250_read_phy_reg()
189 * https://github.com/microchip-pic-avr-solutions/ethernet-lan9250/ in lan9250_write_phy_reg()
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Deth_numaker.c4 * SPDX-License-Identifier: Apache-2.0
64 /* Delay execution for given amount of ticks for SDK-HAL */
74 synopGMAC_write_phy_reg((u32 *)gmacdev->MacBase, addr, reg, data); in mdio_write()
81 synopGMAC_read_phy_reg((u32 *)gmacdev->MacBase, addr, reg, &data); in mdio_read()
108 return -EIO; in reset_phy()
116 gmacdev->LinkState = LINKUP; in reset_phy()
119 gmacdev->LinkState = LINKDOWN; in reset_phy()
121 return -EIO; in reset_phy()
135 return -EIO; in reset_phy()
141 gmacdev->DuplexMode = FULLDUPLEX; in reset_phy()
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Deth_xlnx_gem.c5 * SPDX-License-Identifier: Apache-2.0
8 * - Only supports 32-bit addresses in buffer descriptors, therefore
9 * the ZynqMP APU (Cortex-A53 cores) may not be fully supported.
10 * - Hardware timestamps not considered.
11 * - VLAN tags not considered.
12 * - Wake-on-LAN interrupt not supported.
13 * - Send function is not SMP-capable (due to single TX done semaphore).
14 * - Interrupt-driven PHY management not supported - polling only.
15 * - No explicit placement of the DMA memory area(s) in either a
18 * with the Cortex-R5 QEMU target or an actual R5 running without the
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Deth_xmc4xxx.c5 * SPDX-License-Identifier: Apache-2.0
49 #define IS_OWNED_BY_DMA_TX(desc) (((desc)->status & ETH_MAC_DMA_TDES0_OWN) != 0)
50 #define IS_OWNED_BY_DMA_RX(desc) (((desc)->status & ETH_MAC_DMA_RDES0_OWN) != 0)
52 #define IS_START_OF_FRAME_RX(desc) (((desc)->status & ETH_MAC_DMA_RDES0_FS) != 0)
53 #define IS_END_OF_FRAME_RX(desc) (((desc)->status & ETH_MAC_DMA_RDES0_LS) != 0)
55 #define IS_TIMESTAMP_AVAILABLE_RX(desc) (((desc)->status & ETH_MAC_DMA_RDES0_TSA) != 0)
56 #define IS_TIMESTAMP_AVAILABLE_TX(desc) (((desc)->status & ETH_MAC_DMA_TDES0_TTSS) != 0)
58 #define TOTAL_FRAME_LENGTH(desc) (FIELD_GET(ETH_MAC_DMA_RDES0_FL, (desc)->status) - 4)
134 return ctx->iface; in get_iface()
139 const struct eth_xmc4xxx_config *dev_cfg = dev->config; in eth_xmc4xxx_tx_dma_descriptors_init()
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/Zephyr-latest/subsys/bluetooth/controller/ll_sw/
Dull_conn_types.h2 * Copyright (c) 2018-2019 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
46 uint8_t pause; member
55 uint8_t pause; member
227 /* Pause Rx data PDU's */
263 /* Detect empty L2CAP start frame */
/Zephyr-latest/include/zephyr/drivers/
Ddai.h4 * SPDX-License-Identifier: Apache-2.0
48 * clock-related configurations w.r.t the DAI
164 /** @brief Optional - Pre Start the transmission / reception of data.
180 /** @brief Pause the transmission / reception of data.
182 * Pause the transmission / reception of data at the end of the current
188 /** @brief Optional - Post Stop the transmission / reception of data.
257 /** Number of audio channels, words in frame. */
259 /** Frame clock (WS) frequency, sampling rate. */
354 const struct dai_driver_api *api = (const struct dai_driver_api *)dev->api; in dai_probe()
356 return api->probe(dev); in dai_probe()
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/Zephyr-latest/doc/connectivity/bluetooth/
Dbluetooth-ctlr-arch.rst1 .. _bluetooth-ctlr-arch:
27 * Software-based Link Layer implementation
107 Pre-emption of Active Event
133 - Event handle (0, 1) < Event preparation (2, 3) < Event/Rx done (4) < Tx
136 - LLL is vendor ISR, ULL is Mayfly ISR concept, Host is kernel thread.
147 - HCI/LLCP API
152 - lll_prepare context to drive ull_cp_run()
156 - rx_demux context to drive ull_cp_tx_ack() and ull_cp_rx()
164 - struct llcp_struct
168 * Basic conn-level abstraction
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/Zephyr-latest/drivers/dai/nxp/sai/
Dsai.c4 * SPDX-License-Identifier: Apache-2.0
53 cfg = dev->config; in sai_mclk_config()
54 data = dev->data; in sai_mclk_config()
56 mclk_config.mclkOutputEnable = cfg->mclk_is_output; in sai_mclk_config()
65 ret = get_mclk_rate(&cfg->clk_data, bclk_source, &mclk_rate); in sai_mclk_config()
73 LOG_DBG("target MCLK is %u", bespoke->mclk_rate); in sai_mclk_config()
79 mclk_config.mclkHz = bespoke->mclk_rate; in sai_mclk_config()
82 SAI_SetMasterClockConfig(UINT_TO_I2S(data->regmap), &mclk_config); in sai_mclk_config()
84 set_msel(data->regmap, msel); in sai_mclk_config()
96 data = dev->data; in sai_isr()
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/Zephyr-latest/drivers/i3c/
Di3c_npcx.c4 * SPDX-License-Identifier: Apache-2.0
103 #define I3C_BUS_TLOW_PP_MIN_NS 24 /* T_LOW period in push-pull mode */
104 #define I3C_BUS_THigh_PP_MIN_NS 24 /* T_High period in push-pull mode */
105 #define I3C_BUS_TLOW_OD_MIN_NS 200 /* T_LOW period in open-drain mode */
107 #define PPBAUD_DIV_MAX (BIT(GET_FIELD_SZ(NPCX_I3C_MCONFIG_PPBAUD)) - 1) /* PPBAUD divider max */
163 uint8_t ppbaud; /* Push-Pull high period */
164 uint8_t pplow; /* Push-Pull low period */
165 uint8_t odhpp; /* Open-Drain high period */
166 uint8_t odbaud; /* Open-Drain low period */
259 struct npcx_i3c_data *const data = dev->data; in npcx_i3c_mutex_lock()
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/Zephyr-latest/doc/releases/
Drelease-notes-3.2.rst13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
157 :dtcompatible:`fixed-partitions`.
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Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
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