Searched +full:other +full:- +full:controller (Results 1 – 25 of 612) sorted by relevance
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| /Zephyr-Core-3.5.0/tests/drivers/i2c/i2c_target_api/ |
| D | README.txt | 9 controllers on a common bus. The test is supported by a test-specific
11 is pre-loaded into the simulated devices outside the I2C API, and the
12 Zephyr application issues commands to one controller that are responded
13 to by the simulated EEPROM connected through the other controller.
16 controller and target behavior simultaneously. This is not true of all
17 I2C controllers, so this behavior is now opt-in using
23 * Use API specific to the simulated EEPROM to pre-populate the simulated
24 devices with device-specific content.
28 * Issue commands on one bus controller (operating as the bus controller) and
29 verify that the data supplied by the other controller (target) match
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/usb/ |
| D | uhc.h | 4 * SPDX-License-Identifier: Apache-2.0
9 * @brief USB host controller (UHC) driver API
22 * @brief USB host controller (UHC) driver API
23 * @defgroup uhc_api USB host controller driver API
72 /** Transfer result, 0 on success, other values on error */
77 * @brief USB host controller event types
99 * Non-correctable error event, requires attention from higher
106 * USB host controller event
111 * by higher layer during controller initialization (uhc_init).
124 /** Pointer to controller's device struct */
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| D | udc.h | 2 * Copyright (c) 2021-2022 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief New USB device controller (UDC) driver API
22 * @brief Maximum packet size of control endpoint supported by the controller.
32 * USB device controller capabilities
37 /** USB high speed capable controller */
39 /** Controller supports USB remote wakeup */
41 /** Controller performs status OUT stage automatically */
62 * USB device controller endpoint capabilities
82 * USB device controller endpoint status
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| /Zephyr-Core-3.5.0/drivers/reset/ |
| D | Kconfig | 1 # Reset Controller driver configuration options
3 # Copyright (c) 2022 Andrei-Edward Popa <andrei.popa105@yahoo.com>
4 # SPDX-License-Identifier: Apache-2.0
7 # Reset Controller options
10 bool "Reset Controller drivers"
12 Reset Controller drivers. Reset node represents a region containing
13 information about reset controller device. The typical use-case is
14 for some other node's drivers to acquire a reference to the reset
15 controller node together with some reset information.
20 int "Reset Controller driver init priority"
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| /Zephyr-Core-3.5.0/drivers/usb/uvb/ |
| D | uvb.h | 4 * SPDX-License-Identifier: Apache-2.0
161 * All devices subscribed to a controller are advertised.
164 * @param[in] host_node Pointer to host controller UVB node
168 * @return 0 on success, all other values should be treated as error.
175 * @brief Submit UVB event to host controller node
180 * @param[in] dev_node Pointer to device controller UVB node
184 * @return 0 on success, all other values should be treated as error.
196 * @param[in] dev_node Pointer to device controller UVB node
198 * @return 0 on success, all other values should be treated as error.
208 * @param[in] dev_node Pointer to device controller UVB node
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| /Zephyr-Core-3.5.0/samples/drivers/led_xec/ |
| D | README.rst | 1 .. zephyr:code-sample:: led-xec
2 :name: Breathing-blinking LED (BBLED)
3 :relevant-api: led_interface
5 Control a BBLED (Breathing-Blinking LED) using Microchip XEC driver.
10 This sample allows to test the Microchip led-xec driver which uses the
11 breathing-blinking LED (BBLED) controllers. The SoC design is fixed
16 - BBLED controller 0 uses GPIO 0156.
17 - BBLED controller 1 uses GPIO 0157.
18 - BBLED controller 2 uses GPIO 0153.
22 - BBLED controller 3 uses GPIO 0035
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| /Zephyr-Core-3.5.0/dts/bindings/flash_controller/ |
| D | st,stm32-flash-controller.yaml | 1 description: STM32 Family flash controller
3 compatible: "st,stm32-flash-controller"
5 include: flash-controller.yaml
8 st,rdp1-enable-byte:
12 This property provides a byte which should used to enable non-permanent
15 RDP1 but in multi-image environment, some other image could check if
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| /Zephyr-Core-3.5.0/drivers/syscon/ |
| D | Kconfig | 4 # SPDX-License-Identifier: Apache-2.0
10 bool "System Controller (SYSCON) drivers"
12 SYSCON (System Controller) drivers. System controller node represents
15 of device. The typical use-case is for some other node's driver, or
16 platform-specific code, to acquire a reference to the syscon node and
22 module-str = syscon
26 bool "Generic SYSCON (System Controller) driver"
30 Enable generic SYSCON (System Controller) driver
33 int "SYSCON (System Controller) driver init priority"
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| /Zephyr-Core-3.5.0/drivers/ps2/ |
| D | Kconfig.npcx | 4 # SPDX-License-Identifier: Apache-2.0
7 bool "Nuvoton NPCX embedded controller (EC) PS2 driver"
12 Each channel has two quasi-bidirectional signals that serve as
13 direct interfaces to an external keyboard, mouse or any other
14 PS/2-compatible pointing device.The driver also depends on the KBC
15 8042 keyboard controller.
25 NPCX PS/2 controller device driver should initialize
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| /Zephyr-Core-3.5.0/subsys/bluetooth/controller/coex/ |
| D | readme.rst | 2 Bluetooth co-existence drivers
5 Co-existence Ticker
8 …-existence with another transmitter. Chips such as nordic nRF9160 provide a 1-wire co-existence in…
10 …ovides detailed description of the 1-wire and 3-wire co-existence interface for the `SoftDevice Bl…
12 Similarly, as in the nordic implementation of the 1-wire interface, the coexistence ticker utilizes…
14 .. code-block:: DTS
17 compatible = "gpio-radio-coex";
18 grant-gpios = <&gpio0 0 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
19 grant-delay-us = <150>;
22 …-active (such as 1 for the nRF9160). state the implementation starts a ticker job, which in predef…
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/ |
| D | reset.h | 2 * Copyright (c) 2022 Andrei-Edward Popa <andrei.popa105@yahoo.com>
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public Reset Controller driver APIs
16 * @brief Reset Controller Interface
17 * @defgroup reset_controller_interface Reset Controller Interface
31 /** Reset controller device configuration. */
33 /** Reset controller device. */
43 * devicetree node identifier, a property specifying a Reset Controller and an index.
63 * controller reset line id as shown above.
87 * instance's Reset Controller property at an index.
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| D | cache.h | 4 * SPDX-License-Identifier: Apache-2.0
9 * Public APIs for external cache controller drivers
18 * @brief External Cache Controller Interface
19 * @defgroup cache_external_interface External Cache Controller Interface
31 * @brief Enable the d-cache
38 * @brief Disable the d-cache
45 * @brief Flush the d-cache
50 * @retval -ENOTSUP If not supported.
51 * @retval -errno Negative errno for other failures.
56 * @brief Invalidate the d-cache
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| /Zephyr-Core-3.5.0/drivers/interrupt_controller/ |
| D | Kconfig.intel_vtd | 1 # Intel VT-D interrupt remapping controller configuration
4 # SPDX-License-Identifier: Apache-2.0
7 bool "Intel VT-D interrupt remapping controller"
13 Such interrupt remapping hardware is provided through Intel VT-D
14 technology. It's being used, currently, only for MSI/MSI-X
15 multi-vector support. If you have such PCIe device requiring
16 multi-vector support, you will need to enable this.
21 bool "XAPIC mode pass-through"
36 other device that would require it for MSI/MSI-X multi-vector support.
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| /Zephyr-Core-3.5.0/dts/bindings/pinctrl/ |
| D | espressif,esp32-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Espressif's pin controller is in charge of controlling pin configurations, pin
7 states are composed by groups of pre-defined pin muxing definitions and user
10 Each Zephyr-based application has its own set of pin muxing/pin configuration
11 requirements. The next steps use ESP-WROVER-KIT's I2C_0 to illustrate how one
13 the same steps can be tweaked to address specifics of any other target board.
15 Suppose an application running on top of the ESP-WROVER-KIT board, for some
18 you'll notice that the I2C_0 node is already assigned to a pre-defined state.
22 #include "esp_wrover_kit-pinctrl.dtsi"
26 pinctrl-0 = <&i2c0_default>;
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| D | nxp,s32k3-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The NXP S32 pin controller is a singleton node responsible for controlling
20 #include <nxp/s32/S32K344-257BGA-pinctrl.h>
26 output-enable;
30 input-enable;
36 of a device. The 'default' state is the active state. Other states for the same
39 In addition to 'pinmux' property, each group can contain other properties such as
40 'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
41 'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
42 output buffer use 'output-enable'.
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| /Zephyr-Core-3.5.0/subsys/bluetooth/common/ |
| D | Kconfig | 5 # SPDX-License-Identifier: Apache-2.0
16 Controller. This value does not include the HCI ACL header.
17 The Host will segment the data transmitted to the Controller so that
18 packets sent to the Controller will contain data up to this size.
20 Controller.
21 In a Host-only build the Host will read the maximum ACL size supported
22 by the Controller and use the smallest value supported by both the
23 Host and the Controller.
26 The Controller will return this value in the HCI LE Read Buffer
28 Layer transmission size then the Controller will perform
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| /Zephyr-Core-3.5.0/drivers/clock_control/ |
| D | Kconfig | 1 # Clock controller driver configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 # Clock controller drivers
10 bool "Clock controller drivers"
12 Enable support for hardware clock controller. Such hardware can
13 provide clock for other subsystem, and thus can be also used for
26 module-str = clock control
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| /Zephyr-Core-3.5.0/dts/bindings/clock/ |
| D | st,stm32f3-rcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32F3 Reset and Clock controller node.
7 For more description confere st,stm32-rcc.yaml
9 compatible: "st,stm32f3-rcc"
11 include: st,stm32-rcc.yaml
14 adc12-prescaler:
17 - 0 # Synchronous mode
18 - 1 # not divided
19 - 2
20 - 4
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| /Zephyr-Core-3.5.0/include/zephyr/arch/ |
| D | cache.h | 4 * SPDX-License-Identifier: Apache-2.0
9 * Public APIs for architectural cache controller drivers
16 * @brief Cache Controller Interface
17 * @defgroup cache_arch_interface Cache Controller Interface
31 * @brief Enable the d-cache
40 * @brief Disable the d-cache
49 * @brief Flush the d-cache
54 * @retval -ENOTSUP If not supported.
55 * @retval -errno Negative errno for other failures.
62 * @brief Invalidate the d-cache
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| /Zephyr-Core-3.5.0/samples/drivers/can/babbling/ |
| D | README.rst | 1 .. zephyr:code-sample:: can-babbling
2 :name: Controller Area Network (CAN) babbling node
3 :relevant-api: can_interface
10 In a Controller Area Network a babbling node is a node continuously (and usually erroneously)
11 transmitting CAN frames with identical - often high - priority. This constant babbling blocks CAN
18 Being able to simulate a babbling CAN node is useful when examining the behavior of other nodes on
27 This sample requires a board with a CAN controller. The CAN controller must be configured using the
28 ``zephyr,canbus`` :ref:`devicetree <dt-guide>` chosen node property.
31 configured using the ``sw0`` :ref:`devicetree <dt-guide>` alias, usually in the :ref:`BOARD.dts file
32 <devicetree-in-out-files>`.
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| /Zephyr-Core-3.5.0/boards/arm/nuvoton_pfm_m487/doc/ |
| D | index.rst | 10 specially developed by Nuvoton. The PFM-M487 is based on the NuMicro® M487
11 Ethernet series MCU with ARM® -Cortex®-M4F core.
15 :alt: PFM-M487
19 - 32-bit Arm Cortex®-M4 M487JIDAE MCU
20 - Core clock up to 192 MHz
21 - 512 KB embedded Dual Bank Flash and 160 KB SRAM
22 - Audio codec (NAU88L25) with Microphone In and Headphone Out
23 - Ethernet (IP101GR) for network application
24 - USB 2.0 High-Speed OTG / Host / Device
25 - USB 1.1 Full-Speed OTG / Host / Device
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| /Zephyr-Core-3.5.0/dts/bindings/spi/ |
| D | snps,designware-spi.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "snps,designware-spi"
8 include: [spi-controller.yaml, pinctrl-device.yaml]
20 other platform, this value should be default 0.
23 fifo-depth:
28 Serial Interface. Depth ranges from 2-256.
|
| /Zephyr-Core-3.5.0/samples/bluetooth/ |
| D | bluetooth.rst | 1 .. _bluetooth-samples:
7 any other Zephyr application. Refer to :ref:`bluetooth-dev` for more information.
10 external Bluetooth Controllers. Refer to the :ref:`bluetooth-hw-setup` section
13 Several of the bluetooth samples will build a Zephyr-based Controller that can
20 ``-DBOARD=nrf5340dk_nrf5340_cpuapp`` or
21 ``-DBOARD=nrf5340dk_nrf5340_cpuapp_ns``) you must also build
23 :ref:`bluetooth-hci-rpmsg-sample` which implements the Bluetooth
24 Low Energy controller.
27 The mutually-shared encryption key created during host-device paring may get
28 old after many test iterations. If this happens, subsequent host-device
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| /Zephyr-Core-3.5.0/doc/connectivity/bluetooth/ |
| D | bluetooth-dev.rst | 1 .. _bluetooth-dev:
22 .. _bluetooth-hw-setup:
35 #. QEMU with an external Controller
36 #. Native POSIX with an external Controller
44 All the :ref:`bluetooth-configs` and :ref:`bluetooth-build-types` are supported
45 but you might need to build Zephyr more than once if you are using a dual-chip
47 build type (e.g., one running the Host, the other the Controller).
50 <getting_started>`, choose one (or more if you are using a dual-chip solution)
54 .. _bluetooth-hci-tracing:
57 --------------------
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| /Zephyr-Core-3.5.0/boards/arm/numaker_pfm_m467/doc/ |
| D | index.rst | 10 specially developed by Nuvoton. The PFM-M467 is based on the NuMicro® M467
11 Ethernet series MCU with ARM® -Cortex®-M4F core.
16 :alt: PFM-M467
20 - 32-bit Arm Cortex®-M4 M467HJHAE MCU
21 - Core clock up to 200 MHz
22 - 1024 KB embedded Dual Bank Flash and 512 KB SRAM
23 - Ethernet (IP101GR) for network application
24 - USB 2.0 High-Speed OTG / Host / Device
25 - USB 1.1 Full-Speed OTG / Host / Device
26 - External SPI Flash (Winbond W25Q20) which can be regarded as ROM module
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