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/Zephyr-latest/dts/bindings/w1/
Dadi,max32-w1.yaml1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
4 description: ADI MAX32xxx MCUs 1-Wire Master
6 include: [w1-master.yaml, pinctrl-device.yaml]
8 compatible: "adi,max32-w1"
20 pinctrl-0:
23 pinctrl-names:
26 internal-pullup:
32 0 - Internal pullup disabled.
33 1 - Internal pullup enabled.
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Dzephyr,w1-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
7 This defines a one-wire driver through GPIO bit-banging.
13 compatible = "zephyr,w1-gpio";
19 - w1 is pin 13 on gpio0. The gpio is active when the pin is high, is
20 configured as an open-drain, and has a pull-up resistor.
23 - Most drivers require the selected gpio to support open drain, this enables onewire
25 - Ensure pullup is strong enough (4.7K according to the specification). Standard pullup in
28 compatible: "zephyr,w1-gpio"
30 include: [w1-master.yaml]
34 type: phandle-array
/Zephyr-latest/doc/hardware/peripherals/
Dw1.rst3 1-Wire Bus
9 1-Wire is a low speed half-duplex serial bus using only a single wire plus
11 Similarly to I2C, 1-Wire uses a bidirectional open-collector data line,
12 and is a single master multidrop bus. This means one master initiates all data
14 The 1-Wire bus supports longer bus lines than I2C, while it reaches speeds of up
23 .. figure:: 1-Wire_bus_topology.drawio.svg
25 :alt: 1-Wire bus topology
27 A typical 1-Wire bus topology
30 .. _w1-master-api:
35 Zephyr's 1-Wire Master API is used to interact with 1-Wire slave devices like
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/Zephyr-latest/samples/drivers/led/xec/
DREADME.rst1 .. zephyr:code-sample:: led-xec
2 :name: Breathing-blinking LED (BBLED)
3 :relevant-api: led_interface
5 Control a BBLED (Breathing-Blinking LED) using Microchip XEC driver.
10 This sample allows to test the Microchip led-xec driver which uses the
11 breathing-blinking LED (BBLED) controllers. The SoC design is fixed
12 allowing each BBLED control over one specific GPIO.
16 - BBLED controller 0 uses GPIO 0156.
17 - BBLED controller 1 uses GPIO 0157.
18 - BBLED controller 2 uses GPIO 0153.
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/Zephyr-latest/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/
Dradio_nrf5_ppi_resources.h2 * Copyright (c) 2021-2024 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
9 /* PPI channel 20 is pre-programmed with the following fixed settings:
10 * EEP: TIMER0->EVENTS_COMPARE[0]
11 * TEP: RADIO->TASKS_TXEN
14 /* PPI channel 21 is pre-programmed with the following fixed settings:
15 * EEP: TIMER0->EVENTS_COMPARE[0]
16 * TEP: RADIO->TASKS_RXEN
20 /* PPI channel 26 is pre-programmed with the following fixed settings:
21 * EEP: RADIO->EVENTS_ADDRESS
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Dradio_nrf5_ppi.h2 * Copyright (c) 2018 - 2020 Nordic Semiconductor ASA
5 * SPDX-License-Identifier: Apache-2.0
10 * SW_SWITCH_TIMER-based auto-switch for TIFS, when receiving in LE Coded PHY.
16 /* Wire the SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
38 * wire the EVENT_TIMER EVENTS_COMPARE[0] event to RADIO TASKS_TXEN/RXEN task.
40 * Use the pre-programmed PPI channels if possible (if TIMER0 is used as the
47 /* No need to configure anything for the pre-programmed channels. in hal_radio_enable_on_tick_ppi_config_and_enable()
66 (uint32_t)&(EVENT_TIMER->EVENTS_COMPARE[0]), in hal_radio_enable_on_tick_ppi_config_and_enable()
67 (uint32_t)&(NRF_RADIO->TASKS_TXEN)); in hal_radio_enable_on_tick_ppi_config_and_enable()
70 NRF_PPI->CHG[SW_SWITCH_SINGLE_TIMER_TASK_GROUP_IDX] = in hal_radio_enable_on_tick_ppi_config_and_enable()
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/Zephyr-latest/doc/hardware/peripherals/can/
Dtransceiver.rst14 from the CAN controller to the bus-levels. The bus lines are called
16 The transmit wire from the controller to the transceiver is called CAN TX,
17 and the receive wire is called CAN RX.
18 These wires use the logic levels whereas the bus-level is interpreted
20 The bus can be either in the recessive (logical one) or dominant (logical zero)
23 To write a dominant bit to the bus, open-drain transistors tie CAN H to Vdd
25 The first and last node use a 120-ohm resistor between CAN H and CAN L to
27 This structure is called a wired-AND.
/Zephyr-latest/samples/sensor/ds18b20/
DREADME.rst1 .. zephyr:code-sample:: ds18b20
2 :name: DS18B20 1-Wire Temperature Sensor
3 :relevant-api: sensor_interface w1_sensor
11 `DS18B20`_ 1-Wire temperature sensor.
31 https://www.analog.com/media/en/technical-documentation/data-sheets/ds18b20.pdf
33 Boards with a built-in DS18B20 or a board-specific overlay
40 .. zephyr-app-commands::
41 :zephyr-app: samples/sensor/ds18b20
48 Make sure that you have an external circuit to provide an open-drain interface
49 for the 1-Wire bus.
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/Zephyr-latest/include/zephyr/drivers/
Dw1.h5 * SPDX-License-Identifier: Apache-2.0
10 * @brief Public 1-Wire Driver APIs
27 * @brief 1-Wire Interface
28 * @defgroup w1_interface 1-Wire Interface
46 (FOR_EACH(F1, (+), DT_SUPPORTS_DEP_ORDS(node_id)) - 1)
53 * @brief Defines the 1-Wire master settings types, which are runtime configurable.
74 /** Configuration common to all 1-Wire master implementations. */
80 /** Data common to all 1-Wire master implementations. */
118 struct w1_master_data *ctrl_data = (struct w1_master_data *)dev->data; in z_impl_w1_change_bus_lock()
119 const struct w1_driver_api *api = (const struct w1_driver_api *)dev->api; in z_impl_w1_change_bus_lock()
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/Zephyr-latest/drivers/w1/
Dw1_zephyr_serial.c4 * SPDX-License-Identifier: Apache-2.0
10 * @brief 1-Wire Bus Master driver using Zephyr serial interface.
12 * This driver implements the 1-Wire interface using an uart.
16 …* https://www.analog.com/en/resources/technical-articles/using-a-uart-to-implement-a-1wire-bus-mas…
54 /** UART device used for 1-Wire communication */
66 * Concurrently transmits and receives one 1-Wire bit
67 * by sending and receiving one uart byte
72 const struct w1_serial_config *cfg = dev->config; in serial_tx_rx()
81 while (uart_poll_in(cfg->uart_dev, &dummy) == 0) { in serial_tx_rx()
85 uart_poll_out(cfg->uart_dev, tx_data[i]); in serial_tx_rx()
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Dw1_net.c4 * SPDX-License-Identifier: Apache-2.0
8 * @brief 1-Wire network related functions.
27 * This function searches the next 1-Wire slave on the bus.
28 * It sets the found ROM and the last discrepancy in case more than one
30 * In case only one slave took part in the search, the discrepancy is set to
36 * @see https://www.analog.com/media/en/technical-documentation/app-notes/1wire-search-algorithm.pdf
41 * their own addresses' bit. This allows the master to branch through 64-bit
47 * bytes (big-endian) stored in rom_inv_64 are in inverse byte order.
62 * @retval -errno Negative error code in case of 1-wire read/write error.
124 (*rom_inv_64 & BIT64(id_bit_nr - 1)))) { in search_slave()
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/Zephyr-latest/include/zephyr/dt-bindings/spi/
Dspi.h4 * SPDX-License-Identifier: Apache-2.0
20 * Some controllers support half duplex transfer, which results in 3-wire usage.
33 * active the whole transfer. In TI, it's active only one serial clock period
/Zephyr-latest/samples/subsys/mgmt/osdp/
DREADME.rst1 .. _osdp-sample:
6 Open Supervised Device Protocol (OSDP) is an IEC standard (IEC 60839-11-5)
11 OSDP describes the communication protocol for interfacing one or more Peripheral
12 Devices (PD) to a Control Panel (CP) over a two-wire RS-485 multi-drop serial
19 too much resource requirements. The security is not top-notch (AES-128) but it
24 - LED
25 - Buzzer
26 - Keypad
27 - Output (GPIOs)
28 - Input Control (GPIOs)
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/Zephyr-latest/subsys/emul/espi/
Demul_espi_host.c4 * SPDX-License-Identifier: Apache-2.0
21 /** Data about the virtual wire */
23 /* Virtual wire signal */
25 /* The level(state) of the virtual wire */
27 /* The direction of the virtual wire. Possible values:
66 /** Run-time data used by the emulator */
72 /** Virtual Wires states, for one slave only.
73 * With multi-slaves config, the states should be saved per slave */
85 /* eSPI chip-select of the emulated device */
100 data->vw_state[i] = vw_state_default[i]; in emul_host_init_vw_state()
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/Zephyr-latest/dts/bindings/mipi-dbi/
Dzephyr,mipi-dbi-spi.yaml2 # SPDX-License-Identifier: Apache-2.0
5 MIPI-DBI Mode C compatible SPI controller. This driver emulates MIPI DBI
7 compatible: "zephyr,mipi-dbi-spi"
9 include: ["mipi-dbi-controller.yaml", "pinctrl-device.yaml"]
12 spi-dev:
19 dc-gpios:
20 type: phandle-array
22 Data/command gpio pin. Required when using 4 wire SPI mode (Mode C1).
25 reset-gpios:
26 type: phandle-array
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/Zephyr-latest/dts/bindings/i2c/
Datmel,sam-i2c-twim.yaml1 # Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
2 # SPDX-License-Identifier: Apache-2.0
7 The Atmel Two-wire Master Interface (TWIM) interconnects components on a
8 unique two-wire bus, made up of one clock line and one data line with speeds
9 of up to 3.4 Mbit/s, based on a byte-oriented transfer format. The TWIM is
20 std-clk-slew-lim = <0>;
21 std-clk-strength-low = "0.5";
22 std-data-slew-lim = <0>;
23 std-data-strength-low = "0.5";
25 hs-clk-slew-lim = <0>;
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/Zephyr-latest/boards/shields/p3t1755dp_ard_i2c/doc/
Dindex.rst9 P3T1755DP is a ±0.5 °C accurate temperature-to-digital converter
10 with a -40 °C to 125 °C range.
21 for different operation conditions: continuous conversion, one-shot mode
22 or shutdown mode. The device supports 2-wire serial I3C (up to 12.5 MHz)
25 For more information about P3T1755DP-ARD see these NXP documents:
27 - `Getting Started with the P3T1755DP-ARD Evaluation Board`_
28 - `P3T1755DP-ARD Evaluation Board User Manual`_
32 - Shield board p3t1755dp_ard in I3C mode
33 J10, J11, J12 3-5, the i3c addr is 0x4800000236152a0090
34 JP2, Jp3 1-2
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/Zephyr-latest/boards/shields/p3t1755dp_ard_i3c/doc/
Dindex.rst9 P3T1755DP is a ±0.5 °C accurate temperature-to-digital converter
10 with a -40 °C to 125 °C range.
21 for different operation conditions: continuous conversion, one-shot mode
22 or shutdown mode. The device supports 2-wire serial I3C (up to 12.5 MHz)
25 For more information about P3T1755DP-ARD see these NXP documents:
27 - `Getting Started with the P3T1755DP-ARD Evaluation Board`_
28 - `P3T1755DP-ARD Evaluation Board User Manual`_
32 - Shield board p3t1755dp_ard in I3C mode
33 J10, J11, J12 3-5, the i3c addr is 0x4800000236152a0090
34 JP2, Jp3 1-2
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/Zephyr-latest/boards/bytesatwork/bytesensi_l/
Dbytesensi_l.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
12 #include <zephyr/dt-bindings/gpio/gpio.h>
16 compatible = "bytesatwork,bytesensi-l";
22 zephyr,code-partition = &slot0_partition;
35 compatible = "fixed-partitions";
36 #address-cells = <1>;
37 #size-cells = <1>;
44 label = "image-0";
48 label = "image-1";
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/Zephyr-latest/doc/connectivity/bluetooth/
Dbluetooth-arch.rst1 .. _bluetooth-arch:
13 Zephyr supports mainly Bluetooth Low Energy (BLE), the low-power
18 .. _bluetooth-layers:
27 multiple (non real-time) network and transport protocols enabling
31 low-level, real-time protocol which provides, in conjunction with the Radio
32 Hardware, standard-interoperable over-the-air communication. The LL schedules
39 .. _bluetooth-hci:
54 .. _bluetooth-configs:
63 * **Single-chip configuration**: In this configuration, a single microcontroller
65 system-on-chip (SoC) implementation. In this case the BLE Host and the BLE
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/Zephyr-latest/drivers/espi/
Despi_npcx.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/espi/npcx_espi.h>
32 /* mapping table between eSPI reset signal and wake-up input */
77 ((struct espi_reg *)((const struct espi_npcx_config *)(dev)->config)->base)
94 /* Minimum delay before acknowledging a virtual wire */
132 /* eSPI Virtual Wire Input (Master-to-Slave) signals configuration structure */
134 enum espi_vwire_signal sig; /* Virtual Wire signal */
136 uint8_t bitmask; /* VW signal bits-mask */
140 /* eSPI Virtual Wire Output (Slave-to-Master) signals configuration structure */
142 enum espi_vwire_signal sig; /* Virtual Wire signal */
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/Zephyr-latest/drivers/led_strip/
Dws2812_spi.c6 * SPDX-License-Identifier: Apache-2.0
24 #include <zephyr/dt-bindings/led/led.h>
26 /* spi-one-frame and spi-zero-frame in DT are for 8-bit frames. */
32 * - mode 0 (the default), 8 bit, MSB first (arbitrary), one-line SPI
33 * - no shenanigans (don't hold CS, don't hold the device lock, this
52 return dev->config; in dev_cfg()
56 * Serialize an 8-bit color channel value into an equivalent sequence
57 * of SPI frames, MSbit first, where a one bit becomes SPI frame
66 buf[i] = color & BIT(7 - i) ? one_frame : zero_frame; in ws2812_spi_ser()
83 const uint8_t one = cfg->one_frame, zero = cfg->zero_frame; in ws2812_strip_update_rgb() local
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Dws2812_i2s.c5 * https://electronut.in/nrf52-i2s-ws2812/
7 * Note: the word "word" refers to a 32-bit integer unless otherwise stated.
11 * The I2S peripheral sends two 16-bit channel values for each clock period.
12 * A single LED color (8 data bits) will take up one 32-bit word or one LRCK
15 * SPDX-License-Identifier: Apache-2.0
28 #include <zephyr/dt-bindings/led/led.h>
49 /* Serialize an 8-bit color channel value into two 16-bit I2S values (or 1 32-bit
68 const struct ws2812_i2s_cfg *cfg = dev->config; in ws2812_strip_update_rgb()
69 const uint8_t sym_one = cfg->nibble_one; in ws2812_strip_update_rgb()
70 const uint8_t sym_zero = cfg->nibble_zero; in ws2812_strip_update_rgb()
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Dtlc59731.c4 * SPDX-License-Identifier: Apache-2.0
13 * TLC59731 is a 3-Channel, 8-Bit, PWM LED Driver
14 * With Single-Wire Interface (EasySet)
17 * them. At least one pulse must be sent every T_CYCLE, which can be
25 * A one is represented by an additional pulse between 275ns and 2.5us
26 * (half a cycle) after the first one. We need at least some delay to get to
99 rgb_write_bit(led_dev, data & BIT((idx--))); in rgb_write_data()
108 const struct tlc59731_cfg *tlc_conf = dev->config; in tlc59731_led_set_color()
109 const struct gpio_dt_spec *led_gpio = &tlc_conf->sdi_gpio; in tlc59731_led_set_color()
112 rgb_write_data(led_gpio, pixel->r); in tlc59731_led_set_color()
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/Zephyr-latest/samples/drivers/counter/maxim_ds3231/
DREADME.rst1 .. zephyr:code-sample:: ds3231
3 :relevant-api: counter_interface
5 Interact with a DS3231 real-time clock using the counter API and dedicated driver API.
10 The `DS3231`_ temperature-compensated real-time clock is a
11 high-precision (2 ppm) battery backed clock that maintains civil time
20 DS3231 has recorded a loss-of-oscillator::
22 ***** Booting Zephyr OS build zephyr-v1.14.0-2409-g322d53aedaa0 *****
37 Now 1563512509: 2019-07-19 05:01:49 Fri 200
47 synchronize the clock is 967 ms, and the whole second value of one
50 Set 2019-07-19 06:00:00.034000000 Fri 200 at 34 ms past: 0
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