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/Zephyr-Core-3.7.0/drivers/interrupt_controller/
Dintc_dw.h26 uint32_t irq_inten_l; /* offset 00 */
27 uint32_t irq_inten_h; /* offset 04 */
28 uint32_t irq_intmask_l; /* offset 08 */
29 uint32_t irq_intmask_h; /* offset 0C */
30 uint32_t irq_intforce_l; /* offset 10 */
31 uint32_t irq_intforce_h; /* offset 14 */
32 uint32_t irq_rawstatus_l; /* offset 18 */
33 uint32_t irq_rawstatus_h; /* offset 1c */
34 uint32_t irq_status_l; /* offset 20 */
35 uint32_t irq_status_h; /* offset 24 */
[all …]
/Zephyr-Core-3.7.0/soc/arm/beetle/
Dsoc_registers.h17 /* Offset: 0x000 (r/w) remap control register */
19 /* Offset: 0x004 (r/w) pmu control register */
21 /* Offset: 0x008 (r/w) reset option register */
23 /* Offset: 0x00c (r/w) emi control register */
25 /* Offset: 0x010 (r/w) reset information register */
28 /* Offset: 0x020 (r/w)AHB peripheral access control set */
30 /* Offset: 0x024 (r/w)AHB peripheral access control clear */
33 /* Offset: 0x030 (r/w)APB peripheral access control set */
35 /* Offset: 0x034 (r/w)APB peripheral access control clear */
38 /* Offset: 0x040 (r/w) main clock control register */
[all …]
/Zephyr-Core-3.7.0/soc/nxp/rw/
Dpinctrl_defs.h12 #define IOMUX_OFFSET_ENABLE(offset, enable, shift) \ argument
13 ((((offset) << 1) | (enable & 0x1)) << shift)
14 #define IOMUX_SCTIMER_OUT_CLR(offset, enable) \ argument
15 IOMUX_OFFSET_ENABLE(offset, enable, 0)
16 #define IOMUX_SCTIMER_IN_CLR(offset, enable) \ argument
17 IOMUX_OFFSET_ENABLE(offset, enable, 4)
18 #define IOMUX_CTIMER_CLR(offset, enable)\ argument
19 IOMUX_OFFSET_ENABLE(offset, enable, 8)
37 /* Pin mux type and gpio offset macros */
92 IOMUX_CTIMER_CLR(0ULL, 1ULL) | /* CTIMER offset to clear */ \
[all …]
/Zephyr-Core-3.7.0/tests/subsys/debug/symtab/src/
Dmain.c30 const uintptr_t last_addr = first_addr + symtab->entries[symtab->length - 1].offset; in ZTEST()
31 uint32_t offset; in ZTEST() local
38 offset = -1; in ZTEST()
39 symbol_name = symtab_find_symbol_name((uintptr_t)main, &offset); in ZTEST()
41 zassert_equal(offset, 0); in ZTEST()
61 * [SYMBOL ADDR] | Name Offset
80 uint32_t offset; in ZTEST() local
84 offset = -1; in ZTEST()
85 symbol_name = symtab_find_symbol_name(first_addr - 1, &offset); in ZTEST()
87 zassert_equal(offset, 0); in ZTEST()
[all …]
/Zephyr-Core-3.7.0/subsys/net/lib/lwm2m/
Dbuf_util.h37 uint16_t offset, uint8_t *src, uint16_t src_len) in buf_insert() argument
47 /* shift everything in fbuf after offset by len */ in buf_insert()
48 memmove(dst + offset + src_len, dst + offset, *dst_len - offset); in buf_insert()
50 /* copy src into fbuf at offset */ in buf_insert()
51 memcpy(dst + offset, src, src_len); in buf_insert()
58 uint16_t *offset) in buf_read() argument
64 if (*offset + len > src_len) { in buf_read()
69 /* copy data at offset into dst */ in buf_read()
70 memcpy(dst, src + *offset, len); in buf_read()
73 *offset += len; in buf_read()
[all …]
/Zephyr-Core-3.7.0/soc/intel/intel_adsp/ace/include/ace30_ptl/
Dadsp_shim.h20 uint32_t dfspsreq; /* Offset: 0x00 */
22 uint32_t dfspsrsp; /* Offset: 0x10 */
24 uint32_t svcfg; /* Offset: 0x18 */
25 uint32_t dfltrc; /* Offset: 0x1c */
37 uint32_t dfpmccap; /* Offset: 0x00 */
38 uint32_t dfhrosccf; /* Offset: 0x04 */
39 uint32_t dfxosccf; /* Offset: 0x08 */
40 uint32_t dflrosccf; /* Offset: 0x0c */
41 uint32_t dfsiorosccf; /* Offset: 0x10 */
42 uint32_t dfhsiorosccf; /* Offset: 0x14 */
[all …]
/Zephyr-Core-3.7.0/arch/arm/core/
Delf.c74 uint32_t sym_base_addr, const char *sym_name, int32_t *offset) in prel31_decode() argument
78 *offset = sign_extend(*(int32_t *)loc, SHIFT_PREL31_SIGN); in prel31_decode()
79 *offset += sym_base_addr - loc; in prel31_decode()
80 if (*offset >= PREL31_UPPER_BOUNDARY || *offset < PREL31_LOWER_BOUNDARY) { in prel31_decode()
91 static inline void prel31_reloc(uint32_t loc, int32_t *offset) in prel31_reloc() argument
94 *(uint32_t *)loc |= *offset & GENMASK(30, 0); in prel31_reloc()
101 int32_t offset; in prel31_handler() local
103 ret = prel31_decode(reloc_type, loc, sym_base_addr, sym_name, &offset); in prel31_handler()
105 prel31_reloc(loc, &offset); in prel31_handler()
112 uint32_t sym_base_addr, const char *sym_name, int32_t *offset) in jumps_decode() argument
[all …]
/Zephyr-Core-3.7.0/tests/subsys/fs/multi-fs/src/
Dtest_ram_backend.c21 static int test_flash_ram_erase(const struct device *dev, off_t offset, in test_flash_ram_erase() argument
25 off_t end_offset = offset + len; in test_flash_ram_erase()
27 zassert_true(offset >= 0, "invalid offset"); in test_flash_ram_erase()
28 zassert_true(offset + len <= TEST_PARTITION_SIZE, in test_flash_ram_erase()
31 while (offset < end_offset) { in test_flash_ram_erase()
32 flash_get_page_info_by_offs(dev, offset, &info); in test_flash_ram_erase()
34 offset = info.start_offset + info.size; in test_flash_ram_erase()
40 static int test_flash_ram_write(const struct device *dev, off_t offset, in test_flash_ram_write() argument
43 zassert_true(offset >= 0, "invalid offset"); in test_flash_ram_write()
44 zassert_true(offset + len <= TEST_PARTITION_SIZE, in test_flash_ram_write()
[all …]
/Zephyr-Core-3.7.0/include/zephyr/bluetooth/audio/
Dvocs.h3 * @brief Bluetooth Volume Offset Control Service (VOCS) APIs.
16 * @brief Volume Offset Control Service (VOCS)
18 * @defgroup bt_gatt_vocs Volume Offset Control Service (VOCS)
26 * The Volume Offset Control Service is a secondary service, and as such should not be used own its
30 * Note that the API abstracts away the change counter in the volume offset control state and will
45 * @name Volume Offset Control Service Error codes
50 * Offset State characteristic.
60 * @name Volume Offset Control Service offset limits
63 /** Minimum offset value */
65 /** Maximum offset value */
[all …]
/Zephyr-Core-3.7.0/include/zephyr/drivers/gpio/
Dgpio_cmsdk_ahb.h17 /* Offset: 0x000 (r/w) data register */
19 /* Offset: 0x004 (r/w) data output latch register */
22 /* Offset: 0x010 (r/w) output enable set register */
24 /* Offset: 0x014 (r/w) output enable clear register */
26 /* Offset: 0x018 (r/w) alternate function set register */
28 /* Offset: 0x01c (r/w) alternate function clear register */
30 /* Offset: 0x020 (r/w) interrupt enable set register */
32 /* Offset: 0x024 (r/w) interrupt enable clear register */
34 /* Offset: 0x028 (r/w) interrupt type set register */
36 /* Offset: 0x02c (r/w) interrupt type clear register */
[all …]
/Zephyr-Core-3.7.0/drivers/counter/
Ddualtimer_cmsdk_apb.h16 /* Offset: 0x000 (R/W) Timer 1 Load */
18 /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
20 /* Offset: 0x008 (R/W) Timer 1 Control */
22 /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
24 /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
26 /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
28 /* Offset: 0x018 (R/W) Background Load Register */
32 /* Offset: 0x020 (R/W) Timer 2 Load */
34 /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
36 /* Offset: 0x028 (R/W) Timer 2 Control */
[all …]
/Zephyr-Core-3.7.0/soc/intel/intel_adsp/ace/include/ace15_mtpm/
Dadsp_shim.h21 uint32_t dfspsreq; /* Offset: 0x00 */
23 uint32_t dfspsrsp; /* Offset: 0x10 */
25 uint32_t svcfg; /* Offset: 0x18 */
26 uint32_t dfltrc; /* Offset: 0x1c */
39 uint32_t dfpmccap; /* Offset: 0x00 */
42 uint32_t dfhrosccf; /* Offset: 0x04 */
45 uint32_t dfxosccf; /* Offset: 0x08 */
48 uint32_t dflrosccf; /* Offset: 0x0c */
51 uint32_t dfsiorosccf; /* Offset: 0x10 */
54 uint32_t dfhsiorosccf; /* Offset: 0x14 */
[all …]
/Zephyr-Core-3.7.0/soc/intel/intel_adsp/ace/include/ace20_lnl/
Dadsp_shim.h21 uint32_t dfspsreq; /* Offset: 0x00 */
23 uint32_t dfspsrsp; /* Offset: 0x10 */
25 uint32_t svcfg; /* Offset: 0x18 */
26 uint32_t dfltrc; /* Offset: 0x1c */
39 uint32_t dfpmccap; /* Offset: 0x00 */
42 uint32_t dfhrosccf; /* Offset: 0x04 */
45 uint32_t dfxosccf; /* Offset: 0x08 */
48 uint32_t dflrosccf; /* Offset: 0x0c */
51 uint32_t dfsiorosccf; /* Offset: 0x10 */
54 uint32_t dfhsiorosccf; /* Offset: 0x14 */
[all …]
/Zephyr-Core-3.7.0/drivers/flash/
Dflash_gd32_v2.c96 static int gd32_fmc_v2_bank0_write(off_t offset, const void *data, size_t len) in gd32_fmc_v2_bank0_write() argument
98 flash_prg_t *prg_flash = (flash_prg_t *)((uint8_t *)SOC_NV_FLASH_ADDR + offset); in gd32_fmc_v2_bank0_write()
168 static int gd32_fmc_v2_bank0_erase_block(off_t offset, size_t size) in gd32_fmc_v2_bank0_erase_block() argument
170 uint32_t page_addr = SOC_NV_FLASH_ADDR + offset; in gd32_fmc_v2_bank0_erase_block()
211 static int gd32_fmc_v2_bank1_write(off_t offset, const void *data, size_t len) in gd32_fmc_v2_bank1_write() argument
213 flash_prg_t *prg_flash = (flash_prg_t *)((uint8_t *)SOC_NV_FLASH_ADDR + offset); in gd32_fmc_v2_bank1_write()
283 static int gd32_fmc_v2_bank1_erase_block(off_t offset, size_t size) in gd32_fmc_v2_bank1_erase_block() argument
285 uint32_t page_addr = SOC_NV_FLASH_ADDR + offset; in gd32_fmc_v2_bank1_erase_block()
302 bool flash_gd32_valid_range(off_t offset, uint32_t len, bool write) in flash_gd32_valid_range() argument
304 if ((offset > SOC_NV_FLASH_SIZE) || in flash_gd32_valid_range()
[all …]
Dflash_sam.c55 static bool sam_flash_validate_offset_len(off_t offset, size_t len) in sam_flash_validate_offset_len() argument
57 if (offset < 0) { in sam_flash_validate_offset_len()
61 if ((offset + len) < len) { in sam_flash_validate_offset_len()
73 static bool sam_flash_offset_is_on_write_page_boundary(off_t offset) in sam_flash_offset_is_on_write_page_boundary() argument
75 return sam_flash_aligned(offset, SAM_FLASH_WRITE_PAGE_SIZE); in sam_flash_offset_is_on_write_page_boundary()
137 static bool sam_flash_section_is_within_area(const struct device *dev, off_t offset, size_t len) in sam_flash_section_is_within_area() argument
141 if ((offset + ((off_t)len)) < offset) { in sam_flash_section_is_within_area()
145 if ((offset >= 0) && ((offset + len) <= config->area_size)) { in sam_flash_section_is_within_area()
150 (size_t)offset, (size_t)(offset + len), (size_t)config->area_size); in sam_flash_section_is_within_area()
156 off_t offset, size_t len) in sam_flash_section_is_aligned_with_write_block_size() argument
[all …]
Dflash_sam0.c99 static int flash_sam0_valid_range(off_t offset, size_t len) in flash_sam0_valid_range() argument
101 if (offset < 0) { in flash_sam0_valid_range()
102 LOG_WRN("0x%lx: before start of flash", (long)offset); in flash_sam0_valid_range()
105 if ((offset + len) > CONFIG_FLASH_SIZE * 1024) { in flash_sam0_valid_range()
106 LOG_WRN("0x%lx: ends past the end of flash", (long)offset); in flash_sam0_valid_range()
124 static int flash_sam0_check_status(off_t offset) in flash_sam0_check_status() argument
141 LOG_ERR("programming error at 0x%lx", (long)offset); in flash_sam0_check_status()
144 LOG_ERR("lock error at 0x%lx", (long)offset); in flash_sam0_check_status()
147 LOG_ERR("NVM error at 0x%lx", (long)offset); in flash_sam0_check_status()
161 static int flash_sam0_write_page(const struct device *dev, off_t offset, in flash_sam0_write_page() argument
[all …]
Dflash_gecko.c33 static bool write_range_is_valid(off_t offset, uint32_t size);
34 static bool read_range_is_valid(off_t offset, uint32_t size);
35 static int erase_flash_block(off_t offset, size_t size);
38 static int flash_gecko_read(const struct device *dev, off_t offset, in flash_gecko_read() argument
42 if (!read_range_is_valid(offset, size)) { in flash_gecko_read()
50 memcpy(data, (uint8_t *)CONFIG_FLASH_BASE_ADDRESS + offset, size); in flash_gecko_read()
55 static int flash_gecko_write(const struct device *dev, off_t offset, in flash_gecko_write() argument
63 if (!write_range_is_valid(offset, size)) { in flash_gecko_write()
74 address = (uint8_t *)CONFIG_FLASH_BASE_ADDRESS + offset; in flash_gecko_write()
86 static int flash_gecko_erase(const struct device *dev, off_t offset, in flash_gecko_erase() argument
[all …]
/Zephyr-Core-3.7.0/drivers/mm/
Dmm_drv_common.c49 size_t offset; in sys_mm_drv_is_virt_region_mapped() local
52 for (offset = 0; offset < size; offset += CONFIG_MM_DRV_PAGE_SIZE) { in sys_mm_drv_is_virt_region_mapped()
53 uint8_t *va = (uint8_t *)virt + offset; in sys_mm_drv_is_virt_region_mapped()
66 size_t offset; in sys_mm_drv_is_virt_region_unmapped() local
69 for (offset = 0; offset < size; offset += CONFIG_MM_DRV_PAGE_SIZE) { in sys_mm_drv_is_virt_region_unmapped()
70 uint8_t *va = (uint8_t *)virt + offset; in sys_mm_drv_is_virt_region_unmapped()
86 size_t offset; in sys_mm_drv_simple_map_region() local
97 for (offset = 0; offset < size; offset += CONFIG_MM_DRV_PAGE_SIZE) { in sys_mm_drv_simple_map_region()
98 uint8_t *va = (uint8_t *)virt + offset; in sys_mm_drv_simple_map_region()
99 uintptr_t pa = phys + offset; in sys_mm_drv_simple_map_region()
[all …]
/Zephyr-Core-3.7.0/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/
Dservice_c_2_1.c161 * @param offset Offset to start reading from
168 uint16_t len, uint16_t offset) in read_value_v10() argument
172 return bt_gatt_attr_read(conn, attr, buf, len, offset, value, in read_value_v10()
183 * @param offset Offset to start reading from
190 uint16_t len, uint16_t offset) in read_str_value() argument
194 return bt_gatt_attr_read(conn, attr, buf, len, offset, value, in read_str_value()
205 * @param offset Offset to start writing from
213 uint16_t len, uint16_t offset, uint8_t flags) in write_value_v2() argument
217 if (offset >= sizeof(value_v2_value)) in write_value_v2()
219 if (offset + len > sizeof(value_v2_value)) in write_value_v2()
[all …]
Dservice_b_5_1.c57 * @param offset Offset to start reading from
64 uint16_t len, uint16_t offset) in read_value_v8() argument
68 return bt_gatt_attr_read(conn, attr, buf, len, offset, value, in read_value_v8()
79 * @param offset Offset to start writing from
87 uint16_t len, uint16_t offset, uint8_t flags) in write_value_v8() argument
91 if (offset >= sizeof(value_v8_value)) in write_value_v8()
93 if (offset + len > sizeof(value_v8_value)) in write_value_v8()
96 memcpy(value + offset, buf, len); in write_value_v8()
108 * @param offset Offset to start reading from
115 uint16_t len, uint16_t offset) in read_des_v8d1() argument
[all …]
Dservice_f_1.c96 * @param offset Offset to start reading from
103 uint16_t len, uint16_t offset) in read_str_value() argument
107 return bt_gatt_attr_read(conn, attr, buf, len, offset, value, in read_str_value()
118 * @param offset Offset to start reading from
125 uint16_t len, uint16_t offset) in read_value_v15() argument
129 return bt_gatt_attr_read(conn, attr, buf, len, offset, value, in read_value_v15()
140 * @param offset Offset to start writing from
148 uint16_t len, uint16_t offset, uint8_t flags) in write_value_v15() argument
152 if (offset >= sizeof(value_v15_value)) in write_value_v15()
154 if (offset + len > sizeof(value_v15_value)) in write_value_v15()
[all …]
/Zephyr-Core-3.7.0/tests/net/lib/lwm2m/content_plain_text/src/
Dmain.c46 test_packet.offset = sizeof(test_payload); in test_prepare_nomem()
55 test_packet.offset = sizeof(test_payload); in test_prepare_nodata()
56 test_in.offset = sizeof(test_payload); in test_prepare_nodata()
62 test_packet.offset = strlen(payload) + 1; in test_payload_set()
63 test_in.offset = 1; /* Payload marker */ in test_payload_set()
70 uint16_t offset = 0; in ZTEST() local
78 zassert_mem_equal(test_out.out_cpkt->data + offset, in ZTEST()
83 offset += strlen(expected_payload[i]); in ZTEST()
84 zassert_equal(test_out.out_cpkt->offset, offset, in ZTEST()
85 "Invalid packet offset"); in ZTEST()
[all …]
/Zephyr-Core-3.7.0/drivers/ethernet/
Deth_smsc911x_priv.h53 /* Receive FIFO Ports (offset 0x0) */
56 /* Transmit FIFO Ports (offset 0x20) */
60 /* Receive FIFO status port (offset 0x40) */
62 /* Receive FIFO status peek (offset 0x44) */
64 /* Transmit FIFO status port (offset 0x48) */
66 /* Transmit FIFO status peek (offset 0x4C) */
69 /* Chip ID and Revision (offset 0x50) */
71 /* Main Interrupt Configuration (offset 0x54) */
73 /* Interrupt Status (offset 0x58) */
75 /* Interrupt Enable Register (offset 0x5C) */
[all …]
/Zephyr-Core-3.7.0/soc/arm/mps2/
Dsoc_registers.h20 /* Offset: 0x000 LED connections */
22 /* Offset: 0x004 RESERVED */
24 /* Offset: 0x008 Buttons */
26 /* Offset: 0x00c RESERVED */
28 /* Offset: 0x010 1Hz up counter */
30 /* Offset: 0x014 100Hz up counter */
32 /* Offset: 0x018 Cycle up counter */
34 /* Offset: 0x01c Reload value for prescale counter */
36 /* Offset: 0x020 32-bit Prescale counter */
38 /* Offset: 0x024 RESERVED */
[all …]
/Zephyr-Core-3.7.0/drivers/dma/
Ddma_pl330.c162 uint32_t offset = 0, ccr; in dma_pl330_setup_ch() local
175 offset += dma_pl330_gen_mov(dma_exec_addr, in dma_pl330_setup_ch()
178 offset += dma_pl330_gen_mov(dma_exec_addr + offset, in dma_pl330_setup_ch()
183 offset += dma_pl330_gen_mov(dma_exec_addr + offset, in dma_pl330_setup_ch()
192 dma_pl330_gen_op(OP_DMA_LOOP_COUNT1, dma_exec_addr + offset, in dma_pl330_setup_ch()
194 offset = offset + 2; in dma_pl330_setup_ch()
195 dma_pl330_gen_op(OP_DMA_LOOP, dma_exec_addr + offset, in dma_pl330_setup_ch()
197 offset = offset + 2; in dma_pl330_setup_ch()
198 lp1_start = offset; in dma_pl330_setup_ch()
199 lp0_start = offset; in dma_pl330_setup_ch()
[all …]

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