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/Zephyr-latest/dts/bindings/power-domain/
Dpower-domain-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "power-domain-gpio"
8 include: power-domain.yaml
11 enable-gpios:
12 type: phandle-array
18 provide the GPIO polarity and open-drain status in the phandle
19 selector. The Linux enable-active-high and gpio-open-drain
22 startup-delay-us:
27 off-on-delay-us:
30 description: Off delay time, in microseconds
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/Zephyr-latest/tests/drivers/regulator/fixed/dts/
Dtest_common.dtsi3 * SPDX-License-Identifier: Apache-2.0
8 compatible = "regulator-fixed";
9 regulator-name = "test";
10 regulator-boot-on;
11 startup-delay-us = <1000000>;
12 off-on-delay-us = <20000>;
16 compatible = "test-regulator-fixed";
/Zephyr-latest/dts/bindings/regulator/
Dregulator-fixed.yaml1 # Copyright 2019-2020 Peter Bigot Consulting, LLC
3 # SPDX-License-Identifier: Apache-2.0
8 - name: base.yaml
9 - name: regulator.yaml
10 property-allowlist:
11 - regulator-name
12 - regulator-boot-on
13 - regulator-always-on
14 - regulator-min-microvolt
15 - regulator-max-microvolt
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Dregulator.yaml1 # Copyright 2019-2020, Peter Bigot Consulting, LLC
3 # SPDX-License-Identifier: Apache-2.0
14 regulator-name:
18 regulator-init-microvolt:
22 regulator-min-microvolt:
26 regulator-max-microvolt:
30 regulator-microvolt-offset:
34 regulator-init-microamp:
38 regulator-min-microamp:
42 regulator-max-microamp:
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Dnordic,npm1300-regulator.yaml2 # SPDX-License-Identifier: Apache-2.0
16 compatible = "nordic,npm1300-regulator";
33 compatible: "nordic,npm1300-regulator"
38 dvs-gpios:
39 type: phandle-array
47 The effect of the mode change is defined by the enable-gpios
50 child-binding:
52 - name: regulator.yaml
53 property-allowlist:
54 - regulator-always-on
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Dadi,adp5360-regulator.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The PMIC has one buck converter and one buck-boost converter. Both need to be
16 compatible = "adi,adp5360-regulator";
27 compatible: "adi,adp5360-regulator"
31 child-binding:
33 - name: regulator.yaml
34 property-allowlist:
35 - regulator-always-on
36 - regulator-boot-on
37 - regulator-boot-off
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/Zephyr-latest/boards/olimex/olimex_esp32_evb/
Dolimex_esp32_evb_procpu.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "olimex_esp32_evb-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 model = "Olimex ESP32-EVB";
16 compatible = "olimex,esp32-evb", "espressif,esp32-wroom-32e", "espressif,esp32";
20 zephyr,shell-uart = &uart0;
23 zephyr,code-partition = &slot0_partition;
24 zephyr,bt-hci = &esp32_bt_hci;
33 compatible = "gpio-keys";
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/Zephyr-latest/soc/nuvoton/npcx/common/
Dpower.c4 * SPDX-License-Identifier: Apache-2.0
17 * +--------------------------------------------------------------------------+
19 * |--------------------------------------------------------------------------|
20 * | Active | On | On | On | Active | Active | On | On |
21 * | Idle (wfi) | On | On | On | Wait | Active | On | On |
22 * | Sleep | On | On | Stop | Stop | Preserved | On | On |
23 * | Deep Sleep | On | Stop | Stop | Stop | Power Down | On | On |
24 * | Stand-By | Off | Off | Off | Off | Off | Off | On |
25 * +--------------------------------------------------------------------------+
27 * LFCLK - Low-Frequency Clock. Its frequency is fixed to 32kHz.
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/Zephyr-latest/drivers/led_strip/
Dtlc59731.c4 * SPDX-License-Identifier: Apache-2.0
13 * TLC59731 is a 3-Channel, 8-Bit, PWM LED Driver
14 * With Single-Wire Interface (EasySet)
16 * The EasySet protocol is based on short pulses and the time between
18 * between 1.67us and 50us. We want to go as fast as possible, but
19 * delays under 1us don't work very well, so we settle on 5us for the
21 * A pulse must be high for at least 14ns. In practice, turning a GPIO on
22 * and immediately off again already takes longer than that, so no delay
25 * A one is represented by an additional pulse between 275ns and 2.5us
26 * (half a cycle) after the first one. We need at least some delay to get to
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/Zephyr-latest/tests/kernel/timer/timer_behavior/src/
Djitter_drift.c4 * SPDX-License-Identifier: Apache-2.0
31 * auto-restart feature based on its period argument.
68 * the timer and relying solely on the timer's start delay argument to
114 TC_PRINT("WARNING: Caught a timer wrap-around !\n"); in periodic_diff()
118 return later - earlier; in periodic_diff()
187 (double)total_cycles / (double)(CONFIG_TIMER_TEST_SAMPLES - periodic_rollovers); in do_test_using()
189 (double)(CONFIG_TIMER_TEST_SAMPLES - periodic_rollovers); in do_test_using()
197 double mean_cyc_diff = (double)diff - mean_cyc; in do_test_using()
198 double mean_us_diff = cycles_to_us(diff) - mean_us; in do_test_using()
208 variance_us = variance_us / (double)(CONFIG_TIMER_TEST_SAMPLES - periodic_rollovers); in do_test_using()
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/Zephyr-latest/drivers/fpga/
Dfpga_ice40_bitbang.c5 * SPDX-License-Identifier: Apache-2.0
30 * restore the default pinctrl settings. On some higher-end microcontrollers
34 * However, on lower-end microcontrollers, the amount of time that elapses
36 * leaves us with the bitbanging option. Of course, on lower-end
40 * in order to bitbang on lower-end microcontrollers, we actually require
56 * This is a calibrated delay loop used to achieve a 1 MHz SPI_CLK frequency
61 * lattice,ice40-fpga.yaml for details.
65 for (; n > 0; --n) { in fpga_ice40_delay()
70 static void fpga_ice40_send_clocks(size_t delay, volatile gpio_port_pins_t *set, in fpga_ice40_send_clocks() argument
73 for (; n > 0; --n) { in fpga_ice40_send_clocks()
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Dfpga_ice40_spi.c4 * SPDX-License-Identifier: Apache-2.0
30 struct fpga_ice40_data *data = dev->data; in fpga_ice40_load()
32 const struct fpga_ice40_config *config = dev->config; in fpga_ice40_load()
35 memcpy(&bus, &config->bus, sizeof(bus)); in fpga_ice40_load()
45 if (data->loaded && crc == data->crc) { in fpga_ice40_load()
46 LOG_WRN("already loaded with image CRC32c: 0x%08x", data->crc); in fpga_ice40_load()
49 key = k_spin_lock(&data->lock); in fpga_ice40_load()
52 data->crc = 0; in fpga_ice40_load()
53 data->loaded = false; in fpga_ice40_load()
54 fpga_ice40_crc_to_str(0, data->info); in fpga_ice40_load()
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/Zephyr-latest/drivers/auxdisplay/
Dauxdisplay_jhd1313.c4 * Copyright (c) 2022-2023 Jamie McCrae
6 * SPDX-License-Identifier: Apache-2.0
79 { 0, 0, 0 }, /* Off */
95 const struct auxdisplay_jhd1313_config *config = dev->config; in auxdisplay_jhd1313_print()
102 rc = i2c_write_dt(&config->bus, buf, sizeof(buf)); in auxdisplay_jhd1313_print()
112 const struct auxdisplay_jhd1313_config *config = dev->config; in auxdisplay_jhd1313_cursor_position_set()
116 return -EINVAL; in auxdisplay_jhd1313_cursor_position_set()
128 return i2c_write_dt(&config->bus, data, 2); in auxdisplay_jhd1313_cursor_position_set()
134 const struct auxdisplay_jhd1313_config *config = dev->config; in auxdisplay_jhd1313_clear()
137 rc = i2c_write_dt(&config->bus, clear, sizeof(clear)); in auxdisplay_jhd1313_clear()
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/Zephyr-latest/drivers/display/
Ddisplay_hx8394.c4 * SPDX-License-Identifier: Apache-2.0
149 0x73, /* SPON delay */
150 0x74, /* SPOFF delay */
151 0x73, /* CON delay */
152 0x74, /* COFF delay */
153 0x73, /* CON1 delay */
154 0x74, /* COFF1 delay */
159 0x00, /* DX2 off, EQ off, EQ_MI off */
160 0x3F, /* DX2 off period setting */
161 0x73, /* SPON_MPU delay */
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/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
35 * 32768 Hz period is 30.518 us
99 uint32_t RSVD4[(0x00c0 - 0x0094) / 4];
170 #define XEC_CC_VBATR_CS_DI32_VTR_OFF BIT(18) /* disable silicon OSC when VTR off */
192 uint8_t core_clk_div; /* Cortex-M4 clock divider (CPU and NVIC) */
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/Zephyr-latest/drivers/timer/
Dcortex_m_systick.c4 * SPDX-License-Identifier: Apache-2.0
20 #define MAX_TICKS ((k_ticks_t)(COUNTER_MAX / CYC_PER_TICK) - 1)
25 * reliably" -- it becomes the minimum value of the LOAD register, and
61 * Additions/subtractions/comparisons of 64-bits values on 32-bits systems
63 * cycle_count and announced_cycles is stored in a 32-bit variable before
84 * case because the Cortex-m SysTick is not clocked in the low power
102 * re-program the SysTick.LOAD register, in sys_clock_set_timeout().
109 * - reprogramming of SysTick.LOAD must be clearing the SysTick.COUNTER
111 * - ISR must be clearing the 'overflow_cyc' counter.
112 * - no more than one counter-wrap has occurred between
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/Zephyr-latest/subsys/bluetooth/mesh/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
8 depends on BT_OBSERVER && BT_BROADCASTER
11 features that are available may depend on other features
31 depends on BT_MESH_GATT
97 depends on BT_CTLR_ADV_EXT || !HAS_BT_CTLR
98 depends on BT_EXT_ADV
113 bool "Mesh-specific workqueue"
116 mesh-specific workqueue. This will ensure that messages are always sent.
117 The application needs to ensure the mesh-specific workqueue size is large
130 CONFIG_BT_BUF_CMD_TX_COUNT, the host returns -ENOBUFS immediately
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/Zephyr-latest/doc/security/
Dsecure-coding.rst6 Traditionally, microcontroller-based systems have not placed much
7 emphasis on security.
11 this. Now, code running on small microcontrollers often has access to
35 a section on `Secure development knowledge`_, which
36 gives basic requirements that a developer working on the project will
46 documentation about how security-sensitive issues are handled by the
60 - **Open design** as a design guideline incorporates the maxim that
61 protection mechanisms cannot be kept secret on any system in
62 widespread use. Instead of relying on secret, custom-tailored
66 - **Economy of mechanism** specifies that the underlying design of a
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/Zephyr-latest/drivers/sdhc/
Dimx_usdhc.c4 * SPDX-License-Identifier: Apache-2.0
101 struct usdhc_data *data = dev->data; in transfer_complete_cb()
104 data->transfer_status |= TRANSFER_DATA_FAILED; in transfer_complete_cb()
106 data->transfer_status |= TRANSFER_DATA_COMPLETE; in transfer_complete_cb()
108 data->transfer_status |= TRANSFER_CMD_FAILED; in transfer_complete_cb()
110 data->transfer_status |= TRANSFER_CMD_COMPLETE; in transfer_complete_cb()
112 k_sem_give(&data->transfer_sem); in transfer_complete_cb()
119 struct usdhc_data *data = dev->data; in sdio_interrupt_cb()
121 if (data->sdhc_cb) { in sdio_interrupt_cb()
122 data->sdhc_cb(dev, SDHC_INT_SDIO, data->sdhc_cb_user_data); in sdio_interrupt_cb()
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/Zephyr-latest/subsys/bluetooth/controller/ll_sw/openisa/hal/RV32M1/radio/
Dradio.c2 * Copyright (c) 2016 - 2019 Nordic Semiconductor ASA
4 * Copyright 2019 - 2020 NXP
6 * SPDX-License-Identifier: Apache-2.0
43 #define RADIO_AESCCM_HDR_MASK 0xE3 /* AES-CCM: NESN, SN, MD bits masked to 0 */
44 #define RADIO_PDU_LEN_MAX (BIT(8) - 1)
46 ((bytes) * 8 >> (__builtin_ffs(bits_per_usec) - 1))
48 /* us values */
52 #define RX_WTMRK 5 /* (AA + PDU header) - 1 */
66 #define RADIO_DISABLE_TMR 4 /* us */
68 /* Delay needed in order to enter Manual DSM.
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/Zephyr-latest/include/zephyr/bluetooth/
Dconn.h6 * Copyright (c) 2015-2016 Intel Corporation
8 * SPDX-License-Identifier: Apache-2.0
73 * Connection Interval: 30-50 ms
152 /** Maximum Link Layer transmission payload time in us. */
156 /** Maximum Link Layer reception payload time in us. */
164 /** Maximum Link Layer transmission payload time in us. */
171 * @param _tx_max_time Maximum Link Layer transmission payload time in us.
182 * @param _tx_max_time Maximum Link Layer transmission payload time in us.
208 * after a packet containing a Link Layer PDU with a non-zero Length
224 * a packet containing a Link Layer PDU with a non-zero Length
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/Zephyr-latest/include/zephyr/
Dkernel.h4 * SPDX-License-Identifier: Apache-2.0
53 #define K_PRIO_COOP(x) (-(CONFIG_NUM_COOP_PRIORITIES - (x)))
56 #define K_HIGHEST_THREAD_PRIO (-CONFIG_NUM_COOP_PRIORITIES)
60 #define K_LOWEST_APPLICATION_THREAD_PRIO (K_LOWEST_THREAD_PRIO - 1)
126 * @brief Iterate over all the threads in running on specified cpu.
129 * but it only loops through the threads running on specified cpu only.
188 * @brief Iterate over the threads in running on current cpu without locking.
192 * running on specified cpu. If CONFIG_SMP is not defined the
245 * bits, arch-specific use high bits.
289 * from within a user-provided callback they have been invoked.
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/Zephyr-latest/tests/kernel/timer/timer_api/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
20 #define WITHIN_ERROR(var, target, epsilon) (llabs((int64_t) ((target) - (var))) <= (epsilon))
25 * end up being off by a tick depending on the relative error between
32 /* On Nordic SOCs one or both of the tick and busy-wait clocks may
33 * derive from sources that have slews that sum to +/- 13%.
37 /* On other platforms assume the clocks are perfectly aligned. */
44 * larger or smaller than expected by a value that depends on the slew
96 * slow CPUs) for us to arrive at the uptime check above too in interval_check()
99 * one-ticks deltas (NOT one two-tick delta!) in interval_check()
221 busy_wait_ms(DURATION + PERIOD * (EXPIRE_TIMES - 1) + PERIOD / 2); in ZTEST_USER()
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/Zephyr-latest/doc/services/logging/
Dindex.rst17 - Deferred logging reduces the time needed to log a message by shifting time
20 - Multiple backends supported (up to 9 backends).
21 - Custom frontend support. It can work together with backends.
22 - Compile time filtering on module level.
23 - Run time filtering independent for each backend.
24 - Additional run time filtering on module instance level.
25 - Timestamping with user provided function. Timestamp can have 32 or 64 bits.
26 - Dedicated API for dumping data.
27 - Dedicated API for handling transient strings.
28 - Panic support - in panic mode logging switches to blocking, synchronous
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/Zephyr-latest/drivers/ieee802154/
Dieee802154_dw1000_regs.h4 * SPDX-License-Identifier: Apache-2.0
6 * This file is based on dw1000_regs.h and dw1000_mac.c from
7 * https://github.com/Decawave/mynewt-dw1000-core.git
14 * Copyright (C) 2017-2018, Decawave Limited, All Rights Reserved
24 * http://www.apache.org/licenses/LICENSE-2.0
27 * software distributed under the License is distributed on an
75 /* Frame Filtering Behave as a Co-ordinator */
99 /* Disable receiver abort on PHR error */
101 /* Disable Receiver Abort on RSD error */
117 * Receiver Auto-Re-enable.
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