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/Zephyr-latest/dts/bindings/led_strip/
Dworldsemi,ws2812-i2s.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "worldsemi,ws2812-i2s"
12 include: [i2s-device.yaml, ws2812.yaml]
16 out-active-low:
20 nibble-one:
23 description: 4-bit value to shift out for a 1 pulse.
25 nibble-zero:
28 description: 4-bit value to shift out for a 0 pulse.
30 lrck-period:
35 extra-wait-time:
/Zephyr-latest/dts/bindings/display/
Dnordic,nrf-led-matrix.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nordic,nrf-led-matrix"
8 include: display-controller.yaml
11 row-gpios:
12 type: phandle-array
17 col-gpios:
18 type: phandle-array
23 pixel-mapping:
24 type: uint8-array
29 array corresponds to one pixel of the matrix and specifies the row
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Dsolomon,ssd1322.yaml5 include: [mipi-dbi-spi-device.yaml, display-controller.yaml]
8 column-offset:
13 row-offset:
17 COM pin used as first row, mapped to the line set by start-line.
20 start-line:
24 Starting line address of display ram (0-127).
27 mux-ratio:
31 COM Pin Multiplex ratio from 16-128.
34 remap-row-first:
38 remap-columns:
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/Zephyr-latest/doc/services/debugging/
Dmipi_stp_decoder.rst7 be shared by multiple application-specific trace protocols. It serves as a wrapper protocol
14 One example where protocol is used is ARM Coresight STM (System Trace Macrocell) where data
17 This module can be used to perform on-chip decoding of the data stream. STP v2 is used.
25 If decoder is not synchronized to the stream then it decodes each nibble in search for ASYNC opcode.
36 Implementation supports optimized version with unaligned memory access and generic one.
37 Optimized version is used for ARM Cortex-M (expect for M0).
/Zephyr-latest/doc/services/binary_descriptors/
Dindex.rst14 .. code-block:: c
22 .. code-block:: c
28 .. code-block:: bash
45 Each tag is a 16 bit unsigned integer, where the most significant nibble (4 bits) is the type
57 always aligned to 32 bits. If the value of the previous descriptor had a non-aligned
63 .. code-block::
78 3. It allows upstream-ability of descriptor generation (see Standard Descriptors)
82 .. code-block:: c
96 .. code-block:: kconfig
109 the range between ``0x800-0xfff``. This leaves ``0x000-0x7ff`` to users.
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/Zephyr-latest/drivers/flash/
Dflash_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
19 #include <zephyr/linker/linker-defs.h>
36 * One page program instruction allows maximum 256 bytes (a page) of data
50 * ILM(ILM -> CPU)instead of flash(flash -> I-Cache -> CPU) if enabled.
98 /* I-Cache tag sram reset */ in ramcode_reset_i_cache()
99 gctrl_regs->GCTRL_MCCR |= IT8XXX2_GCTRL_ICACHE_RESET; in ramcode_reset_i_cache()
100 /* Make sure the I-Cache is reset */ in ramcode_reset_i_cache()
103 gctrl_regs->GCTRL_MCCR &= ~IT8XXX2_GCTRL_ICACHE_RESET; in ramcode_reset_i_cache()
111 * ECINDAR3-0 are EC-indirect memory address registers. in ramcode_flash_follow_mode()
113 * Enter follow mode by writing 0xf to low nibble of ECINDAR3 register, in ramcode_flash_follow_mode()
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/Zephyr-latest/soc/microchip/mec/mec15xx/
Dsoc_espi_saf_v1.h4 * SPDX-License-Identifier: Apache-2.0
60 /* QMSPI descriptors 12-15 for all SPI flash devices */
64 * QMSPI descriptors 12-13 are exit continuous mode
84 * QMSPI descriptors 14-15 are poll 16-bit flash status
85 * Transmit one byte opcode at 1X (no DMA).
106 /* SAF Pre-fetch optimization mode */
112 * SAF Opcode 32-bit register value.
113 * Each byte contain a SPI flash 8-bit opcode.
117 * op0 = SPI flash write-enable opcode
127 * op0 = SPI flash read 1-4-4 continuous mode opcode
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/Zephyr-latest/tests/net/npf/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
40 "The Zephyr Project is a scalable real-time operating system (RTOS) supporting\n"
44 "The Zephyr OS is based on a small-footprint kernel designed for use on\n"
45 "resource-constrained systems: from simple embedded environmental sensors and\n"
48 "The Zephyr kernel supports multiple architectures, including ARM Cortex-M,\n"
49 "Intel x86, ARC, Nios II, Tensilica Xtensa, and RISC-V, and a large number of\n"
70 zassert_true((size - sizeof(eth_hdr)) <= sizeof(dummy_data), ""); in build_test_pkt()
71 ret = net_pkt_write(pkt, dummy_data, size - sizeof(eth_hdr)); in build_test_pkt()
82 int ret = -1; in build_test_ip_pkt()
195 /* test "small" non-IP packet */ in test_npf_example_common()
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/Zephyr-latest/soc/microchip/mec/mec172x/
Dsoc_espi_saf_v2.h4 * SPDX-License-Identifier: Apache-2.0
41 * Boot-ROM OTP configuration.
70 /* QMSPI descriptors 12-15 for all SPI flash devices */
72 /* QMSPI descriptors 12-13 are exit continuous mode */
108 * QMSPI descriptors 14-15 are poll 16-bit flash status
109 * Transmit one byte opcode at 1X (no DMA).
130 /* SAF Pre-fetch optimization mode */
136 * SAF Opcode 32-bit register value.
137 * Each byte contain a SPI flash 8-bit opcode.
141 * op0 = SPI flash write-enable opcode
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/Zephyr-latest/include/zephyr/sys/
Dutil.h2 * Copyright (c) 2011-2014, Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
40 * @defgroup sys-util Utility Functions
63 /** Number of bits in a nibble. */
80 (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
83 * @brief Create a contiguous 64-bit bitmask starting at bit position @p l
87 (((~0ULL) - (1ULL << (l)) + 1) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
89 /** @brief 0 if @p cond is true-ish; causes a compile error otherwise. */
90 #define ZERO_OR_COMPILE_ERROR(cond) ((int) sizeof(char[1 - 2 * !(cond)]) - 1)
94 /* The built-in function used below for type checking in C is not
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/Zephyr-latest/arch/xtensa/core/startup/
Dreset_vector.S3 * SPDX-License-Identifier: Apache-2.0
10 #include <xtensa/xtensa-xer.h>
11 #include <xtensa/xdm-regs.h>
14 #include <xtensa/xtruntime-core-state.h>
42 .size __start, . - __start
57 #warning "Xtensa TX reset vector not at start of iram0, irom0, or uram0 -- ROMing LSPs may not work"
76 * Even if the processor supports the non-PC-relative L32R option,
77 * it will always start up in PC-relative mode. We take advantage of
78 * this, and use PC-relative mode at least until we're sure the .lit4
81 .begin no-absolute-literals
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