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/Zephyr-latest/tests/drivers/spi/spi_controller_peripheral/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
5 int "SPI mode"
8 SPI mode value (clock polarity and phase) used in the test.
9 0: CPOL 0 (Active high), CPHA 0 (leading)
10 1: CPOL 0 (Active high), CPHA 1 (trailing)
11 2: CPOL 1 (Active low), CPHA 0 (leading)
12 3: CPOL 1 (Active low), CPHA 1 (trailing)
/Zephyr-latest/dts/bindings/wifi/
Dnordic,nrf70-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: This is a representation of the nRF70 Wi-Fi chip.
8 on-bus: qspi
11 qspi-frequency:
20 qspi-quad-mode:
23 If specified, Use QSPI in quad mode (4 IO lines) otherwise in
24 SPI mode (2 IO lines - MOSI & MISO).
26 qspi-rx-delay:
33 qspi-cpha:
36 Set to indicate phase starts with asserted half-phase (CPHA=1).
[all …]
/Zephyr-latest/dts/bindings/sdhc/
Dzephyr,sdhc-spi-slot.yaml3 compatible: "zephyr,sdhc-spi-slot"
5 include: [spi-device.yaml]
8 power-delay-ms:
16 spi-clock-mode-cpol:
22 spi-clock-mode-cpha:
26 on the clock's polarity. When mode-cpol is set and this option as well,
30 pwr-gpios:
31 type: phandle-array
/Zephyr-latest/dts/bindings/mspi/
Dmspi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
8 on-bus: mspi
14 mspi-max-frequency:
22 mspi-io-mode:
25 - "MSPI_IO_MODE_SINGLE"
26 - "MSPI_IO_MODE_DUAL"
27 - "MSPI_IO_MODE_DUAL_1_1_2"
28 - "MSPI_IO_MODE_DUAL_1_2_2"
29 - "MSPI_IO_MODE_QUAD"
30 - "MSPI_IO_MODE_QUAD_1_1_4"
[all …]
/Zephyr-latest/soc/microchip/mec/
DKconfig5 # SPDX-License-Identifier: Apache-2.0
18 Boot-ROM. Use the full Microchip SPI image generator program for
19 authentication and all other Boot-ROM loader features. Refer to the MCHP
58 prompt "Reading mode used by the SPI flash"
61 This sets the reading mode that can be used by the SPI flash.
65 bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
68 bool "SPI flash operates full-duplex with fast reading mode"
71 bool "SPI flash operates with dual data reading mode"
74 bool "SPI flash operates with quad data reading mode"
195 int "Flash SPI Mode"
[all …]
/Zephyr-latest/samples/subsys/fs/fs_sample/boards/
Dnucleo_f429zi.overlay2 * Copyright (c) 2023 Łukasz Hejnak (LeHack) <lehack-ghub@lehack.pl>
4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "zephyr,sdhc-spi-slot";
13 compatible = "zephyr,sdmmc-disk";
14 disk-name = "SD";
17 spi-max-frequency = <25000000>;
18 spi-clock-mode-cpol;
19 spi-clock-mode-cpha;
/Zephyr-latest/drivers/spi/
Dspi_xec_qmspi.c4 * SPDX-License-Identifier: Apache-2.0
58 REG8(&regs->TX_FIFO) = data8; in txb_wr8()
63 return REG8(&regs->RX_FIFO); in rxb_rd8()
69 * mode register is defined as: 0=maximum divider of 256. Values 1 through
87 qmode = regs->MODE & ~(MCHP_QMSPI_M_FDIV_MASK); in qmspi_set_frequency()
89 regs->MODE = qmode; in qmspi_set_frequency()
93 * SPI signalling mode: CPOL and CPHA
94 * CPOL = 0 is clock idles low, 1 is clock idle high
99 * SPI Mode nomenclature:
100 * Mode CPOL CPHA
[all …]
Dspi_xec_qmspi_ldma.c4 * SPDX-License-Identifier: Apache-2.0
20 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
21 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
33 /* MEC172x QMSPI controller SPI Mode 3 signalling has an anomaly where
35 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
123 return -ETIMEDOUT; in xec_qmspi_spin_yield()
133 * Some QMSPI timing register may be modified by the Boot-ROM OTP
141 uint32_t mode; in qmspi_reset() local
144 taps[0] = regs->TM_TAPS; in qmspi_reset()
145 taps[1] = regs->TM_TAPS_ADJ; in qmspi_reset()
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Dspi_numaker.c2 * SPDX-License-Identifier: Apache-2.0
42 * CPOL/CPHA = 0/0 --> SPI_MODE_0
43 * CPOL/CPHA = 0/1 --> SPI_MODE_1
44 * CPOL/CPHA = 1/0 --> SPI_MODE_2
45 * CPOL/CPHA = 1/1 --> SPI_MODE_3
57 int mode; in spi_numaker_configure() local
58 struct spi_numaker_data *data = dev->data; in spi_numaker_configure()
59 const struct spi_numaker_config *dev_cfg = dev->config; in spi_numaker_configure()
62 if (spi_context_configured(&data->ctx, config)) { in spi_numaker_configure()
66 if (SPI_MODE_GET(config->operation) & SPI_MODE_LOOP) { in spi_numaker_configure()
[all …]
Dspi_rpi_pico_pio.c4 * SPDX-License-Identifier: Apache-2.0
56 /* ------------ */
58 /* ------------ */
71 /* ------------ */
73 /* ------------ */
88 /* ------------------- */
90 /* ------------------- */
105 /* ------------------------- */
107 /* ------------------------- */
119 0x0042, /* 3: jmp x--, 2 side 0 */
[all …]
Dspi_sedi.c4 * SPDX-License-Identifier: Apache-2.0
40 struct spi_sedi_data *data = dev->data; in spi_sedi_configure()
41 const struct spi_sedi_config *info = dev->config; in spi_sedi_configure()
42 uint32_t word_size, cpol, cpha, loopback; in spi_sedi_configure() local
44 if (spi_context_configured(&data->ctx, config) == true) { in spi_sedi_configure()
48 word_size = SPI_WORD_SIZE_GET(config->operation); in spi_sedi_configure()
49 sedi_spi_control(info->spi_device, SEDI_SPI_IOCTL_DATA_WIDTH, in spi_sedi_configure()
52 /* CPOL and CPHA */ in spi_sedi_configure()
53 cpol = SPI_MODE_GET(config->operation) & SPI_MODE_CPOL; in spi_sedi_configure()
54 cpha = SPI_MODE_GET(config->operation) & SPI_MODE_CPHA; in spi_sedi_configure()
[all …]
Dspi_npcx_spip.c4 * SPDX-License-Identifier: Apache-2.0
46 const struct spi_npcx_spip_cfg *const config = dev->config; in spi_npcx_spip_configure()
47 struct spi_npcx_spip_data *const data = dev->data; in spi_npcx_spip_configure()
48 struct spip_reg *const reg_base = config->reg_base; in spi_npcx_spip_configure()
49 spi_operation_t operation = spi_cfg->operation; in spi_npcx_spip_configure()
52 if (spi_context_configured(&data->ctx, spi_cfg)) { in spi_npcx_spip_configure()
58 LOG_ERR("Half duplex mode is not supported"); in spi_npcx_spip_configure()
59 return -ENOTSUP; in spi_npcx_spip_configure()
63 LOG_ERR("Only SPI controller mode is supported"); in spi_npcx_spip_configure()
64 return -ENOTSUP; in spi_npcx_spip_configure()
[all …]
Dspi_xmc4xxx.c4 * SPDX-License-Identifier: Apache-2.0
79 data->dma_status_flags |= SPI_XMC4XXX_DMA_ERROR_FLAG; in spi_xmc4xxx_dma_callback()
81 if (dev_dma == data->dma_tx.dev_dma && dma_channel == data->dma_tx.dma_channel) { in spi_xmc4xxx_dma_callback()
82 data->dma_status_flags |= SPI_XMC4XXX_DMA_TX_DONE_FLAG; in spi_xmc4xxx_dma_callback()
83 } else if (dev_dma == data->dma_rx.dev_dma && in spi_xmc4xxx_dma_callback()
84 dma_channel == data->dma_rx.dma_channel) { in spi_xmc4xxx_dma_callback()
85 data->dma_status_flags |= SPI_XMC4XXX_DMA_RX_DONE_FLAG; in spi_xmc4xxx_dma_callback()
88 data->dma_status_flags |= SPI_XMC4XXX_DMA_ERROR_FLAG; in spi_xmc4xxx_dma_callback()
91 k_sem_give(&data->status_sem); in spi_xmc4xxx_dma_callback()
111 struct spi_xmc4xxx_data *data = dev->data; in spi_xmc4xxx_shift_frames()
[all …]
Dspi_grlib_spimctrl.c4 * SPDX-License-Identifier: Apache-2.0
35 #define SPI_DATA(dev) ((struct data *) ((dev)->data))
48 if (config->slave != 0) { in spi_config()
50 return -ENOTSUP; in spi_config()
53 if (SPI_WORD_SIZE_GET(config->operation) != 8) { in spi_config()
55 return -ENOTSUP; in spi_config()
58 if (config->operation & SPI_CS_ACTIVE_HIGH) { in spi_config()
60 return -ENOTSUP; in spi_config()
63 if (config->operation & SPI_LOCK_ON) { in spi_config()
65 return -ENOTSUP; in spi_config()
[all …]
Dspi_litex_litespi.c4 * SPDX-License-Identifier: Apache-2.0
44 const struct spi_litex_dev_config *dev_config = dev->config; in spi_litex_set_frequency()
46 if (!dev_config->phy_clk_divisor_exists) { in spi_litex_set_frequency()
52 uint32_t divisor = DIV_ROUND_UP(sys_clock_hw_cycles_per_sec(), (2 * config->frequency)) - 1; in spi_litex_set_frequency()
54 litex_write32(divisor, dev_config->phy_clk_divisor_addr); in spi_litex_set_frequency()
61 struct spi_litex_data *dev_data = dev->data; in spi_config()
63 if (config->slave != 0) { in spi_config()
64 if (config->slave >= SPI_MAX_CS_SIZE) { in spi_config()
66 return -ENOTSUP; in spi_config()
70 if (config->operation & SPI_HALF_DUPLEX) { in spi_config()
[all …]
Dspi_litex.c5 * SPDX-License-Identifier: Apache-2.0
38 const struct spi_litex_cfg *dev_config = dev->config; in spi_set_frequency()
40 if (!dev_config->clk_divider_exists) { in spi_set_frequency()
46 uint16_t divisor = DIV_ROUND_UP(sys_clock_hw_cycles_per_sec(), config->frequency); in spi_set_frequency()
48 litex_write16(divisor, dev_config->clk_divider_addr); in spi_set_frequency()
54 const struct spi_litex_cfg *dev_config = dev->config; in spi_config()
55 struct spi_litex_data *dev_data = dev->data; in spi_config()
57 if (config->slave >= dev_config->max_cs) { in spi_config()
59 return -ENOTSUP; in spi_config()
62 if (config->operation & SPI_HALF_DUPLEX) { in spi_config()
[all …]
Dspi_nxp_s32.c2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
15 struct spi_context *ctx = &data->ctx; in spi_nxp_s32_last_packet()
17 if (ctx->tx_count <= 1U && ctx->rx_count <= 1U) { in spi_nxp_s32_last_packet()
18 if (!spi_context_tx_on(ctx) && (data->transfer_len == ctx->rx_len)) { in spi_nxp_s32_last_packet()
22 if (!spi_context_rx_on(ctx) && (data->transfer_len == ctx->tx_len)) { in spi_nxp_s32_last_packet()
26 if ((ctx->rx_len == ctx->tx_len) && (data->transfer_len == ctx->tx_len)) { in spi_nxp_s32_last_packet()
41 const struct spi_nxp_s32_config *config = dev->config; in spi_nxp_s32_transfer_next_packet()
42 struct spi_nxp_s32_data *data = dev->data; in spi_nxp_s32_transfer_next_packet()
49 data_cb = config->cb; in spi_nxp_s32_transfer_next_packet()
[all …]
Dspi_sifive.c4 * SPDX-License-Identifier: Apache-2.0
38 return -ENOTSUP; in spi_config()
42 return -ENOTSUP; in spi_config()
46 return -ENOTSUP; in spi_config()
50 div = (SPI_CFG(dev)->f_sys / (frequency * 2U)) - 1; in spi_config()
55 /* If CPOL is set, then SCK idles at logical 1 */ in spi_config()
77 return -ENOTSUP; in spi_config()
87 return -ENOTSUP; in spi_config()
129 struct spi_context *ctx = &SPI_DATA(dev)->ctx; in spi_sifive_xfer()
142 txd = *ctx->tx_buf; in spi_sifive_xfer()
[all …]
Dspi_gecko_usart.c4 * SPDX-License-Identifier: Apache-2.0
46 : -1)
50 : -1)
55 : -1)
61 : -1)
68 : -1)
76 : -1)
120 const struct spi_gecko_config *gecko_config = dev->config; in spi_config()
121 struct spi_gecko_data *data = dev->data; in spi_config()
122 mem_addr_t ctrl_reg = (mem_addr_t)&gecko_config->base->CTRL; in spi_config()
[all …]
/Zephyr-latest/dts/bindings/mipi-dbi/
Dmipi-dbi-spi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for MIPI DBI devices using Mode C (SPI)
6 include: [mipi-dbi-device.yaml]
13 SPI Duplex mode, full or half. By default it's always full duplex thus 0
14 as this is, by far, the most common mode.
18 list (see dt-bindings/spi/spi.h)
21 mipi-cpol:
26 mipi-cpha:
31 mipi-hold-cs:
/Zephyr-latest/dts/bindings/spi/
Dspi-device.yaml1 # Copyright (c) 2018, I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
8 on-bus: spi
13 spi-max-frequency:
21 Duplex mode, full or half. By default it's always full duplex thus 0
22 as this is, by far, the most common mode.
24 list (see dt-bindings/spi/spi.h)
28 - 0
29 - 2048
30 frame-format:
[all …]
/Zephyr-latest/drivers/flash/
Dnrf_qspi_nor.c2 * Copyright (c) 2019-2024, Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
69 #error "No size specified. 'size' or 'size-in-bytes' must be set"
73 "Node " DT_NODE_PATH(DT_DRV_INST(0)) " has both size and size-in-bytes "
80 * frequencies 2 - 32 MHz and the nRF53 one supports 6 - 96 MHz.
108 INST_0_SCK_FREQUENCY) - 1)
121 INST_0_SCK_FREQUENCY) - 1)
140 INST_0_SCK_FREQUENCY) - 1)
146 /* 0 for MODE0 (CPOL=0, CPHA=0), 1 for MODE3 (CPOL=1, CPHA=1). */
147 #define INST_0_SPI_MODE DT_INST_PROP(0, cpol)
[all …]
/Zephyr-latest/boards/st/sensortile_box_pro/
Dsensortile_box_pro.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/u5/stm32u585aiixq-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "STMicroelectronics SENSORTILE-BOX-PRO board";
14 compatible = "st,sensortile-box-pro";
19 zephyr,code-partition = &slot0_partition;
20 zephyr,bt-hci = &hci_spi;
24 compatible = "gpio-leds";
44 compatible = "gpio-keys";
[all …]
/Zephyr-latest/drivers/fpga/
Dfpga_ice40_bitbang.c5 * SPDX-License-Identifier: Apache-2.0
28 * The logical alternative would be to put the CS into GPIO mode, perform 3
30 * restore the default pinctrl settings. On some higher-end microcontrollers
34 * However, on lower-end microcontrollers, the amount of time that elapses
36 * leaves us with the bitbanging option. Of course, on lower-end
40 * in order to bitbang on lower-end microcontrollers, we actually require
57 * with the GPIO bitbang mode. It is used both in fpga_ice40_send_clocks()
61 * lattice,ice40-fpga.yaml for details.
65 for (; n > 0; --n) { in fpga_ice40_delay()
73 for (; n > 0; --n) { in fpga_ice40_send_clocks()
[all …]
/Zephyr-latest/drivers/led_strip/
Dtlc5971.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/led/led.h>
34 /** SPI operation word constant, SPI mode 0, CPOL = 0, CPHA = 0 */
57 /** GS reference clock edge select bit for OUTXn on-off timing control in FC data */
60 /** Constant-current output enable bit in FC data (0 = output control enabled, 1 = blank). */
63 /** Auto display repeat mode enable bit in FC data (0 = disabled, 1 = enabled). */
66 /** Display timing reset mode enable bit in FC data (0 = disabled, 1 = enabled). */
157 temp = pixel_data->r; in tlc5971_map_color()
160 temp = pixel_data->g; in tlc5971_map_color()
163 temp = pixel_data->b; in tlc5971_map_color()
[all …]

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