Home
last modified time | relevance | path

Searched +full:mmu +full:- +full:type (Results 1 – 25 of 58) sorted by relevance

123

/Zephyr-latest/dts/bindings/cpu/
Driscv,cpus.yaml2 # SPDX-License-Identifier: Apache-2.0
7 mmu-type:
8 description: Memory Management Unit (MMU)
9 type: string
11 - riscv,sv32
12 - riscv,sv39
13 - riscv,sv48
14 - riscv,none
17 description: RISC-V instruction set architecture
19 type: string
/Zephyr-latest/boards/qemu/xtensa/
Dqemu_xtensa_dc233c_mmu.yaml1 identifier: qemu_xtensa/dc233c/mmu
2 name: QEMU Emulation for Xtensa with MMU
3 type: qemu
5 - name: qemu
8 - zephyr
9 - xtools
13 - net
14 - bluetooth
/Zephyr-latest/include/zephyr/arch/arm/mmu/
Darm_mmu.h2 * ARMv7 MMU support
5 * SPDX-License-Identifier: Apache-2.0
15 * ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition,
17 * Memory type definitions:
18 * Table B3-10, chap. B3.8.2, p. B3-1363f.
20 * Table B3-11, chap. B3.8.2, p. B3-1364
71 * @brief Auto generate mmu region entry for node_id
93 * @brief Auto generate mmu region entry for status = "okay"
123 /* MMU configuration data structure */
132 * Reference to the MMU configuration.
[all …]
/Zephyr-latest/dts/riscv/andes/
Dandes_v5_ae350.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
19 compatible = "andestech,andescore-v5", "riscv";
24 mmu-type = "riscv,sv32";
25 clock-frequency = <60000000>;
[all …]
/Zephyr-latest/boards/qemu/x86/
Dqemu_x86_atom_nommu.yaml2 name: QEMU Emulation for X86 (MMU disabled)
3 type: qemu
6 - name: qemu
8 - zephyr
9 - xtools
13 - kernel
14 - userspace
/Zephyr-latest/samples/userspace/hello_world_user/
Dsample.yaml7 - mps2/an385
11 type: one_line
13 - "Hello World from UserSpace! (.*)"
18 - posix
20 - qemu_xtensa/dc233c/mmu
/Zephyr-latest/dts/riscv/sifive/
Driscv64-fu740.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
13 compatible = "sifive,FU740-C000", "fu740-dev", "sifive-dev";
17 coreclk: core-clk {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <DT_FREQ_M(1000)>;
23 pclk: p-clk {
[all …]
Driscv64-fu540.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "sifive,FU540-C000", "fu540-dev", "sifive-dev";
17 coreclk: core-clk {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <DT_FREQ_M(1000)>;
23 tlclk: tl-clk {
[all …]
/Zephyr-latest/samples/subsys/demand_paging/
Dsample.yaml2 description: On-Demand paging of firmware larger than available memory
3 name: demand-paging
6 - kernel
7 - mmu
8 - demand_paging
10 - qemu_cortex_a53
13 type: multi_line
16 - "Calling huge body of code that doesn't fit in memory"
17 - "free memory pages: from (.*) to 0, (.*) page faults"
18 - "Calling it a second time"
[all …]
/Zephyr-latest/dts/riscv/starfive/
Djh7110-visionfive-v2.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include "jh7110-clk.dtsi"
9 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
28 cpu0_intc: interrupt-controller {
29 compatible = "riscv,cpu-intc";
30 interrupt-controller;
[all …]
Dstarfive_jh7100_beagle_v.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
13 compatible = "sifive,freedom-u74-arty";
14 model = "sifive,freedom-u74-arty";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 compatible = "starfive,fu74-g000";
21 clock-frequency = <0>;
[all …]
/Zephyr-latest/tests/subsys/llext/
Dtestcase.yaml5 - numaker_pfm_m487 # See #63167
6 - s32z2xxdc2/s32z270/rtu0 # See commit 18a0660
7 - s32z2xxdc2/s32z270/rtu1 # See commit 18a0660
9 - qemu_cortex_m0
10 - qemu_xtensa/dc233c/mmu
12 - qemu_cortex_a9 # ARM Cortex-A9 (ARMv7-A ISA)
13 - qemu_cortex_r5 # ARM Cortex-R5 (ARMv7-R ISA)
14 - mps2/an385 # ARM Cortex-M3 (ARMv7-M ISA)
15 - mps2/an521/cpu0 # ARM Cortex-M33 (ARMv8-M ISA)
18 - arch:arm64:CONFIG_LLEXT_HEAP_SIZE=128
[all …]
/Zephyr-latest/tests/subsys/debug/coredump/
Dtestcase.yaml9 - posix
11 - qemu_x86
14 type: multi_line
16 - "Coredump: (.*)"
17 - ">>> ZEPHYR FATAL ERROR "
18 - "E: #CD:BEGIN#"
19 - "E: #CD:5([aA])45([0-9a-fA-F]+)"
20 - "E: #CD:41([0-9a-fA-F]+)"
21 - "E: #CD:4([dD])([0-9a-fA-F]+)"
22 - "E: #CD:4([dD])([0-9a-fA-F]+)"
[all …]
/Zephyr-latest/arch/arm/core/mmu/
Darm_mmu.c2 * ARMv7 MMU support
4 * This implementation supports the Short-descriptor translation
14 * ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition,
18 * SPDX-License-Identifier: Apache-2.0
25 #include <zephyr/linker/linker-defs.h>
34 #include <zephyr/arch/arm/mmu/arm_mmu.h>
39 /* Level 1 page table: always required, must be 16k-aligned */
65 * processed upon MMU initialization.
70 * cacheable, read / write and non-executable
95 /* Mark rodata segment cacheable, read only and non-executable */
[all …]
Darm_mmu_priv.h2 * ARMv7 MMU support
7 * SPDX-License-Identifier: Apache-2.0
15 * ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition
17 * L1 / L2 page table entry formats and entry type IDs:
18 * Chapter B3.5.1, fig. B3-4 and B3-5, p. B3-1323 f.
70 /* <-- end MP-/non-MP-specific */
84 #define ARM_MMU_L2_PT_INDEX(pt) ((uint32_t)pt - (uint32_t)l2_page_tables) /\
175 * MMU initialization.
/Zephyr-latest/arch/xtensa/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
32 the core-isa.h file. This replaces the previous scheme
62 A design trick on multi-core hardware is to map memory twice
71 This specifies which 512M region (0-7, as defined by the Xtensa
79 region (0-7) contains the "uncached" mapping.
161 bool "Xtensa exceptions and interrupts cannot be pre-empted"
164 pre-empting low priority interrupts and exceptions.
169 bool "Xtensa MMU Support"
170 select MMU
260 hex "Default Memory Type"
[all …]
/Zephyr-latest/arch/x86/core/
Dmultiboot.c4 * SPDX-License-Identifier: Apache-2.0
33 x86_memmap[index].type = X86_MEMMAP_ENTRY_UNUSED; in clear_memmap()
48 * Without MMU, all memory are identity-mapped already in z_multiboot_init()
69 if ((info->flags & MULTIBOOT_INFO_FLAGS_MMAP) && in z_multiboot_init()
75 uint32_t type; in z_multiboot_init() local
78 address = info->mmap_addr; in z_multiboot_init()
82 k_mem_map_phys_bare(&address_va, info->mmap_addr, info->mmap_length, in z_multiboot_init()
88 address_end = address + info->mmap_length; in z_multiboot_init()
94 x86_memmap[index].base = mmap->base; in z_multiboot_init()
95 x86_memmap[index].length = mmap->length; in z_multiboot_init()
[all …]
/Zephyr-latest/tests/subsys/debug/thread_analyzer/
Dtestcase.yaml3 - qemu_x86
4 - qemu_x86_64
8 - mps2/an385
9 - qemu_cortex_a53
10 - qemu_x86
11 - qemu_x86_64
12 - qemu_riscv32
13 - qemu_riscv64
14 - qemu_xtensa/dc233c/mmu
16 - CONFIG_QEMU_ICOUNT=n
[all …]
/Zephyr-latest/doc/kernel/usermode/
Dmemory_domain.rst8 which have a paged MMU (Memory Management Unit), but in that case the MMU is
24 - Any configuration of memory regions which need to have special caching or
25 write-back policies for basic hardware and driver function. Note that most
30 ARMv7-M/ARMv8-M this is called the System Address Map, other CPUs may
34 - A read-only, executable region or regions for program text and ro-data, that
35 is accessible to user mode. This could be further sub-divided into a
36 read-only region for ro-data, and a read-only, executable region for text, but
38 threads running in user mode can read ro-data and fetch instructions.
40 - Depending on configuration, user-accessible read-write regions to support
45 text/ro-data, this is sufficient for the boot time configuration.
[all …]
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dpower_down.S2 * SPDX-License-Identifier: Apache-2.0
17 .type power_down, @function
24 * @param A2 - argument for LPSRAM
25 * @param A3 - argument for HPSRAM
26 * @param A4 - send response to ipc
68 * This addresses an issue on platforms with an MMU where a
70 * registers during the power-down process. By preloading the IPC
110 * Send IPC to host informing of PD completion - Clear BUSY
148 addi temp_reg0, temp_reg0, -1
157 .size power_down , . - power_down
/Zephyr-latest/arch/arm64/core/
Dmmu.c7 * SPDX-License-Identifier: Apache-2.0
22 #include <zephyr/linker/linker-defs.h>
25 #include <mmu.h>
27 #include "mmu.h"
63 unsigned int i = (pte - xlat_tables) / Ln_XLAT_NUM_ENTRIES; in table_index()
78 MMU_DEBUG("table [%d]%p: usage %#x -> %#x\n", i, table, prev_count, new_count); in table_usage()
101 table_usage(table, -ref_unit); in dec_table_ref()
175 bool aligned = (desc & PTE_PHYSADDR_MASK & (level_size - 1)) == 0; in is_desc_block_aligned()
200 MMU_DEBUG("---\n"); in debug_show_pte()
218 MMU_DEBUG("[paged-out] "); in debug_show_pte()
[all …]
/Zephyr-latest/doc/releases/
Drelease-notes-1.9.rst49 * Bluetooth Qualification-ready BLE Controller
54 * MMU/MPU (Cont.): Thread Isolation, Paging
65 * kernel: introduce opaque data type for stacks
79 * x86: Enable MMU for application memory
82 * ARC: Nested interrupt support for normal, non-FIRQ interrupts
90 * arm: Added Olimex STM32-E407 and STM32-P405 boards
91 * arm: Added STM32F412 Nucleo and STM32F429I-DISC1 boards
116 * net-app API support added. This is higher level API that can be used
126 networking applications using a well-known, cross-platform API
140 * IPSP net-app support: a simplified networking API reducing duplication
[all …]
/Zephyr-latest/doc/kernel/
Dcode-relocation.rst13 This script provides a robust way to re-order the memory contents without
25 ``python3 gen_relocate_app.py -i input_string -o generated_linker -c generated_code``
48 for data copy operations from ROM to required memory type.
74 .. code-block:: none
79 * if the memory type is appended with _DATA, _TEXT, _RODATA or _BSS, only the
83 .. code-block:: none
92 expressions can be used to relocate a comma-separated list of files
94 .. code-block:: none
106 it is invoked with ``--gc-sections``. If you'd like to override this behavior,
109 .. code-block:: none
[all …]
/Zephyr-latest/doc/services/llext/
Dload.rst50 call :c:func:`llext_bringup`, then a user-specified function in the same
58 The returned ``void *`` can then be cast to the appropriate type and used.
90 * If possible, disable memory protection (MMU/MPU) and see if this results in
/Zephyr-latest/doc/develop/languages/c/
Dnewlib.rst13 Other 3rd-party toolchains, such as :ref:`toolchain_gnuarmemb`, also bundle
18 :file:`lib/libc/newlib/libc-hooks.c` and translate the library internal system
37 :kconfig:option:`CONFIG_NEWLIB_LIBC` and de-selecting the
45 size-optimized version of the Newlib, and supports all features that the full
47 the ``char``, ``long long`` type format specifiers (i.e. ``%hhX`` and
92 the Zephyr-side libc hooks is the :c:func:`sbrk` function, which is used by the
96 The :c:func:`_sbrk` hook function, implemented in :file:`libc-hooks.c`, handles
108 * When MMU is enabled (:kconfig:option:`CONFIG_MMU` is selected), the amount of
114 * When MPU is enabled and the MPU requires power-of-two partition size and
116 set to a non-zero value), the amount of memory space reserved for the Newlib

123