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/hal_espressif-latest/components/driver/spi/include/driver/
Dspi_common.h59 …COMMON_BUSFLAG_MISO (1<<4) ///< Check existing of MISO pin. Or indicates MISO line in…
61 #define SPICOMMON_BUSFLAG_DUAL (1<<6) ///< Check MOSI and MISO pins can output. Or ind…
63 …MMON_BUSFLAG_DUAL|SPICOMMON_BUSFLAG_WPHD) ///< Check existing of MOSI/MISO/WP/HD pins as outpu…
65 …MMON_BUSFLAG_QUAD|SPICOMMON_BUSFLAG_IO4_IO7) ///< Check existing of MOSI/MISO/WP/HD/SPIIO4/SPIIO5…
Dspi_master.h75 …elay_ns; /**< Maximum data valid time of slave. The time required between SCLK and MISO
77 …delay before the MISO is ready on the line. Leave at 0 unless you know you need a delay. For bette…
144 …void *rx_buffer; ///< Pointer to receive buffer, or NULL for no MISO phase. Written by …
371 * @param input_delay_ns Input delay from SCLK launch edge to MISO data valid.
389 * @param input_delay_ns Input delay from SCLK launch edge to MISO data valid.
Dspi_slave.h75 void *rx_buffer; /**< Pointer to receive buffer, or NULL for no MISO phase.
/hal_espressif-latest/tools/esptool_py/docs/en/advanced-topics/
Dspi-flash-modes.rst41 * Master In Slave Out (MISO)
46 …l. In single SPI mode, data is sent from the device to the host using the MISO pin and from the ho…
53 … flash manufacturers introduced "Dual SPI". In Dual SPI modes, the MOSI & MISO pins are both used …
55 …chip via normal SPI, but then the host reads the data via both the MOSI & MISO pins simultaneously…
56 This doubles the data transfer rate compared to single SPI which only uses MISO to read data.
58 …l SPI, but then the address is sent to the flash chip via both the MOSI & MISO pins with two bits …
/hal_espressif-latest/components/esp_rom/include/esp32s2/rom/
Dopi_flash.h174 * @param miso_data data buffer to accept data in miso field
175 * @param miso_bit_len bit length of data buffer to accept data in miso field
/hal_espressif-latest/zephyr/port/pincfgs/
Desp32s2.yml49 miso:
78 miso:
Desp32c2.yml45 miso:
Desp32c3.yml45 miso:
Desp32c6.yml50 miso:
Desp32.yml64 miso:
84 miso:
Desp32s3.yml136 miso:
165 miso:
/hal_espressif-latest/components/bootloader_support/bootloader_flash/include/
Dbootloader_flash_priv.h176 * @param miso_len Length of MISO data to receive, in bits
177 * @return Received MISO data
/hal_espressif-latest/components/hal/
Dspi_hal.c141 //give MISO a delay if needed to make sure we sample at the time MISO is stable in spi_hal_cal_timing()
Dspi_slave_hal_iram.c75 //SPI Slave mode on ESP32 requires MOSI/MISO enable in spi_slave_hal_prepare_data()
/hal_espressif-latest/components/esp_rom/include/esp32s3/rom/
Dopi_flash.h212 * @param miso_data data buffer to accept data in miso field
213 * @param miso_bit_len bit length of data buffer to accept data in miso field
/hal_espressif-latest/components/hal/include/hal/
Dspi_hal.h60 int timing_miso_delay; ///< Extra miso delay clocks to compensate the timing
254 * @param miso_delay_n suggested delay on the MISO line, in APB clocks.
Dspi_flash_hal.h73 …int input_delay_ns; ///< Input delay on the MISO pin after the launch clock, used for timing c…
/hal_espressif-latest/components/soc/esp32/include/soc/
Dspi_struct.h62 …uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB fi…
90 …uint32_t miso_delay_mode: 2; /*MISO signals are delayed by spi_clk. 0: zero 1:…
91 …uint32_t miso_delay_num: 3; /*MISO signals are delayed by system clock cycles*/
118 …uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: littl…
124 … /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the s…
/hal_espressif-latest/components/driver/spi/gpspi/
Dspi_common.c554 SPI_CHECK_PIN(bus_config->miso_io_num, "miso", miso_need_output); in spicommon_bus_initialize_io()
556 //set flags for DUAL mode according to output-capability of MOSI and MISO pins. in spicommon_bus_initialize_io()
582 ESP_LOGE(SPI_TAG, "miso pin required."); in spicommon_bus_initialize_io()
585 ESP_LOGE(SPI_TAG, "not both mosi and miso output capable"); in spicommon_bus_initialize_io()
Dspi_master.c788 …bled, "SPI half duplex mode does not support using DMA with both MOSI and MISO phases.", ESP_ERR_I… in check_trans_valid()
792 …|| !rx_enabled, "SPI half duplex mode is not supported when both MOSI and MISO phases are enabled.… in check_trans_valid()
793 …desc->rxlength, "SPI half duplex mode is not supported when both MOSI and MISO phases are enabled.… in check_trans_valid()
797 //MISO phase is skipped only when both rx_buffer and SPI_TRANS_USE_RXDATA are not set. in check_trans_valid()
799 …_buffer should be NULL and SPI_TRANS_USE_RXDATA should be cleared to skip MISO phase.", ESP_ERR_IN… in check_trans_valid()
/hal_espressif-latest/components/driver/include/esp_private/
Dspi_common_internal.h167 …* Make sure SCLK/MISO/MOSI is/are set to a valid GPIO. Also check output capabili…
168 …* - ``SPICOMMON_BUSFLAG_DUAL``: Make sure both MISO and MOSI are output capable so th…
177 * CLK/MISO/MOSI connected.
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dspi_struct.h40 …uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: hi…
45 …uint32_t rd_bit_order : 1; /*In read-data (MISO) phase 1: LSB first 0: MSB fi…
79 … 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the s…
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dspi_struct.h42 …uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high…
47 …uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB firs…
96 …uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: little_…
102 … /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the s…
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dspi_struct.h43 …uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: hi…
48 …uint32_t rd_bit_order : 2; /*In read-data (MISO) phase 1: LSB first 0: MSB fi…
82 … 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the s…
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dspi_struct.h51 …uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: hi…
56 …uint32_t rd_bit_order : 2; /*In read-data (MISO) phase 1: LSB first 0: MSB fi…
90 … 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the s…

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