| /Zephyr-latest/dts/bindings/misc/ |
| D | nxp,s32-emios.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 as a reference timebase (master bus) for other channels.
10 compatible: "nxp,s32-emios"
21 interrupt-names:
27 clock-divider:
33 internal-cnt:
39 child-binding:
40 child-binding:
42 Node for eMIOS master bus. Each channel is capable to become a master bus has
44 the master bus, the devicetree node should be enabled and dts properties
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| D | nxp,rdc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 core, a bus master, or set of cores and bus masters.
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | nxp,s32-emios-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 require to use a reference timebase from a master bus.
11 - Channel 0 for mode OPWFMB
12 - Channel 1 for mode OPWMB
13 - Channel 2 for mode OPWMCB with deadtime inserted at leading edge
14 - Channel 3 for mode SAIC, use internal timebase with input filter = 2 eMIOS clock
19 pwm-mode = "OPWFMB";
22 duty-cycle = <32768>;
28 master-bus = <&emios1_bus_a>;
29 pwm-mode = "OPWMB";
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| /Zephyr-latest/doc/hardware/peripherals/ |
| D | w1.rst | 3 1-Wire Bus
9 1-Wire is a low speed half-duplex serial bus using only a single wire plus
11 Similarly to I2C, 1-Wire uses a bidirectional open-collector data line,
12 and is a single master multidrop bus. This means one master initiates all data
14 The 1-Wire bus supports longer bus lines than I2C, while it reaches speeds of up
17 over a bus length of 100 meters. Using overdrive speed, 3 nodes on a bus of
19 fewer nodes on the bus may allow to reach larger bus extents.
23 .. figure:: 1-Wire_bus_topology.drawio.svg
25 :alt: 1-Wire bus topology
27 A typical 1-Wire bus topology
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| /Zephyr-latest/samples/drivers/i2c/custom_target/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
11 static const struct device *bus = DEVICE_DT_GET(DT_NODELABEL(flexcomm4)); variable
15 * @brief Callback which is called when a write request is received from the master.
25 * @brief Callback which is called when a write is received from the master.
27 * @param val The byte received from the master.
37 * @brief Callback which is called when a read request is received from the master.
39 * @param val Pointer to the byte to be sent to the master.
49 * @brief Callback which is called when a read is processed from the master.
51 * @param val Pointer to the next byte to be sent to the master.
61 * @brief Callback which is called when the master sends a stop condition.
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| /Zephyr-latest/drivers/w1/ |
| D | Kconfig.zephyr_gpio | 1 # Configuration options for the Zephyr GPIO 1-Wire Master driver
4 # SPDX-License-Identifier: Apache-2.0
7 bool "1-wire GPIO"
11 This option enables the Zephyr GPIO 1-Wire master driver.
13 The bus reset, and bit read and write operations are executed
23 This option forces the 1-Wire GPIO driver to use time critical
24 operations for bus reset, and bit read and write operations.
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| D | Kconfig.zephyr_serial | 1 # Configuration options for the Zephyr serial 1-Wire Master driver
4 # SPDX-License-Identifier: Apache-2.0
7 bool "1-wire Serial"
13 This option enables the Zephyr serial 1-Wire master driver.
15 The bus reset, and bit read and write operations are executed
26 uart byte (1-wire standard speed data bit).
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| D | w1_zephyr_serial.c | 4 * SPDX-License-Identifier: Apache-2.0
10 * @brief 1-Wire Bus Master driver using Zephyr serial interface.
12 * This driver implements the 1-Wire interface using an uart.
16 …* https://www.analog.com/en/resources/technical-articles/using-a-uart-to-implement-a-1wire-bus-mas…
52 /** w1 master config, common to all drivers */
54 /** UART device used for 1-Wire communication */
59 /** w1 master data, common to all drivers */
66 * Concurrently transmits and receives one 1-Wire bit
72 const struct w1_serial_config *cfg = dev->config; in serial_tx_rx()
81 while (uart_poll_in(cfg->uart_dev, &dummy) == 0) { in serial_tx_rx()
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| /Zephyr-latest/include/zephyr/drivers/ |
| D | w1.h | 5 * SPDX-License-Identifier: Apache-2.0
10 * @brief Public 1-Wire Driver APIs
27 * @brief 1-Wire Interface
28 * @defgroup w1_interface 1-Wire Interface
38 * Count the number of slaves expected on the bus.
39 * This can be used to decide if the bus has a multidrop topology or
46 (FOR_EACH(F1, (+), DT_SUPPORTS_DEP_ORDS(node_id)) - 1)
53 * @brief Defines the 1-Wire master settings types, which are runtime configurable.
74 /** Configuration common to all 1-Wire master implementations. */
80 /** Data common to all 1-Wire master implementations. */
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| /Zephyr-latest/drivers/i2s/ |
| D | Kconfig.sam_ssc | 1 # Atmel SAM I2S bus driver configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 bool "Atmel SAM MCU family I2S (SSC) Bus Driver"
13 Enable Inter Sound (I2S) bus driver for Atmel SAM MCU family based on
32 in master or slave mode.
43 in master or slave mode.
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| /Zephyr-latest/dts/bindings/test/ |
| D | vnd,w1.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Test W1 bus master node
8 include: [w1-master.yaml]
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | mikro-bus.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 GPIO pins exposed on Mikro BUS headers.
7 The Mikro BUS layout provides two headers, aligned on the opposite
12 … https://download.mikroe.com/documents/standards/mikrobus/mikrobus-standard-specification-v200.pdf
15 numbered 0 - 5 (AN - MOSI), the right side pins are numbered 6 - 10
16 (PWM - SDA). The bottom 2 pins on each side are used for input voltage
19 Analog - AN PWM - PWM output
20 Reset - RST INT - Hardware Interrupt
21 SPI Chip Select - CS RX - UART Receive
22 SPI Clock - SCK TX - UART Transmit
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| /Zephyr-latest/dts/bindings/watchdog/ |
| D | nxp,s32-swt.yaml | 1 # Copyright 2022-2024 NXP
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,s32-swt"
20 master-access-mask:
25 bus master corresponding to the bit. The platform bus master assignments
26 are chip-specific.
29 reset-on-invalid-access:
34 service-mode:
38 - "fixed"
39 - "keyed"
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| /Zephyr-latest/dts/bindings/w1/ |
| D | maxim,ds2482-800-channel.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: DS4282-800, 8-Channel 1-Wire Master (Channel driver)
6 compatible: "maxim,ds2482-800-channel"
8 include: [w1-master.yaml]
10 on-bus: ds2482-800
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| D | maxim,ds2482-800.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: DS4282-800, 8-Channel 1-Wire Master
6 compatible: "maxim,ds2482-800"
8 include: [i2c-device.yaml]
10 bus: ds2482-800
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_rcar.c | 4 * SPDX-License-Identifier: Apache-2.0
20 #include "i2c-priv.h"
39 #define RCAR_I2C_ICMCR 0x04 /* Master Control Register */
41 #define RCAR_I2C_ICMIER 0x14 /* Master IRQ Enable */
43 #define RCAR_I2C_ICMSR 0x0c /* Master Status */
46 #define RCAR_I2C_ICMAR 0x20 /* Master Address Register */
51 #define RCAR_I2C_ICMCR_MDBS BIT(7) /* Master Data Buffer Select */
54 #define RCAR_I2C_ICMCR_OBPC BIT(4) /* Override Bus Pin Control */
55 #define RCAR_I2C_ICMCR_MIE BIT(3) /* Master Interface Enable */
57 #define RCAR_I2C_ICMCR_FSB BIT(1) /* Forced Stop onto the Bus */
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| D | i2c_numaker.c | 4 * SPDX-License-Identifier: Apache-2.0
18 #include "i2c-priv.h"
22 /* i2c Master Mode Status */
24 #define M_REPEAT_START 0x10 /* Master Repeat Start */
25 #define M_TRAN_ADDR_ACK 0x18 /* Master Transmit Address ACK */
26 #define M_TRAN_ADDR_NACK 0x20 /* Master Transmit Address NACK */
27 #define M_TRAN_DATA_ACK 0x28 /* Master Transmit Data ACK */
28 #define M_TRAN_DATA_NACK 0x30 /* Master Transmit Data NACK */
29 #define M_ARB_LOST 0x38 /* Master Arbitration Los */
30 #define M_RECE_ADDR_ACK 0x40 /* Master Receive Address ACK */
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| /Zephyr-latest/tests/drivers/i2c/i2c_target_api/src/ |
| D | main.c | 5 * SPDX-License-Identifier: Apache-2.0
31 * We need 5x(buffer size) + 1 to print a comma-separated list of each
52 TC_PRINT("Testing full read: Master: %s, address: 0x%x\n", in run_full_read()
53 i2c->name, addr); in run_full_read()
55 /* Read EEPROM from I2C Master requests, then compare */ in run_full_read()
69 return -EIO; in run_full_read()
81 TC_PRINT("Testing partial read. Master: %s, address: 0x%x, off=%d\n", in run_partial_read()
82 i2c->name, addr, offset); in run_partial_read()
92 return -EINVAL; in run_partial_read()
96 start_addr, (addr_width >> 3), i2c_buffer, TEST_DATA_SIZE-offset); in run_partial_read()
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| /Zephyr-latest/dts/bindings/i2c/ |
| D | atmel,sam-i2c-twim.yaml | 1 # Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
2 # SPDX-License-Identifier: Apache-2.0
7 The Atmel Two-wire Master Interface (TWIM) interconnects components on a
8 unique two-wire bus, made up of one clock line and one data line with speeds
9 of up to 3.4 Mbit/s, based on a byte-oriented transfer format. The TWIM is
10 always a bus master and can transfer sequential or single bytes. Multiple
11 master capability is supported. Arbitration of the bus is performed
12 internally and relinquishes the bus automatically if the bus arbitration is
20 std-clk-slew-lim = <0>;
21 std-clk-strength-low = "0.5";
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| /Zephyr-latest/samples/drivers/espi/ |
| D | sample.yaml | 3 master
8 - drivers
9 - espi
10 filter: dt_compat_enabled("microchip,mec15xx-board-power")
18 - "Hello eSPI test (.*)"
19 - "eSPI test - I/O initialization...complete"
20 - "eSPI slave configured successfully!"
21 - "eSPI test - callbacks initialization... complete"
22 - "eSPI test - Power initialization...complete"
23 - "eSPI BUS reset (.*)"
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| /Zephyr-latest/samples/bluetooth/hci_spi/ |
| D | README.rst | 1 .. zephyr:code-sample:: bluetooth_hci_spi
3 :relevant-api: hci_raw bluetooth spi_interface
21 You then need to ensure that your :ref:`devicetree <dt-guide>` defines a node
23 :dtcompatible:`zephyr,bt-hci-spi-slave`. This node sets an interrupt line to
24 the host and associates the application with a SPI bus to use.
31 the usual way; see :ref:`boards` for board-specific building and
34 You will also need a separate chip acting as BT HCI SPI master. This
35 application is compatible with the HCI SPI master driver provided by
39 Refer to :zephyr:code-sample-category:`bluetooth` for general Bluetooth information, and
|
| /Zephyr-latest/drivers/dma/ |
| D | Kconfig.dw_axi_dmac | 4 # SPDX-License-Identifier: Apache-2.0
27 This flag can be enabled if hardware support Linked List multi-block transfer
42 int "data bus width"
45 update this flag to change the axi master interface data width
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| /Zephyr-latest/drivers/tee/optee/ |
| D | optee_rpc_cmd.h | 1 /* SPDX-License-Identifier: BSD-2-Clause */
3 * Copyright (c) 2016-2021, Linaro Limited
14 * RPC communication with tee-supplicant is reversed compared to normal
23 * 1970-01-01 00:00:00 +0000 (UTC).
39 * which instead is sent via a non-secure interrupt.
70 /* Memory that can be shared with a non-secure user space application */
72 /* Memory only shared with non-secure kernel */
85 * Issue master requests (read and write operations) to an I2C chip.
88 * [in] value[0].b The I2C bus (a.k.a adapter).
92 * [in] value[1].a The I2C master control flags (ie, 10 bit address).
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| /Zephyr-latest/include/zephyr/arch/arm/mpu/ |
| D | nxp_mpu.h | 4 * SPDX-License-Identifier: Apache-2.0
13 /* Bus Master User Mode Access */
23 /* Bus Master Supervisor Mode Access */
83 #define ENDADDR_ROUND(x) (x - 0x1F)
117 /* ENET (Master 3) and USB (Master 4) devices will not be able
119 DEBUGGER (Master 1) can't be disabled in Region 0. */
141 * (access permissions and cache-ability).
147 /* Read-Write access permission attributes */
161 /* Execution-allowed attributes */
171 * @brief Evaluate Write-ability
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_nxp_s32_emios.c | 4 * SPDX-License-Identifier: Apache-2.0
94 return -EINVAL; in pwm_nxp_s32_set_cycles_internal_timebase()
106 return -EIO; in pwm_nxp_s32_set_cycles_internal_timebase()
128 return -EINVAL; in pwm_nxp_s32_set_cycles_external_timebase()
140 return -EIO; in pwm_nxp_s32_set_cycles_external_timebase()
147 return -EIO; in pwm_nxp_s32_set_cycles_external_timebase()
159 const struct pwm_nxp_s32_config *config = dev->config; in pwm_nxp_s32_set_cycles()
160 struct pwm_nxp_s32_data *data = dev->data; in pwm_nxp_s32_set_cycles()
167 return -EINVAL; in pwm_nxp_s32_set_cycles()
170 if (eMios_Pwm_Ip_IndexInChState[config->instance][channel] >= in pwm_nxp_s32_set_cycles()
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