| /Zephyr-Core-3.5.0/soc/arm/atmel_sam/common/ |
| D | soc_sam4l_gpio.c | 15 uint32_t mask, uint32_t flags) in configure_common_attr() argument
20 gpio->IERC = mask; in configure_common_attr()
24 gpio->PUERS = mask; in configure_common_attr()
26 gpio->PUERC = mask; in configure_common_attr()
31 gpio->PDERS = mask; in configure_common_attr()
33 gpio->PDERC = mask; in configure_common_attr()
38 gpio->ODMERS = mask; in configure_common_attr()
40 gpio->ODMERC = mask; in configure_common_attr()
45 uint32_t mask, uint32_t flags) in configure_input_attr() argument
52 gpio->GFERC = mask; in configure_input_attr()
[all …]
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| D | soc_gpio.c | 24 static void configure_common_attr(Pio *pio, uint32_t mask, uint32_t flags) in configure_common_attr() argument
27 pio->PIO_IDR = mask; in configure_common_attr()
31 pio->PIO_PUER = mask; in configure_common_attr()
33 pio->PIO_PUDR = mask; in configure_common_attr()
40 pio->PIO_PPDER = mask; in configure_common_attr()
42 pio->PIO_PPDDR = mask; in configure_common_attr()
48 pio->PIO_MDER = mask; in configure_common_attr()
50 pio->PIO_MDDR = mask; in configure_common_attr()
54 static void configure_input_attr(Pio *pio, uint32_t mask, uint32_t flags) in configure_input_attr() argument
61 pio->PIO_IFSCER = mask; in configure_input_attr()
[all …]
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| D | soc_sam4l_pm.c | 29 1, /* CPU MASK Instances */
30 10, /* HSB MASK Instances */
31 24, /* PBA MASK Instances */
32 7, /* PBB MASK Instances */
33 5, /* PBC MASK Instances */
34 6, /* PBD MASK Instances */
42 uint32_t mask; in soc_pmc_peripheral_enable() local
54 mask = *(&PM->CPUMASK + bus_id); in soc_pmc_peripheral_enable()
55 mask |= (1U << per_idx); in soc_pmc_peripheral_enable()
60 *(&PM->CPUMASK + bus_id) = mask; in soc_pmc_peripheral_enable()
[all …]
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| /Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/common/include/ |
| D | _soc_inthandlers.h | 14 * order (low bits first) and will return a mask of that bit that can
120 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
124 if (mask & 0x7f) { in _xtensa_handle_one_int1()
125 if (mask & 0x7) { in _xtensa_handle_one_int1()
126 if (mask & BIT(0)) { in _xtensa_handle_one_int1()
127 mask = BIT(0); in _xtensa_handle_one_int1()
131 if (mask & BIT(1)) { in _xtensa_handle_one_int1()
132 mask = BIT(1); in _xtensa_handle_one_int1()
136 if (mask & BIT(2)) { in _xtensa_handle_one_int1()
137 mask = BIT(2); in _xtensa_handle_one_int1()
[all …]
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| /Zephyr-Core-3.5.0/soc/xtensa/espressif_esp32/esp32_net/include/ |
| D | _soc_inthandlers.h | 108 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
112 if (mask & 0x7f) { in _xtensa_handle_one_int1()
113 if (mask & 0x7) { in _xtensa_handle_one_int1()
114 if (mask & BIT(0)) { in _xtensa_handle_one_int1()
115 mask = BIT(0); in _xtensa_handle_one_int1()
119 if (mask & BIT(1)) { in _xtensa_handle_one_int1()
120 mask = BIT(1); in _xtensa_handle_one_int1()
124 if (mask & BIT(2)) { in _xtensa_handle_one_int1()
125 mask = BIT(2); in _xtensa_handle_one_int1()
130 if (mask & 0x18) { in _xtensa_handle_one_int1()
[all …]
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| /Zephyr-Core-3.5.0/soc/xtensa/dc233c/include/ |
| D | _soc_inthandlers.h | 8 * order (low bits first) and will return a mask of that bit that can
84 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
88 if (mask & 0x7f) { in _xtensa_handle_one_int1()
89 if (mask & 0x7) { in _xtensa_handle_one_int1()
90 if (mask & BIT(0)) { in _xtensa_handle_one_int1()
91 mask = BIT(0); in _xtensa_handle_one_int1()
95 if (mask & BIT(1)) { in _xtensa_handle_one_int1()
96 mask = BIT(1); in _xtensa_handle_one_int1()
100 if (mask & BIT(2)) { in _xtensa_handle_one_int1()
101 mask = BIT(2); in _xtensa_handle_one_int1()
[all …]
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/common/include/ |
| D | _soc_inthandlers.h | 12 * order (low bits first) and will return a mask of that bit that can
85 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
89 if (mask & 0x3) { in _xtensa_handle_one_int1()
90 if (mask & BIT(0)) { in _xtensa_handle_one_int1()
91 mask = BIT(0); in _xtensa_handle_one_int1()
95 if (mask & BIT(1)) { in _xtensa_handle_one_int1()
96 mask = BIT(1); in _xtensa_handle_one_int1()
101 if (mask & BIT(2)) { in _xtensa_handle_one_int1()
102 mask = BIT(2); in _xtensa_handle_one_int1()
106 if (mask & BIT(3)) { in _xtensa_handle_one_int1()
[all …]
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/ |
| D | _soc_inthandlers.h | 11 * order (low bits first) and will return a mask of that bit that can
48 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
52 if (mask & BIT(0)) { in _xtensa_handle_one_int1()
53 mask = BIT(0); in _xtensa_handle_one_int1()
57 if (mask & BIT(1)) { in _xtensa_handle_one_int1()
58 mask = BIT(1); in _xtensa_handle_one_int1()
65 return mask; in _xtensa_handle_one_int1()
68 static inline int _xtensa_handle_one_int2(unsigned int mask) in _xtensa_handle_one_int2() argument
72 if (mask & BIT(2)) { in _xtensa_handle_one_int2()
73 mask = BIT(2); in _xtensa_handle_one_int2()
[all …]
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| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | gpio_sam4l.c | 41 uint32_t mask, in gpio_sam_port_configure() argument
53 gpio->IERC = mask; in gpio_sam_port_configure()
54 gpio->PUERC = mask; in gpio_sam_port_configure()
55 gpio->PDERC = mask; in gpio_sam_port_configure()
56 gpio->GPERS = mask; in gpio_sam_port_configure()
57 gpio->ODERC = mask; in gpio_sam_port_configure()
58 gpio->STERC = mask; in gpio_sam_port_configure()
67 gpio->STERS = mask; in gpio_sam_port_configure()
71 gpio->OVRS = mask; in gpio_sam_port_configure()
74 gpio->OVRC = mask; in gpio_sam_port_configure()
[all …]
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| D | gpio_sam.c | 41 static int gpio_sam_port_configure(const struct device *dev, uint32_t mask, in gpio_sam_port_configure() argument
50 pio->PIO_MDER = mask; in gpio_sam_port_configure()
57 pio->PIO_MDDR = mask; in gpio_sam_port_configure()
64 pio->PIO_IDR = mask; in gpio_sam_port_configure()
66 pio->PIO_PUDR = mask; in gpio_sam_port_configure()
72 pio->PIO_PPDDR = mask; in gpio_sam_port_configure()
75 pio->PIO_PER = mask; in gpio_sam_port_configure()
77 pio->PIO_ODR = mask; in gpio_sam_port_configure()
86 pio->PIO_SODR = mask; in gpio_sam_port_configure()
90 pio->PIO_CODR = mask; in gpio_sam_port_configure()
[all …]
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| D | gpio_mmio32.c | 23 * It is possible to specify a restricted mask of bits that are valid for
25 * mask will be preserved, even when the whole port is written to using
39 if ((config->mask & (1 << pin)) == 0) { in gpio_mmio32_config()
40 return -EINVAL; /* Pin not in our validity mask */ in gpio_mmio32_config()
58 *reg = (*reg & (config->mask & ~(1 << pin))); in gpio_mmio32_config()
71 *value = *config->reg & config->mask; in gpio_mmio32_port_get_raw()
77 uint32_t mask, in gpio_mmio32_port_set_masked_raw() argument
85 mask &= config->mask; in gpio_mmio32_port_set_masked_raw()
86 value &= mask; in gpio_mmio32_port_set_masked_raw()
90 *reg = (*reg & ~mask) | value; in gpio_mmio32_port_set_masked_raw()
[all …]
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| D | gpio_nct38xx_port.c | 24 /* GPIO port 0 pinmux mask */
45 uint32_t mask; in gpio_nct38xx_pin_config() local
73 mask = BIT(pin) | ~config->pinmux_mask; in gpio_nct38xx_pin_config()
75 ret = i2c_reg_update_byte_dt(data->i2c_dev, NCT38XX_REG_MUX_CONTROL, mask, new_reg); in gpio_nct38xx_pin_config()
85 mask = BIT(pin); in gpio_nct38xx_pin_config()
87 mask, new_reg); in gpio_nct38xx_pin_config()
93 mask = BIT(pin); in gpio_nct38xx_pin_config()
95 new_reg = mask; in gpio_nct38xx_pin_config()
100 mask, new_reg); in gpio_nct38xx_pin_config()
107 new_reg = mask; in gpio_nct38xx_pin_config()
[all …]
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| D | gpio_kscan_ite_it8xxx2.c | 47 uint8_t mask = BIT(pin); in gpio_kscan_it8xxx2_configure() local
57 *reg_ksi_kso_gctrl |= mask; in gpio_kscan_it8xxx2_configure()
66 *reg_ksi_kso_gpod |= mask; in gpio_kscan_it8xxx2_configure()
69 *reg_ksi_kso_gpod &= ~mask; in gpio_kscan_it8xxx2_configure()
76 *reg_ksi_kso_gdat |= mask; in gpio_kscan_it8xxx2_configure()
78 *reg_ksi_kso_gdat &= ~mask; in gpio_kscan_it8xxx2_configure()
84 *reg_ksi_kso_goen |= mask; in gpio_kscan_it8xxx2_configure()
87 *reg_ksi_kso_goen &= ~mask; in gpio_kscan_it8xxx2_configure()
91 *reg_ksi_kso_gpod |= mask; in gpio_kscan_it8xxx2_configure()
94 *reg_ksi_kso_gpod &= ~mask; in gpio_kscan_it8xxx2_configure()
[all …]
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| D | gpio_npcx.c | 107 uint32_t mask = BIT(pin); in gpio_npcx_config() local
126 inst->PDIR &= ~mask; in gpio_npcx_config()
147 inst->PTYPE |= mask; in gpio_npcx_config()
149 inst->PTYPE &= ~mask; in gpio_npcx_config()
154 inst->PPUD &= ~mask; in gpio_npcx_config()
155 inst->PPULL |= mask; in gpio_npcx_config()
157 inst->PPUD |= mask; in gpio_npcx_config()
158 inst->PPULL |= mask; in gpio_npcx_config()
161 inst->PPULL &= ~mask; in gpio_npcx_config()
166 inst->PDOUT |= mask; in gpio_npcx_config()
[all …]
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/interrupt_controller/ |
| D | wuc_ite_it8xxx2.h | 18 * @param mask Pin mask of WUC group
20 void it8xxx2_wuc_enable(const struct device *dev, uint8_t mask);
27 * @param mask Pin mask of WUC group
29 void it8xxx2_wuc_disable(const struct device *dev, uint8_t mask);
36 * @param mask Pin mask of WUC group
38 void it8xxx2_wuc_clear_status(const struct device *dev, uint8_t mask);
44 * @param mask Pin mask of WUC group
47 void it8xxx2_wuc_set_polarity(const struct device *dev, uint8_t mask,
|
| /Zephyr-Core-3.5.0/soc/xtensa/nxp_adsp/imx8/include/ |
| D | _soc_inthandlers.h | 13 * order (low bits first) and will return a mask of that bit that can
86 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
90 if (mask & BIT(8)) { in _xtensa_handle_one_int1()
91 mask = BIT(8); in _xtensa_handle_one_int1()
98 return mask; in _xtensa_handle_one_int1()
101 static inline int _xtensa_handle_one_int2(unsigned int mask) in _xtensa_handle_one_int2() argument
106 mask &= XCHAL_INTLEVEL2_MASK; in _xtensa_handle_one_int2()
108 if (mask & BIT(i)) { in _xtensa_handle_one_int2()
109 mask = BIT(i); in _xtensa_handle_one_int2()
116 return mask; in _xtensa_handle_one_int2()
[all …]
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| /Zephyr-Core-3.5.0/soc/xtensa/nxp_adsp/imx8m/include/ |
| D | _soc_inthandlers.h | 13 * order (low bits first) and will return a mask of that bit that can
86 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
90 if (mask & BIT(8)) { in _xtensa_handle_one_int1()
91 mask = BIT(8); in _xtensa_handle_one_int1()
98 return mask; in _xtensa_handle_one_int1()
101 static inline int _xtensa_handle_one_int2(unsigned int mask) in _xtensa_handle_one_int2() argument
106 mask &= XCHAL_INTLEVEL2_MASK; in _xtensa_handle_one_int2()
108 if (mask & BIT(i)) { in _xtensa_handle_one_int2()
109 mask = BIT(i); in _xtensa_handle_one_int2()
116 return mask; in _xtensa_handle_one_int2()
[all …]
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| /Zephyr-Core-3.5.0/drivers/hwinfo/ |
| D | hwinfo_mcux_rcm.c | 14 * @brief Translate from RCM reset source mask to Zephyr hwinfo sources mask.
19 * @param NXP MCUX RCM reset source mask.
20 * @retval Zephyr hwinfo reset source mask.
24 uint32_t mask = 0; in hwinfo_mcux_rcm_xlate_reset_sources() local
28 mask |= RESET_LOW_POWER_WAKE; in hwinfo_mcux_rcm_xlate_reset_sources()
33 mask |= RESET_BROWNOUT; in hwinfo_mcux_rcm_xlate_reset_sources()
38 mask |= RESET_CLOCK; in hwinfo_mcux_rcm_xlate_reset_sources()
44 mask |= RESET_PLL; in hwinfo_mcux_rcm_xlate_reset_sources()
49 mask |= RESET_WATCHDOG; in hwinfo_mcux_rcm_xlate_reset_sources()
53 mask |= RESET_PIN; in hwinfo_mcux_rcm_xlate_reset_sources()
[all …]
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| /Zephyr-Core-3.5.0/soc/xtensa/sample_controller/include/ |
| D | _soc_inthandlers.h | 8 * order (low bits first) and will return a mask of that bit that can
83 static inline int _xtensa_handle_one_int0(unsigned int mask) in _xtensa_handle_one_int0() argument
88 static inline int _xtensa_handle_one_int1(unsigned int mask) in _xtensa_handle_one_int1() argument
90 if (mask & 0x7f) { in _xtensa_handle_one_int1()
91 if (mask & 0x7) { in _xtensa_handle_one_int1()
92 if (mask & (1 << 0)) { in _xtensa_handle_one_int1()
98 if (mask & (1 << 1)) { in _xtensa_handle_one_int1()
104 if (mask & (1 << 2)) { in _xtensa_handle_one_int1()
111 if (mask & 0x18) { in _xtensa_handle_one_int1()
112 if (mask & (1 << 3)) { in _xtensa_handle_one_int1()
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/nuvoton/npcx/ |
| D | npcx-miwus-int-map.dtsi | 17 group-mask = <0x02>;
22 group-mask = <0x04>;
33 group-mask = <0x01>;
38 group-mask = <0x02>;
43 group-mask = <0x04>;
48 group-mask = <0x08>;
53 group-mask = <0x10>;
58 group-mask = <0x20>;
63 group-mask = <0x40>;
68 group-mask = <0x80>;
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/nuvoton/npcx/npcx4/ |
| D | npcx4-miwus-int-map.dtsi | 21 group-mask = <0x01>;
26 group-mask = <0x08>;
31 group-mask = <0x10>;
36 group-mask = <0x20>;
41 group-mask = <0x40>;
46 group-mask = <0x80>;
57 group-mask = <0x10>;
62 group-mask = <0x20>;
67 group-mask = <0x40>;
72 group-mask = <0x80>;
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| /Zephyr-Core-3.5.0/drivers/interrupt_controller/ |
| D | wuc_ite_it8xxx2.c | 32 void it8xxx2_wuc_enable(const struct device *dev, uint8_t mask) in it8xxx2_wuc_enable() argument
46 *reg_wuenr |= mask; in it8xxx2_wuc_enable()
49 void it8xxx2_wuc_disable(const struct device *dev, uint8_t mask) in it8xxx2_wuc_disable() argument
63 *reg_wuenr &= ~mask; in it8xxx2_wuc_disable()
66 void it8xxx2_wuc_clear_status(const struct device *dev, uint8_t mask) in it8xxx2_wuc_clear_status() argument
76 *reg_wuesr = mask; in it8xxx2_wuc_clear_status()
79 void it8xxx2_wuc_set_polarity(const struct device *dev, uint8_t mask, uint32_t flags) in it8xxx2_wuc_set_polarity() argument
91 *reg_wubemr &= ~mask; in it8xxx2_wuc_set_polarity()
92 *reg_wuemr &= ~mask; in it8xxx2_wuc_set_polarity()
94 *reg_wubemr &= ~mask; in it8xxx2_wuc_set_polarity()
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/nuvoton/npcx/npcx9/ |
| D | npcx9-miwus-int-map.dtsi | 21 group-mask = <0x01>;
26 group-mask = <0x08>;
31 group-mask = <0x10>;
36 group-mask = <0x20>;
41 group-mask = <0x40>;
46 group-mask = <0x80>;
57 group-mask = <0x20>;
62 group-mask = <0x40>;
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| /Zephyr-Core-3.5.0/dts/riscv/ite/ |
| D | it81xx2.dtsi | 66 func3-en-mask = <0 0 0 0
70 func4-en-mask = <0 0 0 0
74 volt-sel-mask = <0 0 0 0
85 func3-en-mask = <0x01 0x02 0 0
89 func4-en-mask = <0 0 0 0
93 volt-sel-mask = <0 0 0 0x02
104 func3-en-mask = <0 0 0 0x10
108 func4-en-mask = <0 0 0 0
112 volt-sel-mask = <0x80 0x20 0x10 0
123 func3-en-mask = <0 0 0 0
[all …]
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| /Zephyr-Core-3.5.0/dts/bindings/mbox/ |
| D | nordic,mbox-nrf-ipc.yaml | 11 tx-mask:
14 description: TX supported channels mask
16 rx-mask:
19 description: RX supported channels mask
|
