Searched full:latched (Results 1 – 25 of 40) sorted by relevance
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | ti,tca9538.yaml | 31 is not latched. When input latch register bit is 1 and the input
32 pin state is latched.
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| /Zephyr-latest/soc/mediatek/mt8xxx/ |
| D | soc.h | 16 * signaled and cleared. An interrupt is latched if any bits are
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| /Zephyr-latest/drivers/sensor/bosch/bma4xx/ |
| D | bma4xx_emul.h | 23 * whether interrupts are in latched mode. The return value is the current value
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| /Zephyr-latest/drivers/sensor/bosch/bma280/ |
| D | bma280_trigger.c | 114 /* clear latched interrupt */ in bma280_thread_cb()
223 /* set latched interrupts */ in bma280_init_interrupt()
228 LOG_DBG("Could not set latched interrupts"); in bma280_init_interrupt()
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| /Zephyr-latest/dts/bindings/led_strip/ |
| D | ws2812.yaml | 45 latched the signal. If omitted, a default value of 8 microseconds is used.
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | st,lis2de12-common.yaml | 78 and the latched mode when disabled.
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| D | st,lps22df-common.yaml | 36 and the latched mode when disabled.
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| D | st,lis2du12-common.yaml | 97 and the latched mode when disabled.
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| D | st,lsm6dso-common.yaml | 148 and the latched mode when disabled.
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| D | st,lsm6dso16is-common.yaml | 147 and the latched mode when disabled.
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| /Zephyr-latest/soc/microchip/mec/common/reg/ |
| D | mec_tach.h | 54 /* Read-only latched TACH pulse counter */
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| /Zephyr-latest/include/zephyr/drivers/sensor/ |
| D | mcux_lpcmp.h | 79 * 00b: latched
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| /Zephyr-latest/include/zephyr/drivers/interrupt_controller/ |
| D | intc_mchp_xec_ecia.h | 115 /** @brief clear GIRQ latched source status bit
179 /** @brief clear GIRQ latched source status bit
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| /Zephyr-latest/soc/intel/intel_adsp/common/include/ |
| D | cavs-idc.h | 22 * ITC register, an IDC interrupt is latched for the target core.
91 * field indicates interrupts that are currently latched and awaiting
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| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/ |
| D | adsp_interrupt.h | 54 * this is "upstream" of DW: an interrupt will not be latched into the
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| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace20_lnl/ |
| D | adsp_interrupt.h | 52 * this is "upstream" of DW: an interrupt will not be latched into the
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| /Zephyr-latest/soc/intel/intel_adsp/ace/include/ace30/ |
| D | adsp_interrupt.h | 52 * this is "upstream" of DW: an interrupt will not be latched into the
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| /Zephyr-latest/drivers/sensor/microchip/mchp_tach_xec/ |
| D | tach_mchp_xec.c | 62 /* See whether internal counter is already latched */ in tach_xec_sample_fetch()
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| /Zephyr-latest/drivers/sensor/st/lps2xdf/ |
| D | lps2xdf_trigger.c | 173 /* enable drdy in pulsed/latched mode */ in lps2xdf_init_interrupt()
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| /Zephyr-latest/drivers/ethernet/phy/ |
| D | phy_mii.c | 208 /* On some PHY chips, the BMSR bits are latched, so the first read may in update_link_state()
215 /* Second read, clears the latched bits and gives the correct status */ in update_link_state()
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_ite_it8xxx2_v2.c | 197 * isn't latched in a load operation, we read it again to make in get_irq()
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| D | intc_mchp_ecia_xec.c | 460 * GIRQ source(status) bits are latched (R/W1C). The peripheral status
479 /* clear GIRQ latched status */ in xec_girq_isr()
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| /Zephyr-latest/drivers/timer/ |
| D | riscv_machine_timer.c | 130 * but are NOT internally latched for multiword transfers. So in set_mtimecmp()
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| /Zephyr-latest/drivers/sensor/bosch/bmg160/ |
| D | bmg160_trigger.c | 221 /* set interrupt mode to non-latched */ in bmg160_trigger_init()
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| /Zephyr-latest/drivers/led_strip/ |
| D | ws2812_gpio.c | 110 * signal getting latched, so this will be fine as in send_buf()
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