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Searched +full:irq +full:- +full:prio (Results 1 – 25 of 52) sorted by relevance

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/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx-miwus-int-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 npcx-miwus-int-map {
10 map_miwu0_groups: map-miwu0-groups {
11 compatible = "nuvoton,npcx-miwu-int-map";
14 group_b0: group-b0-map {
15 irq = <31>;
16 irq-prio = <2>;
17 group-mask = <0x02>;
19 group_c0: group-c0-map {
20 irq = <15>;
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-miwus-int-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common MIWU group-interrupt mapping configurations in npcx family */
8 #include <nuvoton/npcx/npcx-miwus-int-map.dtsi>
10 /* Specific MIWU group-interrupt mapping configurations in npcx4 series */
13 npcx-miwus-int-map {
14 map_miwu0_groups: map-miwu0-groups {
15 compatible = "nuvoton,npcx-miwu-int-map";
18 group_a0: group-a0-map {
19 irq = <7>;
20 irq-prio = <2>;
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/Zephyr-latest/dts/arm/nuvoton/npcx/npcx9/
Dnpcx9-miwus-int-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common MIWU group-interrupt mapping configurations in npcx family */
8 #include <nuvoton/npcx/npcx-miwus-int-map.dtsi>
10 /* Specific MIWU group-interrupt mapping configurations in npcx9 series */
13 npcx-miwus-int-map {
14 map_miwu0_groups: map-miwu0-groups {
15 compatible = "nuvoton,npcx-miwu-int-map";
18 group_a0: group-a0-map {
19 irq = <7>;
20 irq-prio = <2>;
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/Zephyr-latest/arch/arc/core/
Dirq_manage.c4 * SPDX-License-Identifier: Apache-2.0
14 * - enabling/disabling
16 * An IRQ number passed to the @a irq parameters found in this file is a
17 * number from 16 to last IRQ number on the platform.
26 #include <zephyr/irq.h>
55 /* the z_arc_firq_stack_set must be called when irq diasbled, as in z_arc_firq_stack_set()
87 * Single-core (UP) case:
89 * --------------------------
91 * --------------------------
94 * --------------------------
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/Zephyr-latest/include/zephyr/arch/arm64/
Dirq.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Cortex-A public interrupt handling
11 * ARM64-specific kernel interrupt handling interface.
18 #include <zephyr/irq.h>
38 extern void arch_irq_enable(unsigned int irq);
39 extern void arch_irq_disable(unsigned int irq);
40 extern int arch_irq_is_enabled(unsigned int irq);
43 extern void z_arm64_irq_priority_set(unsigned int irq, unsigned int prio,
54 void z_soc_irq_enable(unsigned int irq);
55 void z_soc_irq_disable(unsigned int irq);
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/Zephyr-latest/drivers/interrupt_controller/
Dintc_vim.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/arch/arm/irq.h>
26 /* Reading IRQVEC register, ACTIRQ gets loaded with valid IRQ values */ in z_vim_irq_get_active()
32 /* Check if the irq number is valid, else return invalid irq number. in z_vim_irq_get_active()
52 void z_vim_irq_eoi(unsigned int irq) in z_vim_irq_eoi() argument
64 void z_vim_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) in z_vim_irq_priority_set() argument
68 if (irq > CONFIG_NUM_IRQS || prio > VIM_PRI_INT_MAX || in z_vim_irq_priority_set()
70 LOG_ERR("%s: Invalid argument irq = %u prio = %u flags = %u\n", in z_vim_irq_priority_set()
71 __func__, irq, prio, flags); in z_vim_irq_priority_set()
75 sys_write8(prio, VIM_PRI_INT(irq)); in z_vim_irq_priority_set()
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/Zephyr-latest/soc/common/riscv-privileged/
Dsoc_common_irq.c2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/irq.h>
20 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
22 riscv_clic_irq_enable(irq); in arch_irq_enable()
25 void arch_irq_disable(unsigned int irq) in arch_irq_disable() argument
27 riscv_clic_irq_disable(irq); in arch_irq_disable()
30 int arch_irq_is_enabled(unsigned int irq) in arch_irq_is_enabled() argument
32 return riscv_clic_irq_is_enabled(irq); in arch_irq_is_enabled()
35 void z_riscv_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) in z_riscv_irq_priority_set() argument
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/Zephyr-latest/modules/hal_nordic/nrf_802154/sl_opensource/platform/
Dnrf_802154_irq_zephyr.c2 * Copyright (c) 2020 - 2021 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/irq.h>
12 void nrf_802154_irq_init(uint32_t irqn, int32_t prio, nrf_802154_isr_t isr) in nrf_802154_irq_init() argument
16 if (prio < 0) { in nrf_802154_irq_init()
17 prio = 0; in nrf_802154_irq_init()
21 irq_connect_dynamic(irqn, prio, isr, NULL, flags); in nrf_802154_irq_init()
36 /* Zephyr does not provide abstraction layer for setting pending IRQ */ in nrf_802154_irq_set_pending()
42 /* Zephyr does not provide abstraction layer for clearing pending IRQ */ in nrf_802154_irq_clear_pending()
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx7/
Dnpcx7-miwus-int-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common MIWU group-interrupt mapping configurations in npcx family */
8 #include <nuvoton/npcx/npcx-miwus-int-map.dtsi>
10 /* Specific MIWU group-interrupt mapping configurations in npcx7 series */
13 npcx-miwus-int-map {
14 map_miwu0_groups: map-miwu0-groups {
15 compatible = "nuvoton,npcx-miwu-int-map";
18 group_ad0: group-ad0-map {
19 irq = <7>;
20 irq-prio = <2>;
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/Zephyr-latest/soc/ti/k3/am6x/r5/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
17 void z_soc_irq_eoi(unsigned int irq) in z_soc_irq_eoi() argument
19 z_vim_irq_eoi(irq); in z_soc_irq_eoi()
27 void z_soc_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) in z_soc_irq_priority_set() argument
30 z_vim_irq_priority_set(irq, prio, flags); in z_soc_irq_priority_set()
33 void z_soc_irq_enable(unsigned int irq) in z_soc_irq_enable() argument
36 z_vim_irq_enable(irq); in z_soc_irq_enable()
39 void z_soc_irq_disable(unsigned int irq) in z_soc_irq_disable() argument
42 z_vim_irq_disable(irq); in z_soc_irq_disable()
45 int z_soc_irq_is_enabled(unsigned int irq) in z_soc_irq_is_enabled() argument
[all …]
/Zephyr-latest/include/zephyr/
Dirq_nextlevel.h4 * SPDX-License-Identifier: Apache-2.0
26 unsigned int irq);
29 unsigned int irq, unsigned int prio,
32 unsigned int irq);
46 * @brief Enable an IRQ in the next level.
51 * @param irq IRQ to be enabled.
54 uint32_t irq) in irq_enable_next_level() argument
57 (const struct irq_next_level_api *)dev->api; in irq_enable_next_level()
59 api->intr_enable(dev, irq); in irq_enable_next_level()
63 * @brief Disable an IRQ in the next level.
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/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Driscv_clic.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Driver for Core-Local Interrupt Controller (CLIC)
18 * @param irq interrupt ID
20 void riscv_clic_irq_enable(uint32_t irq);
25 * @param irq interrupt ID
27 void riscv_clic_irq_disable(uint32_t irq);
32 * @param irq interrupt ID
35 int riscv_clic_irq_is_enabled(uint32_t irq);
40 * @param irq interrupt ID
41 * @param prio interrupt priority
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Driscv_plic.h4 * SPDX-License-Identifier: Apache-2.0
20 * @param irq Multi-level encoded interrupt ID
22 void riscv_plic_irq_enable(uint32_t irq);
27 * @param irq Multi-level encoded interrupt ID
29 void riscv_plic_irq_disable(uint32_t irq);
34 * @param irq Multi-level encoded interrupt ID
37 int riscv_plic_irq_is_enabled(uint32_t irq);
42 * @param irq Multi-level encoded interrupt ID
43 * @param prio interrupt priority
45 void riscv_plic_set_priority(uint32_t irq, uint32_t prio);
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/Zephyr-latest/arch/arm/core/cortex_m/
Dirq_manage.c2 * Copyright (c) 2013-2014 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief ARM Cortex-M interrupt management
25 #include <zephyr/irq.h>
32 #define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG) argument
33 #define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG) argument
37 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
39 NVIC_EnableIRQ((IRQn_Type)irq); in arch_irq_enable()
42 void arch_irq_disable(unsigned int irq) in arch_irq_disable() argument
44 NVIC_DisableIRQ((IRQn_Type)irq); in arch_irq_disable()
[all …]
/Zephyr-latest/boards/native/native_posix/
Dirq_ctrl.c4 * SPDX-License-Identifier: Apache-2.0
6 * HW IRQ controller model
27 * irq handler
41 static bool lock_ignore; /* For the hard fake IRQ, temporarily ignore lock */
44 /* note that prio = 0 == highest, prio=255 == lowest */
46 static int currently_running_prio = 256; /* 255 is the lowest prio interrupt */
75 void hw_irq_ctrl_prio_set(unsigned int irq, unsigned int prio) in hw_irq_ctrl_prio_set() argument
77 irq_prio[irq] = prio; in hw_irq_ctrl_prio_set()
80 uint8_t hw_irq_ctrl_get_prio(unsigned int irq) in hw_irq_ctrl_get_prio() argument
82 return irq_prio[irq]; in hw_irq_ctrl_get_prio()
[all …]
Dirq_ctrl.h4 * SPDX-License-Identifier: Apache-2.0
23 void hw_irq_ctrl_prio_set(unsigned int irq, unsigned int prio);
24 uint8_t hw_irq_ctrl_get_prio(unsigned int irq);
30 void hw_irq_ctrl_disable_irq(unsigned int irq);
31 int hw_irq_ctrl_is_irq_enabled(unsigned int irq);
32 void hw_irq_ctrl_clear_irq(unsigned int irq);
33 void hw_irq_ctrl_enable_irq(unsigned int irq);
34 void hw_irq_ctrl_set_irq(unsigned int irq);
35 void hw_irq_ctrl_raise_im(unsigned int irq);
36 void hw_irq_ctrl_raise_im_from_sw(unsigned int irq);
/Zephyr-latest/arch/xtensa/core/
Dirq_manage.c3 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/arch/xtensa/irq.h>
31 * interrupts are locked system-wide, so care must be taken when using them.
34 void z_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags) in z_irq_priority_set() argument
36 __ASSERT(prio < XCHAL_EXCM_LEVEL + 1, in z_irq_priority_set()
38 prio, XCHAL_EXCM_LEVEL + 1); in z_irq_priority_set()
46 int z_arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, in z_arch_irq_connect_dynamic() argument
53 z_isr_install(irq, routine, parameter); in z_arch_irq_connect_dynamic()
54 return irq; in z_arch_irq_connect_dynamic()
57 int z_arch_irq_connect_dynamic(unsigned int irq, unsigned int priority, in z_arch_irq_connect_dynamic() argument
[all …]
/Zephyr-latest/scripts/native_simulator/native/src/
Dirq_ctrl.c5 * SPDX-License-Identifier: Apache-2.0
7 * HW IRQ controller model
26 * irq handler
40 static bool lock_ignore; /* For the hard fake IRQ, temporarily ignore lock */
43 /* note that prio = 0 == highest, prio=255 == lowest */
45 static int currently_running_prio = 256; /* 255 is the lowest prio interrupt */
71 void hw_irq_ctrl_prio_set(unsigned int irq, unsigned int prio) in hw_irq_ctrl_prio_set() argument
73 irq_prio[irq] = prio; in hw_irq_ctrl_prio_set()
76 uint8_t hw_irq_ctrl_get_prio(unsigned int irq) in hw_irq_ctrl_get_prio() argument
78 return irq_prio[irq]; in hw_irq_ctrl_get_prio()
[all …]
/Zephyr-latest/tests/arch/arm/arm_custom_interrupt/src/
Darm_custom_interrupt.c4 * SPDX-License-Identifier: Apache-2.0
12 unsigned int sw_irq_number = (unsigned int)(-1);
21 * These closely match the normal Cortex-M implementations.
25 #define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG) argument
26 #define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG) argument
30 int irq = 0; in z_soc_irq_init() local
32 for (; irq < CONFIG_NUM_IRQS; irq++) { in z_soc_irq_init()
33 NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET); in z_soc_irq_init()
39 void z_soc_irq_enable(unsigned int irq) in z_soc_irq_enable() argument
41 if (irq == sw_irq_number) { in z_soc_irq_enable()
[all …]
/Zephyr-latest/arch/arm64/core/
Dirq_manage.c4 * SPDX-License-Identifier: Apache-2.0
9 * @brief ARM64 Cortex-A interrupt management
15 #include <zephyr/irq.h>
32 * `include/arch/arm64/irq.h`.
35 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
37 arm_gic_irq_enable(irq); in arch_irq_enable()
40 void arch_irq_disable(unsigned int irq) in arch_irq_disable() argument
42 arm_gic_irq_disable(irq); in arch_irq_disable()
45 int arch_irq_is_enabled(unsigned int irq) in arch_irq_is_enabled() argument
47 return arm_gic_irq_is_enabled(irq); in arch_irq_is_enabled()
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/Zephyr-latest/arch/x86/
Dgen_idt.py5 # SPDX-License-Identifier: Apache-2.0
14 which is a link of the Zephyr kernel without various build-time
27 3. An array which maps configured IRQ lines to their associated
66 gate_type = 0xE # 32-bit interrupt gate
79 gate_type = 0x5 # 32-bit task gate
112 def priority_range(prio): argument
114 base = 32 + (prio * 16)
118 def update_irq_vec_map(irq_vec_map, irq, vector, max_irq): argument
119 # No IRQ associated; exception or software interrupt
120 if irq == -1:
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/Zephyr-latest/include/zephyr/arch/arc/v2/
Darcv2_irq_unit.h1 /* arcv2_irq_unit.h - ARCv2 Interrupt Unit device driver */
7 * SPDX-License-Identifier: Apache-2.0
31 * APIs themselves are writing the IRQ_SELECT, selecting which IRQ's registers
34 * Locking the interrupts inside of the APIs are some kind of self-protection
44 * @param irq IRQ line number
50 int irq, in z_arc_v2_irq_unit_irq_enable_set() argument
56 z_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq); in z_arc_v2_irq_unit_irq_enable_set()
69 void z_arc_v2_irq_unit_int_enable(int irq) in z_arc_v2_irq_unit_int_enable() argument
71 z_arc_v2_irq_unit_irq_enable_set(irq, _ARC_V2_INT_ENABLE); in z_arc_v2_irq_unit_int_enable()
81 void z_arc_v2_irq_unit_int_disable(int irq) in z_arc_v2_irq_unit_int_disable() argument
[all …]
/Zephyr-latest/arch/arm/core/cortex_a_r/
Dirq_manage.c2 * Copyright (c) 2013-2014 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief ARM Cortex-A and Cortex-R interrupt management
25 #include <zephyr/irq.h>
32 * For Cortex-A and Cortex-R cores, the default interrupt controller is the ARM
39 * `include/arch/arm/irq.h`.
43 void arch_irq_enable(unsigned int irq) in arch_irq_enable() argument
45 arm_gic_irq_enable(irq); in arch_irq_enable()
48 void arch_irq_disable(unsigned int irq) in arch_irq_disable() argument
50 arm_gic_irq_disable(irq); in arch_irq_disable()
[all …]
/Zephyr-latest/scripts/native_simulator/native/src/include/
Dirq_ctrl.h5 * SPDX-License-Identifier: Apache-2.0
10 * @brief API to the native simulator - native interrupt controller
25 void hw_irq_ctrl_prio_set(unsigned int irq, unsigned int prio);
26 uint8_t hw_irq_ctrl_get_prio(unsigned int irq);
32 void hw_irq_ctrl_disable_irq(unsigned int irq);
33 int hw_irq_ctrl_is_irq_enabled(unsigned int irq);
34 void hw_irq_ctrl_clear_irq(unsigned int irq);
35 void hw_irq_ctrl_enable_irq(unsigned int irq);
36 void hw_irq_ctrl_set_irq(unsigned int irq);
37 void hw_irq_ctrl_raise_im(unsigned int irq);
[all …]
/Zephyr-latest/dts/bindings/interrupt-controller/
Dnuvoton,npcx-miwu-int-map.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NPCX-MIWU group-interrupt mapping child node
6 compatible: "nuvoton,npcx-miwu-int-map"
14 child-binding:
17 irq:
20 description: irq for miwu group
21 irq-prio:
24 description: irq's priority for miwu group. The valid number is from 0 to 7.
25 group-mask:
28 description: group bit-mask for miwu interrupts

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