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/Zephyr-latest/dts/bindings/interrupt-controller/
Dmicrochip,xec-ecia.yaml1 description: Microchip XEC series External Interrupt Aggregator Controller
3 compatible: "microchip,xec-ecia"
14 direct-capable-girqs:
/Zephyr-latest/snippets/xen_dom0/boards/
Drcar_h3ulcb_r8a77951_a57.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /delete-node/ &ram;
8 /delete-node/ &scif2;
14 * (XEN) Grant table range: 0x00000088080000-0x000000880c0000
17 * is not capable to parse and handle it in runtime.
23 interrupt-parent = <&gic>;
29 * region for Domain-0 for every specific configuration. You can
32 * (XEN) BANK[0] 0x00000060000000-0x00000070000000 (256MB)
35 * is not capable to parse and handle it in runtime.
38 device_type = "mmio-sram";
Drcar_salvator_xs.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /delete-node/ &ram;
8 /delete-node/ &scif2;
14 * (XEN) Grant table range: 0x00000088080000-0x000000880c0000
17 * is not capable to parse and handle it in runtime.
23 interrupt-parent = <&gic>;
29 * region for Domain-0 for every specific configuration. You can
32 * (XEN) BANK[0] 0x00000060000000-0x00000070000000 (256MB)
35 * is not capable to parse and handle it in runtime.
38 device_type = "mmio-sram";
Dqemu_cortex_a53.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /delete-node/ &sram0;
18 * (XEN) Grant table range: 0x00000040200000-0x00000040240000
21 * is not capable to parse and handle it in runtime.
27 interrupt-parent = <&gic>;
33 * region for Domain-0 for every specific configuration. You can
36 * (XEN) BANK[0] 0x00000058000000-0x00000060000000 (128MB)
39 * is not capable to parse and handle it in runtime.
43 device_type = "mmio-sram";
Drcar_spider_s4_r8a779f0_a55.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /delete-node/ &ram;
8 /delete-node/ &hscif0;
14 * (XEN) Grant table range: 0x00000078080000-0x000000780c0000
16 * (XEN) Extended region 1: 0x40000000->0x47e00000
19 * is not capable to parse and handle it in runtime.
25 interrupt-parent = <&gic>;
31 * region for Domain-0 for every specific configuration. You can
34 * (XEN) BANK[0] 0x00000080000000-0x00000090000000 (256MB)
37 * is not capable to parse and handle it in runtime.
[all …]
/Zephyr-latest/tests/kernel/interrupt/src/
Dprevent_irq.c4 * SPDX-License-Identifier: Apache-2.0
27 * @brief Test interrupt prevention
31 * This routine tests if the kernel is capable of preventing interruption, by
32 * locking interrupts and busy-waiting to see if the system timer interrupt is
34 * that the system timer interrupt is serviced after interrupts are unlocked.
47 /* Start the timer and busy-wait for a bit with IRQs locked. The in ZTEST()
49 * locked -- but since they are, check_lock_new isn't updated. in ZTEST()
54 "timer interrupt was serviced while interrupts are locked"); in ZTEST()
/Zephyr-latest/lib/os/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
29 preempting interrupt.
35 Enable usage of mpsc packet buffer. Packet buffer is capable of
42 Enable usage of spsc packet buffer. Packet buffer is capable of
/Zephyr-latest/samples/sensor/adt7420/
DREADME.rst1 .. zephyr:code-sample:: adt7420
2 :name: ADT7420 high-accuracy digital I2C temperature sensor
3 :relevant-api: sensor_interface
16 interrupt causes the application to display an event and update the
22 - ADT7420: https://www.analog.com/adt7420
29 and optionally connect the **INT** to a interrupt capable GPIO.
31 Depending on the baseboard used, the **SDA** and **SCL** lines require Pull-Up
43 .. zephyr-app-commands::
44 :zephyr-app: samples/sensor/adt7420
51 .. code-block:: console
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/Zephyr-latest/dts/bindings/gpio/
Dxlnx,ps-gpio.yaml3 # SPDX-License-Identifier: Apache-2.0
7 Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller node.
9 This GPIO controller is contained in both the Xilinx Zynq-7000 and
11 which can be mapped in the system design tools (MIO pins), or SoC-
18 Zynq-7000 (comp. Zynq-7000 TRM, chap. 14.1.2, p. 381):
32 The controller is interrupt-capable. Certain pins both in the Zynq-
36 compatible: "xlnx,ps-gpio"
/Zephyr-latest/samples/sensor/sht3xd/
DREADME.rst1 .. zephyr:code-sample:: sht3xd
3 :relevant-api: sensor_interface
17 …- `SHT3X-DIS sensor <https://www.sensirion.com/en/environmental-sensors/humidity-sensors/digital-h…
24 and optionally connect the **ALERT** to a interrupt capable GPIO.
26 Depending on the baseboard used, the **SDA** and **SCL** lines require Pull-Up
38 .. zephyr-app-commands::
39 :zephyr-app: samples/sensor/sht3xd
46 .. code-block:: console
/Zephyr-latest/include/zephyr/drivers/usb/
Dudc.h2 * Copyright (c) 2021-2022 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
37 /** USB high speed capable controller */
71 /** Control transfer capable endpoint (for completeness) */
73 /** Interrupt transfer capable endpoint */
74 uint32_t interrupt : 1; member
75 /** Bulk transfer capable endpoint */
77 /** ISO transfer capable endpoint */
79 /** High-Bandwidth (interrupt or iso) capable endpoint */
81 /** IN transfer capable endpoint */
[all …]
/Zephyr-latest/tests/arch/x86/info/src/
Dacpi.c2 * SPDX-License-Identifier: Apache-2.0
15 return "PCI Sub-hierarchy"; in get_dmar_scope_type()
19 return "MSI Capable HPET"; in get_dmar_scope_type()
21 return "ACPI name-space enumerated"; in get_dmar_scope_type()
31 printk("\t\t\t. Scope type %s\n", get_dmar_scope_type(devscope->EntryType)); in dmar_devsope_handler()
32 printk("\t\t\t. Enumeration ID %u\n", devscope->EnumerationId); in dmar_devsope_handler()
34 if (devscope->EntryType < ACPI_DMAR_SCOPE_TYPE_RESERVED) { in dmar_devsope_handler()
36 int num_path = (devscope->Length - 6u) / 2u; in dmar_devsope_handler()
42 while (num_path--) { in dmar_devsope_handler()
43 printk("\t\t\t. PCI Path %02x:%02x.%02x\n", devscope->Bus, in dmar_devsope_handler()
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/Zephyr-latest/dts/bindings/misc/
Dnxp,s32-emios.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-emios"
21 interrupt-names:
27 clock-divider:
33 internal-cnt:
39 child-binding:
40 child-binding:
42 Node for eMIOS master bus. Each channel is capable to become a master bus has
52 bus-type = "BUS_A";
53 channel-mask = <0x07FFFFF>;
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/Zephyr-latest/arch/x86/core/ia32/
Dirq_manage.c2 * Copyright (c) 2010-2014 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Interrupt support for IA-32 arch
30 * Place the addresses of the spurious interrupt handlers into the intList
82 * @brief Allocate a free interrupt vector given <priority>
87 * This routine assumes that the relationship between interrupt priority and
88 * interrupt vector is :
90 * priority = (vector / 16) - 2;
94 * Each interrupt priority level contains 16 vectors.
96 * It is also assumed that the interrupt controllers are capable of managing
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Dfloat.c2 * Copyright (c) 2010-2014 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
73 * @brief Save non-integer context information
75 * This routine saves the system's "live" non-integer context into the
89 * @brief Save non-integer context information
91 * This routine saves the system's "live" non-integer context into the
134 if ((thread->base.user_options & K_SSE_REGS) != 0) { in FpCtxSave()
135 z_do_fp_and_sse_regs_save(&thread->arch.preempFloatReg); in FpCtxSave()
139 z_do_fp_regs_save(&thread->arch.preempFloatReg); in FpCtxSave()
152 if ((thread->base.user_options & K_SSE_REGS) != 0) { in FpCtxInit()
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/Zephyr-latest/kernel/
DKconfig.smp2 # SPDX-License-Identifier: Apache-2.0
15 bool "Use new-style _arch_switch instead of arch_swap"
20 for an SMP-aware scheduler, or if the architecture does not
46 Maximum number of multiprocessing-capable cores available to the
53 to broadcast an interrupt that will call z_sched_ipi() on other CPUs
56 thread to take an interrupt, which can be arbitrarily far in the
105 where all shared data is placed in multiprocessor-coherent
109 running on cache-incoherent architectures only. Note that
124 in a live-lock.
/Zephyr-latest/drivers/timer/
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
6 # SPDX-License-Identifier: Apache-2.0
16 available to provide values from a 64-bit cycle counter.
46 Timer drivers should select this flag if they are capable of
50 sys_clock_announce() (really, not to produce an interrupt at
/Zephyr-latest/boards/st/b_g474e_dpow1/doc/
Dindex.rst5 The B-G474E-DPOW1 Discovery kit is a digital power solution and a complete
7 microcontroller. Leveraging the new HRTimer-oriented features, 96 Kbytes of
8 embedded RAM, math accelerator functions and USB-PD 3.0 offered by STM32G474RET6,
9 the B-G474E-DPOW1 Discovery kit, based on the USB 2.0 FS Type-C™ connector
11 buck-boost converter, RGB power LED lighting or a class-D audio amplifier. The
12 B-G474E-DPOW1 Discovery kit does not require any separate probe, as it integrates
13 the STLINK-V3E debugger and programmer.
15 - STM32G474RET6 Arm® Cortex®-M4 core-based microcontroller, featuring 512 Kbytes
17 - USB Type-C™ with USB 2.0 FS interface compatible with USB-PD 3.0
18 - RGB power LED for a bright lighting
[all …]
/Zephyr-latest/boards/st/stm32vl_disco/doc/
Dindex.rst8 integrated ST-LINK debugger and programmer is included (V1), but the only
18 - On-board ST-LINK/V1 with selection mode switch to use the kit as a standalone
19 ST-LINK/V1 (with SWD connector for programming and debugging)
20 - Board power supply: through USB bus or from an external 5 V supply voltage
21 - External application power supply: 3 V and 5 V
22 - Four LEDs:
24 - LD1 (red) for 3.3 V power on
25 - LD2 (red/green) for USB communication
26 - LD3 (green) for PC9 output
27 - LD4 (blue) for PC8 output
[all …]
/Zephyr-latest/include/zephyr/drivers/pcie/
Dmsi.h4 * SPDX-License-Identifier: Apache-2.0
68 * @param priority the MSI vectors base interrupt priority
84 * @param routine Interrupt service routine
86 * @param flags Arch-specific IRQ configuration flag
106 * @return A (32-bit) value for the MSI MAP register.
119 * @return A (16-bit) value for MSI MDR register.
139 * @brief Check if the given PCI endpoint supports MSI/MSI-X
142 * @return true if the endpoint support MSI/MSI-X
154 #define PCIE_MSI_MCR_MMC 0x000E0000U /* Multi Messages Capable mask */
158 #define PCIE_MSI_MCR_64 0x00800000U /* 64-bit MSI */
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/Zephyr-latest/samples/sensor/fdc2x1x/
DREADME.rst1 .. zephyr:code-sample:: fdc2x1x
2 :name: FDC2X1X Capacitance-to-Digital Converter
3 :relevant-api: sensor_interface
12 to read the 12-Bit and 28-Bit, as well as the 2-Channel and 4-Channel versions
13 (FDC2112, FDC2114, FDC2212, FDC2214). The 4-channel versions are chosen through
14 devicetree properties. The default in this sample is the 2-channel version.
16 Capacitive sensing is a low-power, low-cost, high-resolution contactless sensing
23 architecture, performance can be maintained even in presence of high-noise environments.
36 interrupt capable GPIO.
39 at pages 4-5.
[all …]
/Zephyr-latest/boards/st/stm32l1_disco/doc/
Dindex.rst7 an integrated ST-LINK/V2 debugger and programmer. The boards have a
8 24-segment LCD and a touch slider, along with two user LEDs and a user button.
16 - STM32LDISCOVERY targets STM32L152RBT6, with 128K flash, 16K RAM, 4K EEPROM
17 - STM32L152CDISCOVERY targets STM32L152RCT6, with 256K flash, 32K RAM, 8K EEPROM
31 - On-board ST-LINK/V2 with selection mode switch to use the kit as a standalone
32 ST-LINK/V2 (with SWD connector for programming and debugging)
33 - Board power supply: through USB bus or from an external 5 V supply voltage
34 - External application power supply: 3 V and 5 V
35 - Four LEDs:
37 - LD1 (red) for 3.3 V power on
[all …]
/Zephyr-latest/dts/arm/microchip/
Dmec5.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m4";
32 reg-names = "pcrr", "vbatr";
38 #address-cells = <1>;
39 #size-cells = <1>;
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/Zephyr-latest/soc/nordic/nrf53/
Dsync_rtc.c4 * SPDX-License-Identifier: Apache-2.0
20 * are significant interrupt handling latencies.
25 static int32_t nrf53_sync_offset = -EBUSY;
47 * APP: setup PPI connection from IPC_RECEIVE to RTC CAPTURE, enable interrupt
53 * capable of calculating the offset since it know what counter value corresponds
64 * Note, arbitrary delay is used to accommodate for the case when NET-APP offset
65 * is small enough that interrupt latency would impact it. NET-APP offset depends
124 return -ENOSYS; in z_nrf_rtc_timer_nrf53net_offset_get()
180 nrf53_sync_offset = cc - RTC_SYNC_ARBITRARY_DELAY - 2 * sync_cc; in remote_callback()
214 return -ENODEV; in mbox_rx_init()
[all …]
/Zephyr-latest/include/zephyr/drivers/
Di3c.h5 * SPDX-License-Identifier: Apache-2.0
42 * - BCR[7:6]: Device Role
43 * - 0: I3C Target
44 * - 1: I3C Controller capable
45 * - 2: Reserved
46 * - 3: Reserved
48 * - BCR[5]: Advanced Capabilities
49 * - 0: Does not support optional advanced capabilities.
50 * - 1: Supports optional advanced capabilities which
53 * - BCR[4]: Virtual Target Support
[all …]

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