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/Zephyr-latest/dts/bindings/clock/
Dst,stm32wl-hse-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: STM32WL HSE Clock
6 compatible: "st,stm32wl-hse-clock"
8 include: [fixed-clock.yaml]
11 hse-tcxo:
14 When set, TCXO is selected as external source clock for HSE.
15 Otherwise, external crystal is selected as HSE source clock.
17 hse-div2:
20 When set HSE output clock is divided by 2.
/Zephyr-latest/dts/arm/seeed_studio/
Dlora-e5.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <st/wl/stm32wle5jcix-pinctrl.dtsi>
11 clock-frequency = <DT_FREQ_M(32)>;
12 hse-tcxo;
16 clock-frequency = <32768>;
23 tx-enable-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
24 rx-enable-gpios = <&gpioa 5 GPIO_ACTIVE_LOW>;
25 dio3-tcxo-voltage = <SX126X_DIO3_TCXO_1V7>;
26 tcxo-power-startup-delay-ms = <5>;
27 power-amplifier-output = "rfo-hp";
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dwl_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwb_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwb_i2c1_hsi_lptim1_lse.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/
Dwl_32_hse.overlay4 * SPDX-License-Identifier: Apache-2.0
10 * It applies to the stm32wl where the hse prescaler is 1 and by-passed
14 hse-tcxo;
15 clock-frequency = <DT_FREQ_M(32)>;
21 clock-frequency = <DT_FREQ_M(32)>;
Dwl_pll_48_hse_32.overlay4 * SPDX-License-Identifier: Apache-2.0
10 * It applies to the stm32wl where the hse prescaler is 2 and by-passed
14 hse-tcxo;
15 hse-div2;
16 clock-frequency = <DT_FREQ_M(32)>;
21 div-m = <2>;
22 mul-n = <12>;
23 div-p = <2>;
24 div-q = <2>;
25 div-r = <2>;
[all …]
Dclear_clocks.overlay4 * SPDX-License-Identifier: Apache-2.0
14 /delete-property/ hse-bypass;
15 /delete-property/ clock-frequency;
16 /delete-property/ hse-tcxo;
17 /delete-property/ hse-div2;
22 /delete-property/ hsi-div;
26 /delete-property/ div-m;
27 /delete-property/ mul-n;
28 /delete-property/ div-p;
29 /delete-property/ div-q;
[all …]
/Zephyr-latest/boards/seeed/lora_e5_mini/doc/
Dindex.rst6 LoRa-E5 mini is a compacted-sized development board suitable for the rapid
7 testing and building of small-sized LoRa device, exposing all capabilities of
8 Seeed Studio LoRa-E5 STM32WLE5JC module.
13 The boards' LoRa-E5 Module packages a STM32WLE5JC SOC, a 32MHz TCXO,
14 and a 32.768kHz crystal oscillator in a 28-pin SMD package.
15 This STM32WLEJC SOC is powered by ARM Cortex-M4 core and integrates Semtech
18 - LoRa-E5 STM32WLE5JC Module with STM32WLE5JC multiprotocol LPWAN single-core
19 32-bit microcontroller (Arm® Cortex®-M4 at 48 MHz) in 28-pin SMD package
22 - Ultra-low-power MCU
23 - RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa®,
[all …]
/Zephyr-latest/boards/seeed/lora_e5_dev_board/doc/
Dlora_e5_dev_board.rst6 The LoRa-E5 Dev Board is a compact board for the evaluation of the
7 Seeed Studio LoRa-E5 STM32WLE5JC module.
8 The LoRa-E5-HF STM32WLE5JC Module supports multiple LPWAN protocols on the
10 All GPIOs of the LoRa-E5 Module are laid out supporting
11 various data protocols and interfaces including RS-485 and Grove.
16 The boards LoRa-E5 Module packages a STM32WLE5JC SOC, a 32MHz TCXO,
17 and a 32.768kHz crystal oscillator in a 28-pin SMD package.
18 This STM32WLEJC SOC is powered by ARM Cortex-M4 core and integrates Semtech
21 - LoRa-E5 STM32WLE5JC Module with STM32WLE5JC multiprotocol LPWAN single-core
22 32-bit microcontroller (Arm® Cortex®-M4 at 48 MHz) in 28-pin SMD package
[all …]
/Zephyr-latest/boards/st/nucleo_wl55jc/doc/
Dnucleo_wl55jc.rst6 The NUCLEO-WL55JC STM32WL Nucleo-64 board provides an affordable and flexible
11 - STM32WL55JC microcontroller multiprotocol LPWAN dual-core 32-bit
12 (Arm® Cortex®-M4/M0+ at 48 MHz) in UFBGA73 package featuring:
14 - Ultra-low-power MCU
15 - RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa®,
17 - 256-Kbyte Flash memory and 64-Kbyte SRAM
19 - 3 user LEDs
20 - 3 user buttons and 1 reset push-button
21 - 32.768 kHz LSE crystal oscillator
22 - 32 MHz HSE on-board oscillator
[all …]