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/Zephyr-latest/dts/riscv/ite/
Dit82xx2.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 compatible = "mmio-sram";
16 intc: interrupt-controller@f03f00 {
17 compatible = "ite,it8xxx2-intc-v2";
18 #address-cells = <0>;
19 #interrupt-cells = <2>;
20 interrupt-controller;
25 compatible = "ite,it8xxx2-watchdog";
29 interrupt-parent = <&intc>;
32 gpiogcr: gpio-gcr@f03e00 {
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/Zephyr-latest/dts/bindings/gpio/
Dite,it8xxx2-gpio-v2.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ite,it8xxx2-gpio-v2"
8 include: [gpio-controller.yaml, base.yaml]
14 has-volt-sel:
19 wuc-base:
24 a wake-up signal to the INTC, allowing the CPU to exit
27 wuc-mask:
30 keyboard-controller:
33 When set, this GPIO controller has pins associated with the
37 when the judgment of gpio_config->ksb_ctrl is true.
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/Zephyr-latest/tests/drivers/gpio/gpio_ite_it8xxx2_v2/boards/
Dnative_sim.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
8 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
12 intc: interrupt-controller@f03f00 {
14 #address-cells = <0>;
15 #interrupt-cells = <2>;
16 interrupt-controller;
21 compatible = "ite,it8xxx2-gpio-v2";
28 gpio-controller;
37 interrupt-parent = <&intc>;
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/Zephyr-latest/doc/releases/
Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
124 * Python's argparse argument parser usage in Zephyr scripts has been updated
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/Zephyr-latest/boards/snps/hsdk4xd/doc/
Dindex.rst7 It includes a multicore ARC HS4xD-based chip that integrates a wide range of interfaces
12 (HSDK4xD) <https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit>`__
17 The ARC HSDK4xD has 24 general GPIOs, which divided into 8 groups named from ``GPIO_SEL_0`` to ``GP…
18 Each sel can configured for different functions, such as: GPIO, UART, SPI, I2C and PWM. We can prog…
19 ``CREG_GPIO_MUX`` register to do configuration for each sel. Tables below show the bit definition f…
22 +--------+-------------+---------+--------------+---------------------------------+
24 +--------+-------------+---------+--------------+---------------------------------+
26 +--------+-------------+---------+--------------+---------------------------------+
28 +--------+-------------+---------+--------------+---------------------------------+
30 +--------+-------------+---------+--------------+---------------------------------+
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/Zephyr-latest/boards/snps/hsdk/doc/
Dindex.rst6 The DesignWare(R) ARC(R) HS Development Kit is a ready-to-use platform for
8 single-core and multi-core ARC HS34, HS36 and HS38 processors and offers a wide
15 (HSDK) <https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit>`__
20 The ARC HSDK has 24 general GPIOs, which divided into 8 groups named from GPIO_SEL_0 to GPIO_SEL_7.
21 Each sel can configured for different functions, such as: GPIO, UART, SPI, I2C and PWM. We can prog…
22 CREG_GPIO_MUX register to do configuration for each sel. Tables below show the bit definition for
25 +--------+-------------+---------+--------------+---------------------------------+
27 +--------+-------------+---------+--------------+---------------------------------+
29 +--------+-------------+---------+--------------+---------------------------------+
31 +--------+-------------+---------+--------------+---------------------------------+
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