Home
last modified time | relevance | path

Searched +full:girq +full:- +full:id (Results 1 – 14 of 14) sorted by relevance

/Zephyr-latest/dts/bindings/interrupt-controller/
Dmicrochip,xec-ecia-girq.yaml1 description: Microchip XEC series External Interrupt Aggregator GIRQ
3 compatible: "microchip,xec-ecia-girq"
14 girq-id:
17 description: GIRQ ID number [0, 18]
23 Bit positions of each source implemented by this GIRQ.
/Zephyr-latest/dts/arm/microchip/
Dmec172x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "microchip,xec-pcr";
13 reg-names = "pcrr", "vbatr";
15 core-clock-div = <1>;
17 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
18 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
19 clk32kmon-period-min = <1435>;
20 clk32kmon-period-max = <1495>;
21 clk32kmon-duty-cycle-var-max = <132>;
22 clk32kmon-valid-min = <4>;
[all …]
Dmec1501hsz.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4";
[all …]
/Zephyr-latest/dts/bindings/gpio/
Dmicrochip,xec-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-gpio"
8 include: [gpio-controller.yaml, base.yaml]
14 port-id:
19 girq-id:
22 description: Aggregated GIRQ number for this bank of 32 GPIO pins.
24 "#gpio-cells":
27 gpio-cells:
28 - pin
29 - flags
Dmicrochip,xec-gpio-v2.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-gpio-v2"
8 include: [gpio-controller.yaml, base.yaml]
14 port-id:
19 girq-id:
22 description: Aggregated GIRQ number for this bank of 32 GPIO pins.
24 "#gpio-cells":
27 gpio-cells:
28 - pin
29 - flags
/Zephyr-latest/drivers/interrupt_controller/
Dintc_mchp_ecia_xec.c4 * SPDX-License-Identifier: Apache-2.0
22 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
30 #define GIRQ_ID_TO_BITPOS(id) ((id) + 8) argument
72 ((const struct xec_ecia_config *const)(ecia_dev)->config)
75 ((const struct xec_girq_config *const)(girq_dev)->config)
78 ((struct xec_girq_src_data *const)(girq_dev)->data)
81 * Enable/disable specified GIRQ's aggregated output. Aggregated output is the
82 * bit-wise or of all the GIRQ's result bits.
89 regs->BLK_EN_SET = BIT(girq_num); in mchp_xec_ecia_girq_aggr_en()
91 regs->BLK_EN_CLR = BIT(girq_num); in mchp_xec_ecia_girq_aggr_en()
[all …]
/Zephyr-latest/drivers/espi/
Despi_mchp_xec_v2.h4 * SPDX-License-Identifier: Apache-2.0
27 void (*the_isr)(int girq, int bpos, void *dev);
31 uint8_t gid; /* GIRQ id [8, 26] */
32 uint8_t gpos; /* bit position in GIRQ [0, 31] */
33 uint8_t anid; /* Aggregated GIRQ NVIC number */
34 uint8_t dnid; /* Direct GIRQ NVIC number */
49 ((struct espi_xec_config * const)(dev)->config)
62 ((struct espi_xec_data * const)(dev)->data)
Despi_saf_mchp_xec_v2.c5 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
27 /* SAF EC Portal read/write flash access limited to 1-64 bytes */
41 /* Get QMSPI 0 encoded GIRQ information */
61 * Delay before first Poll-1 command after suspend in 20 ns units
99 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
107 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
109 regs->SAF_CS1_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
117 regs->SAF_CS0_CM_PRF = val; in mchp_saf_cm_prefix_wr()
119 regs->SAF_CS1_CM_PRF = val; in mchp_saf_cm_prefix_wr()
[all …]
Despi_mchp_xec_v2.c5 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
40 * length specified is non-zero.
61 ((struct espi_iom_regs *)ESPI_XEC_CONFIG(dev)->base_addr)
64 ((struct espi_msvw_ar_regs *)(ESPI_XEC_CONFIG(dev)->vw_base_addr))
70 (ESPI_XEC_CONFIG(dev)->vw_base_addr + ESPI_XEC_SMVW_REG_OFS))
77 * ------------------------------------------------------------------------|
79 * ------------------------------------------------------------------------|
81 * ------------------------------------------------------------------------|
88 * ------------------------------------------------------------------------|
[all …]
/Zephyr-latest/drivers/sensor/microchip/mchp_tach_xec/
Dtach_mchp_xec.c5 * SPDX-License-Identifier: Apache-2.0
31 uint8_t girq; member
54 const struct tach_xec_config * const cfg = dev->config; in tach_xec_sample_fetch()
55 struct tach_xec_data * const data = dev->data; in tach_xec_sample_fetch()
56 struct tach_regs * const tach = cfg->regs; in tach_xec_sample_fetch()
63 if (tach->STATUS & MCHP_TACH_STS_CNT_RDY) { in tach_xec_sample_fetch()
64 data->count = in tach_xec_sample_fetch()
65 tach->CONTROL >> MCHP_TACH_CTRL_COUNTER_POS; in tach_xec_sample_fetch()
78 return -EINVAL; in tach_xec_sample_fetch()
82 if (data->count == FAN_STOPPED) { in tach_xec_sample_fetch()
[all …]
/Zephyr-latest/drivers/spi/
Dspi_xec_qmspi_ldma.c4 * SPDX-License-Identifier: Apache-2.0
20 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
21 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
35 * data bytes will be left shifted by 1. Work-around for SPI Mode 3 is
79 uint8_t girq; member
123 return -ETIMEDOUT; in xec_qmspi_spin_yield()
133 * Some QMSPI timing register may be modified by the Boot-ROM OTP
144 taps[0] = regs->TM_TAPS; in qmspi_reset()
145 taps[1] = regs->TM_TAPS_ADJ; in qmspi_reset()
146 taps[2] = regs->TM_TAPS_CTRL; in qmspi_reset()
[all …]
/Zephyr-latest/drivers/dma/
Ddma_mchp_xec.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
105 uint8_t gid; /* GIRQ id [8, 26] */
106 uint8_t gpos; /* bit position in GIRQ [0, 31] */
166 return &devcfg->irq_info_list[channel]; in xec_chan_irq_info()
187 if ((src | dest) & (unitsz - 1U)) { in is_data_aligned()
197 chregs->actv = 0; in xec_dma_chan_clr()
198 chregs->control = 0; in xec_dma_chan_clr()
199 chregs->mem_addr = 0; in xec_dma_chan_clr()
200 chregs->mem_addr_end = 0; in xec_dma_chan_clr()
[all …]
/Zephyr-latest/drivers/serial/
Duart_mchp_xec.c2 * Copyright (c) 2010, 2012-2015 Wind River Systems, Inc.
6 * SPDX-License-Identifier: Apache-2.0
57 #define REG_IIR 0x02 /* Interrupt ID reg. */
81 #define IIR_MASK 0x07 /* interrupt id bits mask */
82 #define IIR_ID 0x06 /* interrupt ID mask without NIP */
97 * RXRDY pin will go inactive when there are no more charac-
102 * reached, the RXRDY pin will go low active. Once it is acti-
107 * FIFO Mode (FCR0 = 1, FCR3 = 0) and there are no charac-
173 #define IIRC(dev) (((struct uart_xec_dev_data *)(dev)->data)->iir_cache)
242 struct uart_xec_device_config const *dev_cfg = dev->config; in uart_clr_slp_en()
[all …]
/Zephyr-latest/doc/releases/
Drelease-notes-2.7.rst17 * Support for M-Profile Vector Extensions (MVE) on ARMv8.1-M
18 * Improved thread safety for Newlib and C++ on SMP-capable systems
20 * New Action-based Power Management API
23 * Linker Support for Tightly-Coupled Memory in RISC-V
25 * Support for extended PCI / PCIe capabilities, improved MIS-X support
33 * The kernel now supports both 32- and 64-bit architectures
36 * We added support for Point-to-Point Protocol (PPP)
37 * We added support for UpdateHub, an end-to-end solution for over-the-air device updates
38 * We added support for ARM Cortex-R Architecture
40 * Expanded support for ARMv6-M architecture
[all …]