Searched +full:gcc +full:- +full:multilib (Results 1 – 7 of 7) sorted by relevance
| /Zephyr-latest/boards/cdns/xt-sim/doc/ |
| D | index.rst | 1 .. zephyr:board:: xt-sim
7 synthesizable 32-bit RISC processor core. Processor and SOC vendors can select
11 For more information, see https://ip.cadence.com/ipportfolio/tensilica-ip/xtensa-customizable
18 - sample_controller
33 releases (with multilib support).
35 Only Xtensa tools version ``RF-2016.4-linux`` or later are officially
38 In order to set up the Zephyr OS build system, a Linux 32-bit GCC compiler must
39 be installed on the building linux box. Install GCC if needed either by
42 On Debian/Ubuntu systems, you can install ``gcc-multilib`` package as follows:
44 .. code-block:: console
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| /Zephyr-latest/doc/develop/getting_started/ |
| D | index.rst | 8 - Set up a command-line Zephyr development environment on Ubuntu, macOS, or
11 - Get the source code
12 - Build, flash, and run a sample application
23 .. group-tab:: Ubuntu
28 .. code-block:: bash
33 .. group-tab:: macOS
39 <https://support.apple.com/en-us/HT201541>`_.
41 .. group-tab:: Windows
46 .. _install-required-tools:
55 .. list-table::
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| D | installation_linux.rst | 32 .. group-tab:: Ubuntu
34 .. code-block:: console
36 sudo apt-get update
37 sudo apt-get upgrade
39 .. group-tab:: Fedora
41 .. code-block:: console
45 .. group-tab:: Clear Linux
47 .. code-block:: console
51 .. group-tab:: Arch Linux
53 .. code-block:: console
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| /Zephyr-latest/boards/openisa/rv32m1_vega/doc/ |
| D | index.rst | 8 The VEGAboard contains the RV32M1 SoC, featuring two RISC-V CPUs,
9 on-die XIP flash, and a full complement of peripherals, including a
10 2.4 GHz multi-protocol radio. It also has built-in sensors and
11 Arduino-style expansion connectors.
13 The two RISC-V CPUs are named RI5CY and ZERO-RISCY, and are
15 `RI5CY`_ and `ZERO-RISCY`_. RI5CY is the "main" core; it has more
16 flash and RAM as well as a more powerful CPU design. ZERO-RISCY is a
17 "secondary" core. The main ZERO-RISCY use-case is as a wireless
30 RV32M1 multi-core SoC:
32 - 1 MiB flash and 192 KiB SRAM (RI5CY core)
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| /Zephyr-latest/boards/native/doc/ |
| D | arch_soc.rst | 22 Zephyr application, eliminating the need for architecture-specific
56 To build for the 32bit targets you must have the 32-bit C library installed in your system
57 (in Debian/Ubuntu this is provided by the ``gcc-multilib`` package).
67 for Linux (WSL1) because WSL1 does not support native 32-bit binaries.
72 <https://github.com/microsoft/WSL/issues/2468#issuecomment-374904520>`_ it
102 - There can **not** be busy wait loops in the application code that wait for
109 .. code-block:: c
117 .. code-block:: c
123 - Code that depends on its own execution speed will normally not
127 .. code-block:: c
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| /Zephyr-latest/doc/releases/ |
| D | release-notes-3.2.rst | 13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
56 This definition can be used by third-party code to compile code conditional
58 Therefore, any third-party code integrated using the Zephyr build system will
91 changed from ``-ENETDOWN`` to ``-ENETUNREACH``. A return value of ``-ENETDOWN`` now indicates
129 * Removed support for configuring the CAN-FD maximum DLC value via Kconfig
156 valid for specific bindings to specify like :dtcompatible:`gpio-leds` and
157 :dtcompatible:`fixed-partitions`.
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| D | release-notes-1.14.rst | 17 * CVE-2020-10066
18 * CVE-2020-10069
19 * CVE-2020-13601
20 * CVE-2020-13602
32 * :github:`issuenumber` - issue title
34 * :github:`18334` - DNS resolution is broken for some addresses in master/2.0-pre
35 * :github:`19917` - Bluetooth: Controller: Missing LL_ENC_RSP after HCI LTK Negative Reply
36 * :github:`21107` - LL_ASSERT and 'Imprecise data bus error' in LL Controller
37 * :github:`21257` - tests/net/net_pkt failed on mimxrt1050_evk board.
38 * :github:`21299` - bluetooth: Controller does not release buffer on central side after peripheral …
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