Searched full:gated (Results 1 – 25 of 43) sorted by relevance
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| /Zephyr-Core-3.6.0/dts/bindings/clock/ |
| D | st,stm32-rcc.yaml | 27 Specifying a gated clock:
29 To specify a gated clock, a peripheral should define a "clocks" property encoded
39 The gated clock is required when accessing to the peripheral controller is needed
54 Domain clock is independent from the bus/gated clock and allows access to the device's
55 register while the gated clock is off. As it doesn't feed the peripheral's controller, it
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| D | st,stm32wba-rcc.yaml | 28 Specifying a gated clock:
30 To specify a gated clock, a peripheral should define a "clocks" property encoded
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1160_evk/ |
| D | mimxrt1160_evk_cm4.dts | 52 * be gated.
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| D | mimxrt1160_evk_cm7.dts | 65 * be gated.
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1170_evk/ |
| D | mimxrt1170_evk_cm4.dts | 52 * be gated.
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| D | mimxrt1170_evk_cm7.dts | 117 * be gated.
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| /Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/ |
| D | Kconfig | 135 (wait for interrupt) during idle, the clock can be gated (however, this
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| /Zephyr-Core-3.6.0/soc/riscv/ite_ec/it8xxx2/ |
| D | soc.c | 273 * the EC processor would be clock gated. in arch_cpu_idle()
326 /* bit2: clocks to UART1 modules are not gated. */ in ite_it8xxx2_init()
344 /* bit2: clocks to UART2 modules are not gated. */ in ite_it8xxx2_init()
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| D | Kconfig.soc | 109 gated by individual drivers. When this option is disabled, CPU idle
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| /Zephyr-Core-3.6.0/include/zephyr/dt-bindings/pm/ |
| D | imx_spc.h | 13 * have their clocks gated at each set point.
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| /Zephyr-Core-3.6.0/drivers/pwm/ |
| D | pwm_mchp_xec_bbled.c | 278 if ((pulse_cycles == 0U) && (period_cycles == 0U)) { /* Controller off, clocks gated */ in pwm_bbled_xec_set_cycles()
337 /* 32K core clock is not gated by PCR in sleep, so BBLED can blink the LED even in pwm_bbled_xec_pm_action()
340 * This flag dont have effect on 48M clock. Since it is gated by PCR in sleep, BBLED in pwm_bbled_xec_pm_action()
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| /Zephyr-Core-3.6.0/soc/posix/inf_clock/ |
| D | soc.c | 21 * The Zephyr OS+APP code and the HW models are gated by a mutex +
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| /Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/cavs/ |
| D | sram.c | 63 /* HSPGCTL, HSRMCTL use reverse logic - 0 means EBB is power gated */ in hp_sram_pm_banks()
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| D | multiprocessing.c | 95 * the cores are NOT power gated even if they're configured to in soc_start_core()
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| /Zephyr-Core-3.6.0/drivers/dai/intel/ssp/ |
| D | dai-params-intel-ipc3.h | 20 #define DAI_INTEL_IPC3_SSP_FMT_GATED (0 << 4) /**< clock is gated */
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1024_evk/ |
| D | mimxrt1024_evk.dts | 167 * be gated.
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1010_evk/ |
| D | mimxrt1010_evk.dts | 170 * be gated.
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1015_evk/ |
| D | mimxrt1015_evk.dts | 167 * be gated.
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1040_evk/ |
| D | mimxrt1040_evk.dts | 171 * be gated.
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| /Zephyr-Core-3.6.0/drivers/serial/ |
| D | uart_ite_it8xxx2.c | 157 * When the system enters deep doze, all clocks are gated only the in uart_it8xxx2_init()
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| /Zephyr-Core-3.6.0/soc/xtensa/intel_adsp/ace/ |
| D | comm_widget.h | 655 * 0: Clk is un-gated
656 * 1: Clk is gated
667 * 1: Clk is gated
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1020_evk/ |
| D | mimxrt1020_evk.dts | 213 * be gated.
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| /Zephyr-Core-3.6.0/soc/arm/nxp_imx/rt/ |
| D | power_rt10xx.c | 248 /* Ensure clocks to ARM core memory will not be gated in low power mode in rt10xx_power_init()
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| /Zephyr-Core-3.6.0/boards/arm/mimxrt1050_evk/ |
| D | mimxrt1050_evk.dts | 299 * be gated.
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| /Zephyr-Core-3.6.0/subsys/sd/ |
| D | sd.c | 126 /* SD clock should start gated */ in sd_init_io()
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