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/Zephyr-latest/dts/bindings/pwm/
Dnxp,imx-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,imx-pwm"
8 include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml]
19 run-in-wait:
24 run-in-debug:
39 - "immediate"
40 - "half-cycle"
41 - "full-cycle"
42 - "half-and-full-cycle"
44 Select how to load the buffered-registers with new values:
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/Zephyr-latest/dts/bindings/memory-controllers/
Datmel,sam-smc.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The SMC allows to interface with static-memory mapped external devices such as
19 pinctrl-0 = <&smc_default>;
20 pinctrl-names = "default";
25 atmel,smc-write-mode = "nwe";
26 atmel,smc-read-mode = "nrd";
27 atmel,smc-setup-timing = <1 1 1 1>;
28 atmel,smc-pulse-timing = <6 6 6 6>;
29 atmel,smc-cycle-timing = <7 7>;
33 The above example configures a is66wv51216dbll-55 device. The device is a
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/Zephyr-latest/include/zephyr/drivers/timer/
Dsystem_timer.h5 * SPDX-License-Identifier: Apache-2.0
59 * ticks and real-world time must be correct.
122 * @brief Hardware cycle counter
124 * Timer drivers are generally responsible for the system cycle
127 * arch_k_cycle_get_32()) to implement the cycle counter, though the
128 * user-facing API is owned by the architecture, not the driver. The
132 * If the counter clock is large enough for this to wrap its full range
137 * @return The current cycle time. This should count up monotonically
138 * through the full 32 bit space, wrapping at 0xffffffff. Hardware
145 * @brief 64 bit hardware cycle counter
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/Zephyr-latest/dts/bindings/display/
Dultrachip,uc81xx-common.yaml4 # SPDX-License-Identifier: Apache-2.0
8 include: [mipi-dbi-spi-device.yaml, display-controller.yaml]
11 busy-gpios:
12 type: phandle-array
21 type: uint8-array
24 child-binding:
28 cycle. Refresh nodes are optional and are used to override
33 always supports partial updates, the driver uses the full refresh
37 in the full profile.
41 - 'full' - Normal / full refresh.
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Dsolomon,ssd16xx-common.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [mipi-dbi-spi-device.yaml, display-controller.yaml]
10 type: uint8-array
13 busy-gpios:
14 type: phandle-array
34 - 0
35 - 90
36 - 180
37 - 270
42 child-binding:
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/Zephyr-latest/drivers/espi/
DKconfig.it8xxx22 # SPDX-License-Identifier: Apache-2.0
128 KBC mouse output buffer is full.
132 # status bit to indicate which cycle triggered the interrupt and data registers
138 bool "EC accepts 0x81 I/O cycle from eSPI transaction"
141 With this option enabled, EC will accept 0x81 I/O cycle from the Host.
Despi_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
207 * Eg. the I/O cycle 800h~8ffh from host can be mapped to x800h~x8ffh.
242 #define H2RAM_WINDOW_SIZE(ram_size) ((find_msb_set((ram_size) / 16) - 1) & 0x7)
249 /* Enable H2RAM eSPI I/O cycle */
257 const struct espi_it8xxx2_config *const config = dev->config; in smfi_it8xxx2_init()
259 (struct smfi_it8xxx2_regs *)config->base_smfi; in smfi_it8xxx2_init()
263 /* Set the host to RAM cycle address offset */ in smfi_it8xxx2_init()
266 gctrl->GCTRL_H2ROFSR = in smfi_it8xxx2_init()
267 (gctrl->GCTRL_H2ROFSR & ~IT8XXX2_ESPI_H2RAM_OFFSET_MASK) | in smfi_it8xxx2_init()
274 smfi_reg->SMFI_HRAMW0BA = in smfi_it8xxx2_init()
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/Zephyr-latest/doc/services/storage/zms/
Dzms.rst5 Zephyr Memory Storage is a new key-value storage system that is designed to work with all types
6 of non-volatile storage technologies. It supports classical on-chip NOR flash as well as new
12 ZMS divides the memory space into sectors (minimum 2), and each sector is filled with key-value
13 pairs until it is full.
15 The key-value pair is divided into two parts:
17 - The key part is written in an ATE (Allocation Table Entry) called "ID-ATE" which is stored
19 - The value part is defined as "DATA" and is stored raw starting from the top of the sector
21 Additionally, for each sector we store at the last positions Header-ATEs which are ATEs that
24 When the current sector is full we verify first that the following sector is empty, we garbage
37 .. list-table::
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/Zephyr-latest/drivers/led/
Dled_mchp_xec.c4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Microchip Breathing-Blinking LED controller
60 * eight 4-bit fields numbered 0 to 7
107 temp--; in calc_blink_32k_prescaler()
118 /* return duty cycle scaled to [0, 255]
129 * BBLED blinking mode uses an 8-bit accumulator and an 8-bit duty cycle
130 * register. The duty cycle register is programmed once and the
131 * accumulator is used as an 8-bit up counter.
132 * The counter uses the 32768 Hz clock and is pre-scaled by the delay
134 * 8-bit duty cycle values: 0x00 = full off, 0xff = full on.
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/Zephyr-latest/samples/modules/tflite-micro/hello_world/src/
Dconstants.h8 * http://www.apache.org/licenses/LICENSE-2.0
29 * of this constant can be tuned so that one full cycle takes a desired amount
31 * inference, this value should be defined per-device.
/Zephyr-latest/drivers/led_strip/
Dtlc59731.c4 * SPDX-License-Identifier: Apache-2.0
13 * TLC59731 is a 3-Channel, 8-Bit, PWM LED Driver
14 * With Single-Wire Interface (EasySet)
20 * cycle time.
24 * A zero is represented by no additional pulses within a cycle.
26 * (half a cycle) after the first one. We need at least some delay to get to
28 * full 1us. After the pulse, we wait an additional T_CYCLE_1 to complete
29 * the cycle. This time can be slightly shorter because the second pulse
30 * already closes the cycle.
99 rgb_write_bit(led_dev, data & BIT((idx--))); in rgb_write_data()
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/Zephyr-latest/drivers/sensor/maxim/max17055/
Dmax17055.h4 * SPDX-License-Identifier: Apache-2.0
58 /* Full charge capacity in 5/Rsense uA */
64 /* Time to full in units of 5.625s */
66 /* Cycle count in 1/100ths (number of charge/discharge cycles) */
/Zephyr-latest/drivers/sensor/maxim/max17262/
Dmax17262.h4 * SPDX-License-Identifier: Apache-2.0
61 /* Full charge capacity in mAh */
67 /* Time to full in seconds */
69 /* Cycle count in 1/100ths (number of charge/discharge cycles) */
/Zephyr-latest/drivers/pwm/
Dpwm_mchp_xec_bbled.c4 * SPDX-License-Identifier: Apache-2.0
42 #define XEC_PWM_BBLED_DC_MIN 1u /* 0 full off */
43 #define XEC_PWM_BBLED_DC_MAX 254u /* 255 is full on */
45 /* BBLED PWM mode uses the duty cycle to set the PWM frequency:
51 * Puse_OFF_width = (1/Fpwm) * (256 - duty_cycle) seconds
52 * where duty_cycle is an 8-bit value 0 to 255.
53 * Prescale is derived from DELAY register LOW_DELAY 12-bit field
54 * Duty cycle is derived from LIMITS register MINIMUM 8-bit field
61 * BBLED PWM mode duty cycle specified by 8-bit MIN field of the LIMITS register
138 * LIMITS.MIN = duty cycle = [1, 254]
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/Zephyr-latest/drivers/timer/
Daltera_avalon_timer_hal.c4 * SPDX-License-Identifier: Apache-2.0
17 /* The old driver "now" API would return a full uptime value. The new
59 * delivered (and accumulated cycle count gets updated). The result in sys_clock_cycle_get_32()
65 * count down from some large initial 64-bit value. This in sys_clock_cycle_get_32()
/Zephyr-latest/samples/drivers/led/pwm/boards/
Dmec15xxevb_assy6853.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pwm/pwm.h>
10 * BBLED controller 0 uses GPIO156/LED0 connected to JP31-13
11 * BBLED controller 1 uses GPIO157/LED1 connected to JP31-15
12 * BBLED controller 2 uses GPIO153/LED2 connected to JP31-17
15 * and implements duty cycle for blink mode as an 8-bit value where 0 is off and
16 * 255 full on. BBLED PWM is 8-bit.
17 * BBLED-PWM driver get cycles API reports 32KHz/256 or 48M/256.
24 compatible = "pwm-leds";
41 microchip,output-func-invert;
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Dmec172xevb_assy6906.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pwm/pwm.h>
10 * BBLED controller 0 uses GPIO156/LED1 connected to JP71-11
11 * BBLED controller 1 uses GPIO157/LED2 connected to JP71-13
12 * BBLED controller 2 uses GPIO153/LED3 connected to JP71-5
13 * BBLED controller 3 uses GPIO035/PWM8 connected to JP67-19
17 * and implements duty cycle for blink mode as an 8-bit value where 0 is off and
18 * 255 full on. BBLED PWM is 8-bit.
19 * BBLED-PWM driver get cycles API reports 32KHz/256 or 48M/256.
26 compatible = "pwm-leds";
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/Zephyr-latest/drivers/sensor/sbs_gauge/
Dsbs_gauge.c4 * SPDX-License-Identifier: Apache-2.0
26 cfg = dev->config; in sbs_cmd_reg_read()
27 status = i2c_burst_read_dt(&cfg->i2c, reg_addr, i2c_data, in sbs_cmd_reg_read()
42 * @return -ENOTSUP for unsupported channels
51 data = dev->data; in sbs_gauge_channel_get()
52 val->val2 = 0; in sbs_gauge_channel_get()
56 val->val1 = data->voltage / 1000; in sbs_gauge_channel_get()
57 val->val2 = (data->voltage % 1000) * 1000; in sbs_gauge_channel_get()
61 val->val1 = data->avg_current / 1000; in sbs_gauge_channel_get()
62 val->val2 = (data->avg_current % 1000) * 1000; in sbs_gauge_channel_get()
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/Zephyr-latest/drivers/watchdog/
Dwdt_npm2100.c3 * SPDX-License-Identifier: Apache-2.0
36 const struct wdt_npm2100_config *config = dev->config; in wdt_npm2100_setup()
37 struct wdt_npm2100_data *data = dev->data; in wdt_npm2100_setup()
39 if (!data->timeout_valid) { in wdt_npm2100_setup()
40 return -EINVAL; in wdt_npm2100_setup()
43 return mfd_npm2100_start_timer(config->mfd); in wdt_npm2100_setup()
48 const struct wdt_npm2100_config *config = dev->config; in wdt_npm2100_disable()
49 struct wdt_npm2100_data *data = dev->data; in wdt_npm2100_disable()
52 ret = i2c_reg_write_byte_dt(&config->i2c, TIMER_TASKS_STOP, 1U); in wdt_npm2100_disable()
57 data->timeout_valid = false; in wdt_npm2100_disable()
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Dwdt_npm1300.c3 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/gpio/nordic-npm1300-gpio.h>
42 const struct wdt_npm1300_config *config = dev->config; in wdt_npm1300_setup()
43 struct wdt_npm1300_data *data = dev->data; in wdt_npm1300_setup()
45 if (!data->timeout_valid) { in wdt_npm1300_setup()
46 return -EINVAL; in wdt_npm1300_setup()
49 return mfd_npm1300_reg_write(config->mfd, TIME_BASE, TIME_OFFSET_START, 1U); in wdt_npm1300_setup()
54 const struct wdt_npm1300_config *config = dev->config; in wdt_npm1300_disable()
55 struct wdt_npm1300_data *data = dev->data; in wdt_npm1300_disable()
58 ret = mfd_npm1300_reg_write(config->mfd, TIME_BASE, TIME_OFFSET_STOP, 1U); in wdt_npm1300_disable()
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/Zephyr-latest/doc/kernel/services/timing/
Dclocks.rst22 The kernel presents a "cycle" count via the :c:func:`k_cycle_get_32`
24 represents the fastest cycle counter that the operating system is able
25 to present to the user (for example, a CPU cycle counter) and that the
46 ----------
59 :c:func:`k_cyc_to_us_floor64` will convert a measured cycle count
60 to an elapsed number of microseconds in a full 64 bits of precision.
61 See the reference documentation for the full enumeration of conversion
66 word, these conversions expand to a 2-4 operation sequence, requiring
67 full precision only where actually required and requested.
127 being 32 bits. Large uptime counts in non-tick units will experience
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/Zephyr-latest/doc/project/
Drelease_process.rst6 The Zephyr project releases on a time-based cycle, rather than a feature-driven
10 A time-based release process enables the Zephyr project to provide users with a
12 roughly 4-month release cycle allows the project to coordinate development of
19 - Release tagging procedure:
21 - linear mode on main branch,
22 - release branches for maintenance after release tagging.
23 - Each release period will consist of a development phase followed by a
29 - Development phase: all changes are considered and merged, subject to
31 - Stabilisation phase: the release manager creates a vN-rc1 tag and the tree
33 - CI sees the tag, builds and runs tests; Test teams analyse the report from the
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/Zephyr-latest/soc/sifive/sifive_freedom/fu700/
Dclock.c4 * SPDX-License-Identifier: Apache-2.0
20 /* HACK to get the '1 full controller clock cycle'. */ in wait_controller_cycle()
26 * - core: to 1GHz PLL (CORE_PLL) from 26MHz oscillator (HFCLK)
27 * - peri: to 250MHz PLL (HFPCLKPLL) from HFCLK
28 * - ddr: to 923MHz PLL (DDRPLL) from HFCLK (half of the data rate)
/Zephyr-latest/drivers/clock_control/
DKconfig.nrf4 # SPDX-License-Identifier: Apache-2.0
53 bool "External full swing"
218 unnecessary HIGH -> LOW -> HIGH cycle given some module will
/Zephyr-latest/include/zephyr/drivers/
Dcharger.h4 * SPDX-License-Identifier: Apache-2.0
107 * Reserved to demark downstream custom properties - use this value as the actual value may
147 /** The battery is full and the charging device will not attempt charging */
322 * @brief Callback API enabling or disabling a charge cycle.
355 const struct charger_driver_api *api = (const struct charger_driver_api *)dev->api; in z_impl_charger_get_prop()
357 return api->get_property(dev, prop, val); in z_impl_charger_get_prop()
376 const struct charger_driver_api *api = (const struct charger_driver_api *)dev->api; in z_impl_charger_set_prop()
378 return api->set_property(dev, prop, val); in z_impl_charger_set_prop()
382 * @brief Enable or disable a charge cycle
385 * @param enable true enables a charge cycle, false disables a charge cycle
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