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/hal_rpi_pico-latest/.github/workflows/
Dbazel_build.yml8 bazel-build-check:
12 os: [ubuntu-latest, macos-latest]
13 fail-fast: false
14 runs-on: ${{ matrix.os }}
16 - name: Checkout
19 fetch-depth: 0
20 - name: Get Bazel
21 uses: bazel-contrib/setup-bazel@0.9.0
24 bazelisk-cache: true
26 disk-cache: ${{ github.workflow }}
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/hal_rpi_pico-latest/src/rp2_common/pico_rand/
Drand.c4 * SPDX-License-Identifier: BSD-3-Clause
38 // they may have useful junk in them, either from power-up or a previous boot.
54 This is a fixed-increment version of Java 8's SplittableRandom generator
58 It is a very fast generator passing BigCrush, and it can be useful if
75 This is xoroshiro128** 1.0, one of our all-purpose, rock-solid,
76 small-state generators. It is extremely (sub-ns) fast and it passes all
80 For generating just floating-point numbers, xoroshiro128+ is even
84 a 64-bit seed, we suggest to seed a splitmix64 generator and use its
88 return (x << k) | (x >> (64 - k)); in rotl()
92 const uint64_t s0 = local_rng_state->r[0]; in xoroshiro128ss()
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/hal_rpi_pico-latest/src/rp2040/hardware_structs/include/hardware/structs/
Dclocks.h1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
6 * SPDX-License-Identifier: BSD-3-Clause
18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-regis…
23 // Bit-field descriptions are of the form:
102 // Clock control, can be changed on-the-fly (except for auxsrc)
112 // Clock divisor, can be changed on-the-fly
113 …// 0xffffff00 [31:8] INT (0x000001) Integer component of the divisor, 0 -> divide by 2^16
118 // Indicates which SRC is currently selected by the glitchless mux (one-hot)
171 …// 0x01000000 [24] FAST (0) Test clock faster than expected, only valid when status_don…
173 // 0x00010000 [16] FAIL (0) Test failed
/hal_rpi_pico-latest/src/rp2350/hardware_structs/include/hardware/structs/
Dclocks.h1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
6 * SPDX-License-Identifier: BSD-3-Clause
18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-regis…
23 // Bit-field descriptions are of the form:
118 // Clock control, can be changed on-the-fly (except for auxsrc)
129 // 0xffff0000 [31:16] INT (0x0001) Integer part of clock divisor, 0 -> max+1, can be...
130 …00ffff [15:0] FRAC (0x0000) Fractional component of the divisor, can be changed on-the-fly
134 // Indicates which src is currently selected (one-hot)
187 …// 0x01000000 [24] FAST (0) Test clock faster than expected, only valid when status_don…
189 // 0x00010000 [16] FAIL (0) Test failed
/hal_rpi_pico-latest/src/rp2040/hardware_regs/include/hardware/regs/
Di2c.h1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
6 * SPDX-License-Identifier: BSD-3-Clause
97 // Read/Write Access: - bit 10 is read only. - bit 11 is read only
98 // - bit 16 is read only - bit 17 is read only - bits 18 and 19
103 // -----------------------------------------------------------------------------
112 // -----------------------------------------------------------------------------
119 // 0x0 -> Overflow when RX_FIFO is full
120 // 0x1 -> Hold bus when RX_FIFO is full
128 // -----------------------------------------------------------------------------
134 // 0x0 -> Default behaviour of TX_EMPTY interrupt
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/hal_rpi_pico-latest/src/rp2350/hardware_regs/include/hardware/regs/
Di2c.h1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
6 * SPDX-License-Identifier: BSD-3-Clause
97 // Read/Write Access: - bit 10 is read only. - bit 11 is read only
98 // - bit 16 is read only - bit 17 is read only - bits 18 and 19
103 // -----------------------------------------------------------------------------
112 // -----------------------------------------------------------------------------
119 // 0x0 -> Overflow when RX_FIFO is full
120 // 0x1 -> Hold bus when RX_FIFO is full
128 // -----------------------------------------------------------------------------
134 // 0x0 -> Default behaviour of TX_EMPTY interrupt
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Dotp_data.h1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
6 * SPDX-License-Identifier: BSD-3-Clause
20 // The CHIPID0..3 rows contain a 64-bit random identifier for this
32 #define OTP_DATA_CHIPID0_RESET "-"
42 #define OTP_DATA_CHIPID1_RESET "-"
52 #define OTP_DATA_CHIPID2_RESET "-"
62 #define OTP_DATA_CHIPID3_RESET "-"
69 // Description : Bits 15:0 of private per-device random number (ECC)
71 // The RANDID0..7 rows form a 128-bit random number generated
82 #define OTP_DATA_RANDID0_RESET "-"
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/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/
DRP2040.h2 * Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause
43 /* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ============…
44 …Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm…
45 …NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped …
46 …HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault …
47 …SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction …
48 …PendSV_IRQn = -2, /*!< -2 Pendable request for system service …
49 …SysTick_IRQn = -1, /*!< -1 System Tick Timer …
85 /* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals …
96 #include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals …
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/hal_rpi_pico-latest/src/rp2040/hardware_regs/
DRP2040.svd1 <?xml version="1.0" encoding="utf-8"?>
2 <!--
5 SPDX-License-Identifier: BSD-3-Clause
6 -->
7 …sion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSI…
13 Dual-core Arm Cortex-M0+ processor, flexible clock running up to 133 MHz
14 264KB on-chip SRAM
18 Supported input power 1.8-5.5V DC
19 Operating temperature -20C to +85C
20 Drag-and-drop programming using mass storage over USB
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/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/
DRP2350.h2 * Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause
43 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ============…
44 …Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm…
45 …NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped …
46 …HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault …
47 …MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including…
49 …BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault…
51 …UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illeg…
52 …SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler …
53 …SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction …
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/hal_rpi_pico-latest/src/rp2350/hardware_regs/
DRP2350.svd1 <?xml version="1.0" encoding="utf-8"?>
2 <!--
5 SPDX-License-Identifier: BSD-3-Clause
6 -->
7 …sion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSI…
13 Dual Cortex-M33 or Hazard3 processors at 150MHz
14 520kB on-chip SRAM, in 10 independent banks
15 Extended low-power sleep states with optional SRAM retention: as low as 10uA DVDD
16 8kB of one-time-programmable storage (OTP)
18 Additional 16MB flash/PSRAM accessible via optional second chip-select
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