| /Zephyr-latest/include/zephyr/arch/ |
| D | exception.h | 1 /* exception.h - automatically selects the correct exception.h file to include */
12 #include <zephyr/arch/x86/intel64/exception.h>
14 #include <zephyr/arch/x86/ia32/exception.h>
16 #include <zephyr/arch/arm64/exception.h>
18 #include <zephyr/arch/arm/exception.h>
20 #include <zephyr/arch/arc/v2/exception.h>
22 #include <zephyr/arch/nios2/exception.h>
24 #include <zephyr/arch/riscv/exception.h>
26 #include <zephyr/arch/xtensa/exception.h>
28 #include <zephyr/arch/mips/exception.h>
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| /Zephyr-latest/scripts/west_commands/zspdx/ |
| D | licenses.py | 11 "389-exception",
48 "Autoconf-exception-2.0",
49 "Autoconf-exception-3.0",
75 "Bison-exception-2.2",
79 "Bootloader-exception",
83 "CAL-1.0-Combined-Work-Exception",
138 "CLISP-exception-2.0",
148 "Classpath-exception-2.0",
157 "DigiRule-FOSS-exception",
173 "FLTK-exception",
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| /Zephyr-latest/arch/arm/core/cortex_a_r/ |
| D | exc.S | 9 * @brief Exception handlers for ARM Cortex-A and Cortex-R
11 * This file implements the exception handlers (undefined instruction, prefetch
14 * All exception handlers save the exception stack frame into the exception
16 * exception behaviour (i.e. an arbitrary thread stack overflow cannot cause
17 * exception handling and thereby subsequent total system failure).
19 * In case the exception is due to a fatal (unrecoverable) fault, the fault
20 * handler is responsible for invoking the architecture fatal exception handler
21 * (z_arm_fatal_error) which invokes the kernel fatal exception handler
23 * depending on the application exception handler implementation.
50 * construct an exception stack frame.
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| D | exc_exit.S | 10 * @brief ARM Cortex-A and Cortex-R exception/interrupt exit API
39 * the privileged stack on exception entry. The return state
70 * saved so restore the float context from the exception stack frame.
193 * @brief Kernel housekeeping when exiting exception handler
195 * The exception exit routine performs appropriate housekeeping tasks depending
198 * If exiting a nested or non-fatal exception, the exit routine restores the
199 * saved exception stack frame to resume the excepted context.
201 * If exiting a non-nested fatal exception, the exit routine, assuming that the
202 * current faulting thread is aborted, discards the saved exception stack
211 /* Do not context switch if exiting a nested exception */
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| /Zephyr-latest/arch/arc/core/ |
| D | fault_s.S | 51 * The exception handling will use top part of interrupt stack to
52 * get smaller memory footprint, because exception is not frequent.
80 * re-use the top part of interrupt stack as exception
82 * and exception is raised, then here it's guaranteed that
83 * exception handling has necessary stack to use
91 * this stack frame is set up in exception stack,
93 * Because the exception may be raised by stack checking or
95 * is setup in original sp, double exception may be raised during
109 /* the exception cause must be fixed in exception handler when exception returns
110 * directly, or exception will be repeated.
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| /Zephyr-latest/arch/x86/core/ia32/ |
| D | gdbstub.c | 9 #include <ia32/exception.h>
22 unsigned int exception; in get_exception() local
26 exception = GDB_EXCEPTION_DIVIDE_ERROR; in get_exception()
29 exception = GDB_EXCEPTION_BREAKPOINT; in get_exception()
32 exception = GDB_EXCEPTION_BREAKPOINT; in get_exception()
35 exception = GDB_EXCEPTION_OVERFLOW; in get_exception()
38 exception = GDB_EXCEPTION_OVERFLOW; in get_exception()
41 exception = GDB_EXCEPTION_INVALID_INSTRUCTION; in get_exception()
44 exception = GDB_EXCEPTION_DIVIDE_ERROR; in get_exception()
47 exception = GDB_EXCEPTION_MEMORY_FAULT; in get_exception()
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| D | excstub.S | 9 * @brief Exception management support for IA-32 architecture
14 * and exiting a C exception handler.
32 * @brief Inform the kernel of an exception
34 * This function is called from the exception stub created by nanoCpuExcConnect()
35 * to inform the kernel of an exception. This routine currently does
36 * _not_ increment a thread/interrupt specific exception count. Also,
37 * execution of the exception handler occurs on the current stack, i.e.
40 * exception stub.
67 * exception exits.
82 * Exception Error code (or junk)
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| /Zephyr-latest/arch/arm/include/cortex_m/ |
| D | exception.h | 9 * @brief Exception/interrupt context helpers for Cortex-M CPUs
11 * Exception/interrupt context helpers.
26 #include <zephyr/arch/arm/exception.h>
42 /* Exception Return (EXC_RETURN) is provided in LR upon exception entry.
43 * It is used to perform an exception return and to detect possible state
44 * transition upon exception.
51 /* bit[0]: Exception Secure. The security domain the exception was taken to. */
82 * Non-secure stack is used to restore stack frame on exception return.
100 * before the current exception occurred.
104 * the current exception state (i.e. nested exception) or not.
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| /Zephyr-latest/include/zephyr/arch/arm/ |
| D | exception.h | 9 * @brief ARM AArch32 public exception handling
11 * ARM AArch32-specific kernel exception handling interface. Included by
19 #include <zephyr/arch/arm/cortex_m/exception.h>
21 #include <zephyr/arch/arm/cortex_a_r/exception.h>
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| /Zephyr-latest/scripts/pylib/pytest-twister-harness/src/twister_harness/ |
| D | exceptions.py | 6 class TwisterHarnessException(Exception):
7 """General Twister harness exception."""
11 """Twister harness timeout exception"""
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| /Zephyr-latest/include/zephyr/arch/x86/ia32/ |
| D | exception.h | 18 * @brief Exception Stack Frame
20 * A pointer to an "exception stack frame" (ESF) is passed as an argument
21 * to exception handlers registered via nanoCpuExcConnect(). As the system
23 * onto the stack when an exception occurs.
25 * The exception stack frame includes the volatile registers (EAX, ECX, and
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| /Zephyr-latest/tests/arch/x86/static_idt/src/ |
| D | main.c | 10 * Ensures interrupt and exception stubs are installed correctly.
75 * This is the handler for the divide by zero exception.
84 * error so that we know the exception connect code is working. Therefore,
85 * a very quick and dirty approach is taken for dealing with the exception;
106 * and exception stubs are installed at the correct place.
123 /* Check for the exception stub */ in ZTEST()
133 * exception and software interrupt are triggered so we don't check in ZTEST()
140 TC_PRINT("- Expect to see unhandled interrupt/exception message\n"); in idt_spur_task()
152 * @details this test is to generate the interrupt, exception,
171 TC_PRINT("Testing to see exception handler executes properly\n"); in ZTEST()
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| /Zephyr-latest/arch/arm64/core/ |
| D | fatal.c | 93 err = "Branch Target Exception"; in dump_esr()
111 err = "Instruction Abort from a lower Exception level, that " in dump_esr()
116 err = "Instruction Abort taken without a change in Exception " in dump_esr()
121 err = "PC alignment fault exception."; in dump_esr()
125 err = "Data Abort from a lower Exception level, that might " in dump_esr()
130 err = "Data Abort taken without a change in Exception level"; in dump_esr()
133 err = "SP alignment fault exception"; in dump_esr()
136 err = "Trapped floating-point exception taken from AArch32 " in dump_esr()
140 err = "Trapped floating-point exception taken from AArch64 " in dump_esr()
147 err = "Breakpoint exception from a lower Exception level, " in dump_esr()
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| D | fpu.c | 144 /* always deny FPU access whenever an exception is entered */ in z_arm64_fpu_enter_exc()
156 * FPU access is disabled and we're trapped while in exception context.
165 * Support only the "FP in exception" cases for now. in simulate_str_q_insn()
216 * We also get here when FP regs are used while in exception as FP access
222 * the triggering exception context.
249 * We were already in exception when the FPU access trap. in z_arm64_fpu_trap()
252 * interrupted exception's FPU context. in z_arm64_fpu_trap()
277 * exception level in case of exceptions, or during a thread context
278 * switch with the exception level of the new thread being 0.
289 /* We're about to execute non-exception code */ in fpu_access_update()
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| /Zephyr-latest/arch/x86/include/ia32/ |
| D | exception.h | 37 * and also the assembly language stubs for the exception. We use
40 * way it's easy for applications or drivers to install custom exception
60 * @brief Connect an exception handler that doesn't expect error code
62 * Assign an exception handler to a particular vector in the IDT.
72 * @brief Connect an exception handler that does expect error code
74 * Assign an exception handler to a particular vector in the IDT.
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| /Zephyr-latest/scripts/tests/twister/ |
| D | test_twister.py | 47 """ Test to validate the exception is raised for incorrect testsuite schema"""
50 with pytest.raises(Exception) as exception:
52 assert str(exception.value) == "Schema validation failed"
101 with pytest.raises(ConfigurationError) as exception:
104 assert len(exception.value.args) == 1
105 assert exception.value.args[0] == str(filename) + ": " + "Dummy message."
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| D | test_cmakecache.py | 43 not isinstance(expected_bool, bool) else nullcontext() as exception:
46 if exception is None:
49 assert str(exception.value) == f'invalid bool {cmake_bool}'
137 isinstance(expected, Exception) else nullcontext() as exception:
140 if exception is not None:
141 assert repr(exception.value) == repr(expected)
231 ids=['list', 'single value', 'empty', 'exception', 'get failure']
240 isinstance(expected, type) and issubclass(expected, Exception) else \
241 nullcontext() as exception:
245 if exception is None:
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| /Zephyr-latest/arch/nios2/core/ |
| D | exception.S | 25 /* Placed into special 'exception' section so that the linker can put this code
36 SECTION_FUNC(exception.entry, _exception)
62 /* ea-4 is the address of the instruction when the exception happened,
69 * exception. If an interrupt, switch stacks and enter IRQ handling
70 * code. If an exception, remain on current stack and enter exception
119 /* Determine whether the exception of the ISR requires context
141 * status register before the exception happened. When coming
173 /* If we get here, the exception wasn't in interrupt or an
195 /* Return address from the exception */
222 * exception state
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| /Zephyr-latest/arch/arm/include/cortex_a_r/ |
| D | exception.h | 9 * @brief Exception/interrupt context helpers for Cortex-A and Cortex-R CPUs
11 * Exception/interrupt context helpers.
49 * @param esf exception frame
50 * @param exc_return EXC_RETURN value present in LR after exception entry.
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| /Zephyr-latest/include/zephyr/arch/arc/v2/ |
| D | exception.h | 9 * @brief ARCv2 public exception handling
11 * ARC-specific kernel exception handling interface. Included by arc/arch.h.
25 /* ARCv2 Exception vector numbers */
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| /Zephyr-latest/arch/riscv/core/ |
| D | fpu.c | 186 /* always deny FPU access whenever an exception is entered */ in z_riscv_fpu_enter_exc()
196 * We also get here when FP regs are used while in exception as FP access
202 * the triggering exception context.
204 * Note that the exception depth count was not incremented before this call
218 * We were already in exception when the FPU access trapped. in z_riscv_fpu_trap()
221 * interrupted exception's FPU context. in z_riscv_fpu_trap()
249 * exception level in case of exceptions, or during a thread context
250 * switch with the exception level of the new thread being 0.
260 /* We're about to execute non-exception code */ in fpu_access_allowed()
270 * claim it back to avoid the likely exception trap in fpu_access_allowed()
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| /Zephyr-latest/arch/xtensa/core/ |
| D | README_MMU.txt | 79 one more special trick: it throws a TLB Miss exception (there are two,
83 The job of that exception handler is simply to ensure that the TLB has
87 the exception handler may result in an invalid/inapplicable mapping
90 exception from within the TLB miss exception handler (i.e. while the
91 EXCM bit is set). This will produce a Double Exception fault, which
93 prohibited exception.
95 After the TLB refill exception, the original faulting instruction is
98 memory access. (And may then result in yet another exception if it
123 done in an exception handler. And running an exception handler
125 means that the page(s) containing the exception handler must never
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| /Zephyr-latest/soc/common/riscv-privileged/ |
| D | soc_irq.S | 25 * Exception number is given as parameter via register a0.
27 SECTION_FUNC(exception.other, __soc_handle_irq)
28 /* Clear exception number from CSR mip register */
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| /Zephyr-latest/soc/openisa/rv32m1/ |
| D | vector_table.ld | 10 * for MCUboot support, so .reset.* and .exception.*
28 KEEP(*(".exception.entry.*")) /* contains _isr_wrapper */
29 *(".exception.other.*")
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| /Zephyr-latest/include/zephyr/ |
| D | fatal.h | 15 #include <zephyr/arch/exception.h>
35 * @param reason Fatal exception reason code
62 * another exception.
65 * @param esf Exception context, with details and partial or full register
81 * @param esf Exception context, with details and partial or full register
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