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/Zephyr-latest/drivers/sensor/microchip/mchp_tach_xec/
DKconfig18 prompt "Number of tach edges"
21 This value represents the number of Tach edges that
26 bool "Configure 9 tach edges or 4 tach periods"
29 bool "Configure 5 tach edges or 2 tach periods"
32 bool "Configure 3 tach edges or 1 tach period"
35 bool "Configure 2 tach edges or 1/2 tach period"
/Zephyr-latest/samples/subsys/usb/uac2_explicit_feedback/
DKconfig7 bool "Measure I2S LRCLK edges directly"
DREADME.rst39 The nRF5340 is capable of counting both edges of I2S LRCLK relative to USB SOF
/Zephyr-latest/dts/bindings/misc/
Drenesas,ra-external-interrupt.yaml26 - "both-edges"
/Zephyr-latest/dts/bindings/gpio/
Dadafruit-feather-header.yaml8 opposite edges of the board.
Dseeed-xiao-header.yaml10 edges of the board.
Dsparkfun-pro-micro-header.yaml8 edges of the board.
Darduino-nano-header-r3.yaml7 The Arduino Nano layout provides two headers on opposite edges of the board.
Dmikro-bus.yaml8 edges of the board.
Darduino-header-r3.yaml9 opposite edges of the board.
Darduino-mkr-header.yaml7 The Arduino MKR layout provides two headers on both edges of the board.
/Zephyr-latest/dts/bindings/sensor/
Despressif,esp32-pcnt.yaml9 rising and/or falling edges of an input signal.
19 Each channel has two inputs: a signal input that accepts signal edges
Dnxp,s32-qdec.yaml89 We use this delay to generate short pulses at the rising and falling edges of input pulse.
/Zephyr-latest/tests/drivers/gpio/gpio_basic_api/src/
Dtest_config_trigger.c42 /* 2. Enable PIN callback as both edges */ in ZTEST()
93 /* 2. Enable PIN callback as both edges */ in ZTEST()
/Zephyr-latest/doc/hardware/peripherals/
Dcomparator.rst32 compare its inputs, producing an output and detecting edges. When suspended, the comparator
/Zephyr-latest/dts/bindings/counter/
Dnxp,lptmr.yaml59 2 ^ [prescaler-glitch-filter] rising edges detected
/Zephyr-latest/drivers/adc/
Dadc_ads7052.c197 * edges provided on SCLK. When all 14 output bits are shifted out, the device outputs 0's on the
198 * subsequent SCLK rising edges. The device enters the ACQ state after 18 clocks and a minimum time
200 * 18 SCLK falling edges in the present serial transfer frame, the device provides an invalid
/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_tach.h37 /* Select TACH edges for counter increment */
/Zephyr-latest/include/zephyr/drivers/sensor/
Dmcux_lpcmp.h89 * 1x1b: COUT both edges event close an active window
/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dnxp_pint.h36 /* Generate Pin Interrupt on both edges */
Dsam0_eic.h24 /* Both edges */
/Zephyr-latest/dts/bindings/qspi/
Dnxp,s32-qspi.yaml33 - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
34 - Double Data Rate (DDR): sampling of incoming data occurs on both edges.
/Zephyr-latest/include/zephyr/drivers/
Dcomparator.h34 /** Trigger on both edges of comparator output */
/Zephyr-latest/dts/bindings/pinctrl/
Dti,cc13xx-cc26xx-pinctrl.yaml136 IOC_BOTH_EDGES: Edge detection on both edges
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dcc13xx_cc26xx-pinctrl.h64 #define IOC_BOTH_EDGES 0x00030000 /* Edge detection on both edges */

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