| /hal_espressif-latest/components/hal/include/hal/ |
| D | ecc_hal.h | 32 * @brief Set the ECC curve of operation
56 * @param px X coordinate of the ECC point
57 * @param py Y coordinate of the ECC point
58 * @param len Length (in bytes) of the ECC point
68 * @param px X coordinate of the ECC point
69 * @param py Y coordinate of the ECC point
70 * @param len Length (in bytes) of the ECC point
81 * @param len Length (in bytes) of the ECC point
113 * @param qx X coordinate of the ECC point in jacobian form
114 * @param qy Y coordinate of the ECC point in jacobian form
[all …]
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| /hal_espressif-latest/components/soc/esp32c2/include/soc/ |
| D | ecc_mult_reg.h | 92 /*description: ECC mult version control register.*/
100 /*description: ECC Mem Parameter k.*/
108 /*description: ECC Mem Parameter k.*/
116 /*description: ECC Mem Parameter k.*/
124 /*description: ECC Mem Parameter k.*/
132 /*description: ECC Mem Parameter k.*/
140 /*description: ECC Mem Parameter k.*/
148 /*description: ECC Mem Parameter k.*/
156 /*description: ECC Mem Parameter k.*/
164 /*description: ECC Mem Parameter Px.*/
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| /hal_espressif-latest/components/soc/esp32c6/include/soc/ |
| D | ecc_mult_struct.h | 17 * ECC interrupt raw register, valid in level.
31 * ECC interrupt status register.
45 * ECC interrupt enable register.
59 * ECC interrupt clear register.
75 * ECC configure register
80 * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
85 * Write 1 to reset ECC Accelerator.
89 * The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256.
101 * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Division mode. 2:
107 * The verification result bit of ECC Accelerator, only valid when calculation is done.
[all …]
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| D | ecc_mult_reg.h | 15 * ECC interrupt raw register, valid in level.
27 * ECC interrupt status register.
39 * ECC interrupt enable register.
51 * ECC interrupt clear register.
63 * ECC configure register
67 * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
75 * Write 1 to reset ECC Accelerator.
82 * The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256.
103 * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Division mode. 2:
112 * The verification result bit of ECC Accelerator, only valid when calculation is done.
[all …]
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| D | spi_mem_struct.h | 78 … is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error…
93 …I_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed …
95 …en : 1; /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes m…
97 …r will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/
386 …ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is c…
422 … : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, whe…
423 … : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when…
446 … : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, whe…
447 … : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when…
475 …g_fmem_pms0_ecc : 1; /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: …
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| D | spi_mem_reg.h | 363 /*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
364 when there is a ECC error in AXI read data. The ECC error information is record
424 whether there is an ECC region or not..*/
430 /*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
444 /*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
1582 times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM
1584 his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq
1587 of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E
1757 /*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
1764 /*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
[all …]
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| /hal_espressif-latest/components/soc/esp32h2/include/soc/ |
| D | ecc_mult_struct.h | 19 * ECC interrupt raw register, valid in level.
33 * ECC interrupt status register.
47 * ECC interrupt enable register.
61 * ECC interrupt clear register.
77 * ECC configure register
82 * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
87 * Write 1 to reset ECC Accelerator.
91 * The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256.
100 * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
112 * The verification result bit of ECC Accelerator, only valid when calculation is done.
[all …]
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| D | ecc_mult_reg.h | 15 * ECC interrupt raw register, valid in level.
27 * ECC interrupt status register.
39 * ECC interrupt enable register.
51 * ECC interrupt clear register.
63 * ECC configure register
67 * Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after
75 * Write 1 to reset ECC Accelerator.
82 * The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256.
97 * The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point
114 * The verification result bit of ECC Accelerator, only valid when calculation is done.
[all …]
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| D | spi_mem_struct.h | 79 … is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error…
94 …I_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed …
96 …en : 1; /*Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes m…
98 …r will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.*/
387 …ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is c…
423 … : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, whe…
424 … : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when…
447 … : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, whe…
448 … : 1; /*Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when…
476 …g_fmem_pms0_ecc : 1; /*SPI1 flash ACE section $n ECC mode, 1: enable ECC mode. 0: …
[all …]
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| D | spi_mem_reg.h | 358 /*description: 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY
359 when there is a ECC error in AXI read data. The ECC error information is record
419 whether there is an ECC region or not..*/
425 /*description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode whe
439 /*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC
1577 times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM
1579 his bit is triggered when the error times of SPI0/1 ECC read external RAM are eq
1582 of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_E
1752 /*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when
1759 /*description: Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when
[all …]
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| /hal_espressif-latest/components/bt/porting/ext/tinycrypt/documentation/ |
| D | tinycrypt.rst | 73 * ECC-DH:
77 * Requires: ECC auxiliary functions (ecc.h/c).
79 * ECC-DSA:
83 * Requires: ECC auxiliary functions (ecc.h/c).
236 * ECC-DH and ECC-DSA:
238 * TinyCrypt ECC implementation is based on micro-ecc (see
239 https://github.com/kmackay/micro-ecc). In the original micro-ecc
349 * `RFC 6090 (ECC-DH and ECC-DSA)`_
351 .. _RFC 6090 (ECC-DH and ECC-DSA):
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| /hal_espressif-latest/components/mbedtls/esp_crt_bundle/ |
| D | cmn_crt_authorities.csv | 15 DigiCert,DigiCert TLS ECC P384 Root G5
19 GlobalSign nv-sa,GlobalSign ECC Root CA - R5
28 Google Trust Services LLC,GlobalSign ECC Root CA - R4
39 Sectigo,COMODO ECC Certification Authority
41 Sectigo,USERTrust ECC Certification Authority
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| /hal_espressif-latest/components/mbedtls/port/include/ |
| D | ecc_impl.h | 31 * @brief Perform ECC point multiplication (R = K * (Px, Py))
33 * @param point ECC point (multiplicand)
47 * @brief Perform ECC point verification,
50 * @param point ECC point that needs to be verified
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| /hal_espressif-latest/components/hal/ |
| D | .build-test-rules.yml | 3 components/hal/test_apps/ecc:
9 …reason: C2 ECC peripheral has a bug in ECC point verification, if value of K is zero the verificat…
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| /hal_espressif-latest/components/esp_hw_support/include/soc/esp32h2/ |
| D | esp_crypto_lock.h | 68 * @brief Acquire lock for the ECC cryptography peripheral.
74 * @brief Release lock for the ECC cryptography peripheral.
83 * Internally also locks the ECC and MPI peripheral, as the ECDSA depends on these peripherals
90 * Internally also releases the ECC and MPI peripheral, as the ECDSA depends on these peripherals
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| /hal_espressif-latest/components/esp_hw_support/port/esp32h2/ |
| D | esp_crypto_lock.c | 15 ECC: independent
18 ECDSA: needs ECC and MPI
33 /* Lock for ECC peripheral */
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| /hal_espressif-latest/components/bootloader/subproject/components/micro-ecc/ |
| D | CMakeLists.txt | 1 # only compile the "uECC_verify_antifault.c" file which includes the "micro-ecc/uECC.c" source file
3 INCLUDE_DIRS . micro-ecc)
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| /hal_espressif-latest/components/esp_hw_support/include/soc/esp32c2/ |
| D | esp_crypto_lock.h | 14 * @brief Acquire lock for the ECC cryptography peripheral.
20 * @brief Release lock for the ECC cryptography peripheral.
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| /hal_espressif-latest/components/esp_hw_support/port/esp32c2/ |
| D | esp_crypto_lock.c | 12 ECC: independent
15 /* Lock for ECC peripheral */
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| /hal_espressif-latest/components/soc/esp32s3/include/soc/ |
| D | spi_mem_struct.h | 87 … inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits ar…
88 …PI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed …
90 …o18_byte_en : 1; /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes m…
428 …uint32_t ecc_err_int_num : 8; /*Set the error times of MSPI ECC read to generate…
429 …_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses …
438 …uint32_t ecc_data_err_bit : 7; /*It records the first ECC data error bit number w…
439 … : 3; /*When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC byte.*/
440 …uint32_t ecc_byte_err : 1; /*It records the first ECC byte error when SPI_FME…
441 … : 8; /*This bits show the error times of MSPI ECC read, including ECC byte erro…
452 … inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits ar…
[all …]
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| /hal_espressif-latest/tools/esptool_py/test/ |
| D | test_modules.py | 31 … ] # Pregenerated pairs consisting of 32 bytes of data + 12 bytes of RS ECC (FPGA verified)
34 rs = reedsolo.RSCodec(12) # 12 ECC symbols
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| /hal_espressif-latest/components/esp_hw_support/port/esp32c6/ |
| D | esp_crypto_lock.c | 15 ECC: independent
32 /* Lock for ECC peripheral */
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| /hal_espressif-latest/components/wpa_supplicant/src/common/ |
| D | dragonfly.c | 21 * purposes: FFC groups whose prime is >= 3072 bits and ECC groups in dragonfly_suitable_group()
23 * ECC groups defined over a characteristic 2 finite field and ECC in dragonfly_suitable_group()
48 /* Default to 40 (this covers most ECC groups) */ in dragonfly_min_pwe_loop_iter()
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| /hal_espressif-latest/components/esp_hw_support/include/soc/esp32c6/ |
| D | esp_crypto_lock.h | 67 * @brief Acquire lock for the ECC cryptography peripheral.
73 * @brief Release lock for the ECC cryptography peripheral.
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| /hal_espressif-latest/components/esp_psram/esp32s3/ |
| D | esp_psram_impl_octal.c | 277 * Can add an input parameter for selecting ECC mode if needed
282 //Clear this bit to use ECC 16to17 mode in s_configure_psram_ecc()
287 * Enable ECC region 0 (ACE0) in s_configure_psram_ecc()
292 ESP_EARLY_LOGI(TAG, "ECC is enabled"); in s_configure_psram_ecc()
398 * If ECC is enabled, available PSRAM size will be 15/16 times its physical size.
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