Searched full:dtcm (Results 1 – 22 of 22) sorted by relevance
36 * 0x2000_0000 .. 0x20ff_ffff NS DTCM37 * 0x3000_0000 .. 0x30ff_ffff S DTCM45 /* Non-secure CPU DTCM */47 /* Secure CPU DTCM */
28 * DTCM | BOOT_SHARED | BL1_1_DATA | BL1_2_DATA |47 * DTCM | BOOT_SHARED | |63 * DTCM | BOOT_SHARED | |77 * DTCM | BOOT_SHARED | |214 /* BL1 data is in DTCM */228 /* BL2 data is after the code. TODO FIXME this should be in DTCM once the CC3XX235 /* Store boot data at the start of the DTCM. */
178 #define DTGU_CTRL_BASE 0xE001E600 /* TGU control register for DTCM */179 #define DTGU_CFG_BASE 0xE001E604 /* TGU configuration register for DTCM */180 #define DTGU_LUTn_BASE 0xE001E610 /* TGU Look Up Table register for DTCM */190 #define DTCM_BLK_NUM (0x2) /* Number of DTCM blocks */
376 | DTCM | | | DTCM | NS | RNR 2 | | NS | in sau_and_idau_cfg()403 | DTCM | | | DTCM | | | | in sau_and_idau_cfg()466 /* Configure DTCM */ in sau_and_idau_cfg()528 ERROR_MSG("Failed to Initialize TGU for DTCM!"); in mpc_init_cfg()535 ERROR_MSG("Failed to Configure TGU for DTCM!"); in mpc_init_cfg()
368 | DTCM | | | DTCM | NS | RNR 2 | | NS | in sau_and_idau_cfg()395 | DTCM | | | DTCM | | | | in sau_and_idau_cfg()458 /* Configure DTCM */ in sau_and_idau_cfg()520 ERROR_MSG("Failed to Initialize TGU for DTCM!"); in mpc_init_cfg()527 ERROR_MSG("Failed to Configure TGU for DTCM!"); in mpc_init_cfg()
354 | DTCM | | | DTCM | NS | RNR 2 | | NS | in sau_and_idau_cfg()380 | DTCM | | | DTCM | | | | in sau_and_idau_cfg()445 /* Configure DTCM */ in sau_and_idau_cfg()507 ERROR_MSG("Failed to Initialize TGU for DTCM!"); in mpc_init_cfg()514 ERROR_MSG("Failed to Configure TGU for DTCM!"); in mpc_init_cfg()
190 #define DTGU_CTRL_BASE 0xE001E600 /* TGU control register for DTCM */191 #define DTGU_CFG_BASE 0xE001E604 /* TGU configuration register for DTCM */192 #define DTGU_LUTn_BASE 0xE001E610 /* TGU Look Up Table register for DTCM */202 #define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */
78 * 0x2000_0000 .. 0x20ff_ffff NS DTCM79 * 0x3000_0000 .. 0x30ff_ffff S DTCM87 /* Non-secure CPU DTCM */89 /* Secure CPU DTCM */
77 /* Mark DTCM as privileged, read-write, execute-never */ \
356 | DTCM | | | DTCM | NS | RNR 2 | | NS | in sau_and_idau_cfg()385 | DTCM | | | DTCM | | | | in sau_and_idau_cfg()450 /* Configure DTCM */ in sau_and_idau_cfg()512 ERROR_MSG("Failed to Initialize TGU for DTCM!"); in mpc_init_cfg()519 ERROR_MSG("Failed to Configure TGU for DTCM!"); in mpc_init_cfg()
200 #define DTGU_CTRL_BASE 0xE001E600 /* TGU control register for DTCM */201 #define DTGU_CFG_BASE 0xE001E604 /* TGU configuration register for DTCM */202 #define DTGU_LUTn_BASE 0xE001E610 /* TGU Look Up Table register for DTCM */212 #define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */
226 #define DTGU_CTRL_BASE 0xE001E600 /* TGU control register for DTCM */227 #define DTGU_CFG_BASE 0xE001E604 /* TGU configuration register for DTCM */228 #define DTGU_LUTn_BASE 0xE001E610 /* TGU Look Up Table register for DTCM */238 #define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */
220 #define DTGU_CTRL_BASE 0xE001E600 /* TGU control register for DTCM */221 #define DTGU_CFG_BASE 0xE001E604 /* TGU configuration register for DTCM */222 #define DTGU_LUTn_BASE 0xE001E610 /* TGU Look Up Table register for DTCM */232 #define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */
216 #define DTGU_CTRL_BASE 0xE001E600 /* TGU control register for DTCM */217 #define DTGU_CFG_BASE 0xE001E604 /* TGU configuration register for DTCM */218 #define DTGU_LUTn_BASE 0xE001E610 /* TGU Look Up Table register for DTCM */228 #define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */
8 # This command writes a random doubleword to the entirety of the DTCM.
27 dtcm:
121 * memory such as the DTCM allowing the total image to be larger than the
121 #define __DTCM_PRESENT 0U /* Set to 1 if DTCM is present */
916 …_Pos 1U /*!< SCB ABFSR: DTCM Position*/917 …TCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
1448 __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */1494 /** \brief MemSysCtl DTCM Control Register Definitions */4351 …e ARMCM52_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */4353 …RR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */
1397 __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */1456 /** \brief MemSysCtl DTCM Control Register Definitions */4299 …e ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */4301 …M55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */
1397 __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */1450 /** \brief MemSysCtl DTCM Control Register Definitions */4323 … 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */4325 …RR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */
