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/Zephyr-latest/tests/drivers/uart/uart_async_api/boards/
Dnucleo_f103rb.overlay5 dmas = <&dma1 4 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>,
6 <&dma1 5 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
10 &dma1 {
Dstm32f3_disco.overlay4 dmas = <&dma1 7 STM32_DMA_PERIPH_TX>,
5 <&dma1 6 STM32_DMA_PERIPH_RX>;
Dxmc45_relax_kit.overlay13 dmas = <&dma1 1 0 XMC4XXX_SET_CONFIG(10,6)>, <&dma1 2 0 XMC4XXX_SET_CONFIG(11,6)>;
32 &dma1 {
Dnucleo_l152re.overlay7 dmas = <&dma1 2 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>,
8 <&dma1 3 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
/Zephyr-latest/tests/drivers/spi/spi_loopback/boards/
Dnucleo_l476rg.overlay8 dmas = <&dma1 3 1 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)
9 &dma1 2 1 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
23 &dma1 {
Dnucleo_l152re.overlay11 dmas = <&dma1 3 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)
12 &dma1 2 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
27 &dma1 {
Dgd32f407v_start.overlay9 &dma1 {
29 dmas = <&dma1 0 3 0 0>, <&dma1 5 3 0 0>;
Dgd32f450i_eval.overlay9 &dma1 {
29 dmas = <&dma1 0 3 0 0>, <&dma1 5 3 0 0>;
Dgd32f450v_start.overlay9 &dma1 {
29 dmas = <&dma1 0 3 0 0>, <&dma1 5 3 0 0>;
Dgd32f450z_eval.overlay9 &dma1 {
29 dmas = <&dma1 0 3 0 0>, <&dma1 5 3 0 0>;
Dgd32f470i_eval.overlay9 &dma1 {
29 dmas = <&dma1 0 3 0 0>, <&dma1 5 3 0 0>;
/Zephyr-latest/samples/drivers/led/led_strip/boards/
Dnucleo_f070rb.overlay12 dmas = <&dma1 3 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>,
13 <&dma1 2 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
37 &dma1 {
/Zephyr-latest/samples/drivers/spi_flash/boards/
Dstm32l562e_dk.overlay8 dmas = <&dma1 0 41 0x480>; /* request 41 for OCTOSPI1 */
12 &dma1 {
/Zephyr-latest/dts/arm/st/f4/
Dstm32f401.dtsi58 dmas = <&dma1 4 0 0x400 0x3
59 &dma1 3 0 0x400 0x3>;
71 dmas = <&dma1 5 0 0x400 0x3
72 &dma1 0 0 0x400 0x3>;
/Zephyr-latest/tests/drivers/adc/adc_api/boards/
Dnucleo_l476rg.overlay15 dmas = <&dma1 1 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>;
30 &dma1 {
Ddisco_l475_iot1.overlay15 dmas = <&dma1 1 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>;
38 &dma1 {
Dnucleo_f103rb_dma.overlay15 dmas = <&dma1 1 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>;
39 &dma1 {
Dstm32f3_disco.overlay15 dmas = <&dma1 1 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>;
39 &dma1 {
Dnucleo_f091rc.overlay15 dmas = <&dma1 1 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>;
39 &dma1 {
Dnucleo_l073rz.overlay15 dmas = <&dma1 1 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>;
39 &dma1 {
Dnucleo_l152re.overlay15 dmas = <&dma1 1 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>;
39 &dma1 {
/Zephyr-latest/dts/bindings/dma/
Dst,stm32-dma-v2bis.yaml53 dma1: dma-controller@40020400 {
60 For the client part, example for stm32f103 on DMA1 instance
65 dmas = <&dma1 3 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)>,
66 <&dma1 2 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
/Zephyr-latest/include/zephyr/devicetree/
Ddma.h31 * dma1: dma@... { ... };
36 * dmas = <&dma1 1 2 0x400 0x3>,
42 * DT_DMAS_CTLR_BY_IDX(DT_NODELABEL(n), 0) // DT_NODELABEL(dma1)
59 * dma1: dma@... { ... };
64 * dmas = <&dma1 1 2 0x400 0x3>,
71 * DT_DMAS_CTLR_BY_NAME(DT_NODELABEL(n), tx) // DT_NODELABEL(dma1)
131 * dma1: dma@... {
142 * dmas = <&dma1 1 0x400>,
184 * dma1: dma@... {
195 * dmas = <&dma1 1 0x400>,
/Zephyr-latest/dts/bindings/spi/
Dinfineon,xmc4xxx-spi.yaml46 dmas = <&dma1 1 0 XMC4XXX_SET_CONFIG(10,6)>, <&dma1 2 0 XMC4XXX_SET_CONFIG(11,6)>;
55 dma1 can connect to lines [8, 11].
/Zephyr-latest/boards/shields/weact_ov2640_cam_module/boards/
Dmini_stm32h743.overlay48 dmas = <&dma1 0 75 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC |
53 &dma1 {

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