Home
last modified time | relevance | path

Searched +full:divider +full:- +full:int +full:- +full:4 (Results 1 – 25 of 137) sorted by relevance

123456

/Zephyr-latest/dts/bindings/pwm/
Draspberrypi,pico-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "raspberrypi,pico-pwm"
8 include: [pwm-controller.yaml, pinctrl-device.yaml, reset-device.yaml, base.yaml]
17 divider-int-0:
18 type: int
20 The integral part of the divider for pwm slice 0.
22 as the integer part of the divider.
26 divider-frac-0:
27 type: int
29 The fractional part of the divider for pwm slice 0.
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_r8a779f0_cpg_mssr.c7 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
17 #include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
82 static int r8a779f0_cpg_enable_disable_core(const struct device *dev, in r8a779f0_cpg_enable_disable_core()
85 int ret = 0; in r8a779f0_cpg_enable_disable_core()
88 switch (clk_info->module) { in r8a779f0_cpg_enable_disable_core()
90 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
100 ret = -ENOTSUP; in r8a779f0_cpg_enable_disable_core()
105 rcar_cpg_write(DEVICE_MMIO_GET(dev), clk_info->offset, reg); in r8a779f0_cpg_enable_disable_core()
[all …]
Dclock_control_r8a7795_cpg_mssr.c6 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
15 #include <zephyr/dt-bindings/clock/r8a7795_cpg_mssr.h>
74 static int r8a7795_cpg_enable_disable_core(const struct device *dev, in r8a7795_cpg_enable_disable_core()
77 int ret = 0; in r8a7795_cpg_enable_disable_core()
82 switch (clk_info->module) { in r8a7795_cpg_enable_disable_core()
87 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
100 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
105 ret = -ENOTSUP; in r8a7795_cpg_enable_disable_core()
[all …]
Dclock_control_lpc11u6x.h4 * SPDX-License-Identifier: Apache-2.0
45 #define LPC11U6X_PRESET_CTRL_FRG (1 << 4)
79 volatile uint32_t sys_ahb_clk_div; /* System clock divider */
82 volatile const uint32_t reserved6[4];
83 volatile uint32_t ssp0_clk_div; /* SSP0 clock divider */
84 volatile uint32_t usart0_clk_div; /* USART0 clock divider */
85 volatile uint32_t ssp1_clk_div; /* SSP1 clock divider */
86 volatile uint32_t frg_clk_div; /* USART 1-4 fractional baud
87 * rate generator clock divider
92 volatile uint32_t usb_clk_div; /* USB clock divider */
[all …]
/Zephyr-latest/dts/bindings/clock/
Dnordic,nrf-auxpll.yaml2 # SPDX-License-Identifier: Apache-2.0
9 f_out = ((R + A * 2^(-16)) * f_src) / B
13 - A: nordic,frequency
14 - B: nordic,outdiv
15 - R: nordic,range (3=low, 4=mid, 5=high, 6=statichigh)
16 - f_src: Source frequency, given by clocks
18 compatible: "nordic,nrf-auxpll"
21 - base.yaml
22 - clock-controller.yaml
23 - nordic-nrf-ficr-client.yaml
[all …]
Dnxp,kinetis-mcg.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-mcg"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
18 type: int
19 enum: [0, 1, 2, 3, 4, 5, 6, 7]
21 Internal Reference Clock Divider.
25 type: int
26 enum: [0, 1, 2, 3, 4, 5, 6, 7]
28 Second Low-frequency Internal Reference Clock Divider.
[all …]
/Zephyr-latest/samples/basic/blinky_pwm/boards/
Drpi_pico.overlay7 divider-frac-4 = <15>;
8 divider-int-4 = <255>;
Dxiao_rp2040.overlay11 divider-frac-4 = <15>;
12 divider-int-4 = <255>;
/Zephyr-latest/dts/bindings/timer/
Dambiq,stimer.yaml2 # SPDX-License-Identifier: Apache-2.0
17 clk-source:
18 type: int
21 clk-source specifies the clock source that used by the system timer.
23 0 - NOCLK : No clock enabled.
24 1 - HFRC_DIV16 : 3MHz from the HFRC clock divider.
25 2 - HFRC_DIV256 : 187.5KHz from the HFRC clock divider.
26 3 - XTAL_DIV1 : 32768Hz from the crystal oscillator.
27 4 - XTAL_DIV2 : 16384Hz from the crystal oscillator.
28 5 - XTAL_DIV32 : 1024Hz from the crystal oscillator.
[all …]
Dnuclei,systimer.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The Nuclei system timer provides RISC-V privileged mtime and mtimecmp
21 clk-divider:
22 type: int
24 clk-divider specifies the division ratio to the CPU frequency that
31 uses 27MHz, which is the CPU clock divided by 4.
35 clock-frequency = <108000000>;
44 Setting clk-divider to 2 specifies the system timer uses the clock
45 that CPU clock frequency divided by (2^2=)4, or 27MHz.
48 dt-bindings/timer/nuclei-systimer.h header file.
/Zephyr-latest/drivers/mdio/
Dmdio_xmc4xxx.c4 * SPDX-License-Identifier: Apache-2.0
30 uint8_t divider; member
35 {.divider = 8, .reg_val = 2}, {.divider = 13, .reg_val = 3},
36 {.divider = 21, .reg_val = 0}, {.divider = 31, .reg_val = 1},
37 {.divider = 51, .reg_val = 4}, {.divider = 62, .reg_val = 5},
51 static int mdio_xmc4xxx_transfer(const struct device *dev, uint8_t phy_addr, uint8_t reg_addr, in mdio_xmc4xxx_transfer()
54 const struct mdio_xmc4xxx_dev_config *const dev_cfg = dev->config; in mdio_xmc4xxx_transfer()
55 ETH_GLOBAL_TypeDef *const regs = dev_cfg->regs; in mdio_xmc4xxx_transfer()
56 struct mdio_xmc4xxx_dev_data *const dev_data = dev->data; in mdio_xmc4xxx_transfer()
58 int ret = 0; in mdio_xmc4xxx_transfer()
[all …]
Dmdio_nxp_enet_qos.c4 * SPDX-License-Identifier: Apache-2.0
41 uint32_t val = base->MAC_MDIO_ADDRESS; in check_busy()
47 static int do_transaction(struct mdio_transaction *mdio) in do_transaction()
49 enet_qos_t *base = mdio->base; in do_transaction()
51 int ret; in do_transaction()
53 k_mutex_lock(mdio->mdio_bus_mutex, K_FOREVER); in do_transaction()
55 if (mdio->op == MDIO_OP_C22_WRITE) { in do_transaction()
56 base->MAC_MDIO_DATA = in do_transaction()
58 ENET_QOS_REG_PREP(MAC_MDIO_DATA, GD, mdio->write_data); in do_transaction()
60 } else if (mdio->op == MDIO_OP_C22_READ) { in do_transaction()
[all …]
/Zephyr-latest/drivers/pwm/
Dpwm_sam.c4 * SPDX-License-Identifier: Apache-2.0
30 uint8_t divider; member
33 static int sam_pwm_get_cycles_per_sec(const struct device *dev, in sam_pwm_get_cycles_per_sec()
36 const struct sam_pwm_config *config = dev->config; in sam_pwm_get_cycles_per_sec()
37 uint8_t prescaler = config->prescaler; in sam_pwm_get_cycles_per_sec()
38 uint8_t divider = config->divider; in sam_pwm_get_cycles_per_sec() local
41 ((1 << prescaler) * divider); in sam_pwm_get_cycles_per_sec()
46 static int sam_pwm_set_cycles(const struct device *dev, uint32_t channel, in sam_pwm_set_cycles()
50 const struct sam_pwm_config *config = dev->config; in sam_pwm_set_cycles()
52 Pwm * const pwm = config->regs; in sam_pwm_set_cycles()
[all …]
/Zephyr-latest/dts/bindings/adc/
Dnxp,vf610-adc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,vf610-adc"
8 include: [adc-controller.yaml, "nxp,rdc-policy.yaml"]
17 clk-source:
18 type: int
23 clk-divider:
24 type: int
27 Select clock divider: 0 clock divided by 1, 1 clock divided by 2, 2 clock divided by 4,
30 "#io-channel-cells":
33 io-channel-cells:
[all …]
Dadi,max32-adc.yaml1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "adi,max32-adc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
20 pinctrl-0:
23 pinctrl-names:
26 channel-count:
27 type: int
31 vref-mv:
32 type: int
[all …]
Dnxp,lpc-lpadc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,lpc-lpadc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
17 clk-divider:
18 type: int
19 description: clock divider for the converter
21 clk-source:
22 type: int
25 voltage-ref:
26 type: int
[all …]
/Zephyr-latest/dts/bindings/tcpc/
Dst,stm32-ucpd.yaml2 # SPDX-License-Identifier: Apache-2.0
5 ST STM32 family USB Type-C / Power Delivery. The default values were
8 compatible: "st,stm32-ucpd"
10 include: [base.yaml, pinctrl-device.yaml]
22 psc-ucpdclk:
24 type: int
26 - 1
27 - 2
28 - 4
29 - 8
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dadi,adltc2990.yaml2 # SPDX-License-Identifier: Apache-2.0
9 include: [sensor-device.yaml, i2c-device.yaml]
12 temperature-format:
13 type: int
19 - 0
20 - 1
22 acquistion-format:
23 type: int
29 - 0
30 - 1
[all …]
/Zephyr-latest/soc/nxp/kinetis/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
35 Set this option to use the oscillator in low-power mode.
40 Set this option to use the oscillator in high-gain mode.
45 int "External oscillator frequency"
55 hex "PLL external reference divider"
60 The resulting frequency must be in the range of 2 MHz to 4 MHz.
63 hex "VCO 0 divider"
72 int "Fast internal reference clock divider"
77 resulting frequency must be in the range 31.25 kHz to 4 MHz.
80 int "FLL external reference divider"
[all …]
/Zephyr-latest/samples/basic/fade_led/boards/
Drpi_pico.overlay3 divider-int-4 = <255>;
Dxiao_rp2040.overlay3 divider-int-4 = <255>;
/Zephyr-latest/drivers/watchdog/
Dwdt_fwdgt_gd32.c4 * SPDX-License-Identifier: Apache-2.0
37 #error Must be initial-timeout > 0
41 #error Must be initial-timeout <= (256 * 4095 * 1000 / GD32_LOW_SPEED_IRC_FREQUENCY)
51 * @return 0 on success, -EINVAL if the timeout is out of range
53 static int gd32_fwdgt_calc_timeout(uint32_t timeout, uint32_t *prescaler, in gd32_fwdgt_calc_timeout()
56 uint16_t divider = 4U; in gd32_fwdgt_calc_timeout() local
61 while ((ticks / divider) > FWDGT_RELOAD_MAX) { in gd32_fwdgt_calc_timeout()
63 divider = 4U << shift; in gd32_fwdgt_calc_timeout()
67 return -EINVAL; in gd32_fwdgt_calc_timeout()
72 *reload = (ticks / divider) - 1U; in gd32_fwdgt_calc_timeout()
[all …]
/Zephyr-latest/drivers/serial/
Duart_b91.c4 * SPDX-License-Identifier: Apache-2.0
22 ((const struct uart_b91_config *)dev->config)->uart_addr)
28 #define UART_DATA_SIZE ((uint8_t)4u)
37 #define UART_STOP_BIT_1P5 BIT(4)
92 FLD_UART_TX_IRQ_TRIQ_LEV_OFFSET = 4,
98 FLD_UART_TX_BUF_CNT_OFFSET = 4,
111 return (uart->bufcnt & FLD_UART_TX_BUF_CNT) >> FLD_UART_TX_BUF_CNT_OFFSET; in uart_b91_get_tx_bufcnt()
117 return (uart->bufcnt & FLD_UART_RX_BUF_CNT) >> FLD_UART_RX_BUF_CNT_OFFSET; in uart_b91_get_rx_bufcnt()
142 uint16_t *divider, uint8_t *bwpc) in uart_b91_cal_div_and_bwpc() argument
151 primeDec = 10 * pclk / baudrate - 10 * primeInt; in uart_b91_cal_div_and_bwpc()
[all …]
/Zephyr-latest/dts/bindings/misc/
Dnxp,s32-emios.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-emios"
21 interrupt-names:
27 clock-divider:
28 type: int
31 Clock divider value for the global prescaler. Could be in range [1 ... 256]
33 internal-cnt:
34 type: int
39 child-binding:
40 child-binding:
[all …]
/Zephyr-latest/soc/sifive/sifive_freedom/fu700/
Dclock.c4 * SPDX-License-Identifier: Apache-2.0
26 * - core: to 1GHz PLL (CORE_PLL) from 26MHz oscillator (HFCLK)
27 * - peri: to 250MHz PLL (HFPCLKPLL) from HFCLK
28 * - ddr: to 923MHz PLL (DDRPLL) from HFCLK (half of the data rate)
37 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
39 PLL_Q(2) | /* output divider: VCO / 2^2 = 1001MHz */ in soc_early_init_hook()
52 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
54 PLL_Q(4) | /* output divider: VCO / 2^4 = 250.25MHz */ in soc_early_init_hook()
67 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
69 PLL_Q(2) | /* output divider: VCO / 2^2 = 936MHz */ in soc_early_init_hook()
[all …]

123456