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/Zephyr-Core-3.6.0/scripts/kconfig/
Dkconfigfunctions.py202 The function will divide the value based on 'unit':
204 'k' or 'K' divide by 1024 (1 << 10)
205 'm' or 'M' divide by 1,048,576 (1 << 20)
206 'g' or 'G' divide by 1,073,741,824 (1 << 30)
207 'kb' or 'Kb' divide by 8192 (1 << 13)
208 'mb' or 'Mb' divide by 8,388,608 (1 << 23)
209 'gb' or 'Gb' divide by 8,589,934,592 (1 << 33)
231 The function will divide the value based on 'unit':
233 'k' or 'K' divide by 1024 (1 << 10)
234 'm' or 'M' divide by 1,048,576 (1 << 20)
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/Zephyr-Core-3.6.0/drivers/adc/
DKconfig.mcux47 prompt "Clock Divide Selection"
51 bool "Divide ratio is 1"
54 bool "Divide ratio is 2"
57 bool "Divide ratio is 4"
60 bool "Divide ratio is 8"
/Zephyr-Core-3.6.0/soc/arm/nxp_kinetis/k8x/
DKconfig.soc48 This option specifies the divide value for the K8x processor core clock
55 This option specifies the divide value for the K8x bus clock from the
62 This option specifies the divide value for the K8x FlexBus clock from the
69 This option specifies the divide value for the K8x flash clock from the
/Zephyr-Core-3.6.0/dts/bindings/clock/
Dlitex,clk.yaml48 litex,divclk-divide-min:
53 litex,divclk-divide-max:
78 litex,clkout-divide-min:
83 litex,clkout-divide-max:
Dmicrochip,xec-pcr.yaml17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
/Zephyr-Core-3.6.0/cmake/compiler/gcc/
Dtarget_x86.cmake21 # In order to use division, `--divide` needs to be passed to
23 list(APPEND TOOLCHAIN_C_FLAGS -Wa,--divide)
/Zephyr-Core-3.6.0/soc/arm/nxp_kinetis/
DKconfig74 Selects the amount to divide down the external reference clock for the PLL.
82 Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
91 Selects the amount to divide down the fast internal reference clock. The
99 Selects the amount to divide down the external reference clock for the
/Zephyr-Core-3.6.0/tests/arch/x86/static_idt/src/
Dmain.c75 * This is the handler for the divide by zero exception.
77 * The source of this divide-by-zero error comes from the following line in
88 * loop of divide-by-zero errors would be created.)
159 volatile int error; /* used to create a divide by zero error */ in ZTEST()
175 * issuing a 'divide by zero' warning. in ZTEST()
/Zephyr-Core-3.6.0/dts/bindings/sensor/
Dti,fdc2x1x.yaml233 1 = divide by 1. Choose for sensor frequencies between
235 2 = divide by 2. Choose for sensor frequencies between 5MHz
239 2 = divide by 2. Choose for sensor frequencies between
242 - 1 # Divide by 1
243 - 2 # Divide by 2
/Zephyr-Core-3.6.0/tests/ztest/error_hook/src/
Dmain.c97 * Do not optimize the divide instruction. GCC will generate invalid
98 * opcode exception instruction instead of real divide instruction.
105 /* divide by zero */ in trigger_fault_divide_zero()
112 * trigger an exception for divide zero. They might need to enable the divide in trigger_fault_divide_zero()
116 * which does not include a divide instruction, the test is skipped, in trigger_fault_divide_zero()
118 * For ARMv8-R, divide by zero trapping is not supported in hardware. in trigger_fault_divide_zero()
/Zephyr-Core-3.6.0/dts/bindings/timer/
Dnxp,s32-sys-timer.yaml24 Selects the module clock divide value for the prescaler, between 1 and 256.
/Zephyr-Core-3.6.0/dts/bindings/can/
Dinfineon,xmc4xxx-can-node.yaml20 description: Option enables clock divide by a factor of 8.
Dst,stm32-fdcan.yaml44 Divide by 1 is the peripherals reset value and remains set unless
Dst,stm32h7-fdcan.yaml44 Divide by 1 is the peripherals reset value and remains set unless this property is configured.
Dmicrochip,mcp251xfd.yaml74 description: The factor to divide the system clock for CLKO pin.
/Zephyr-Core-3.6.0/soc/arm/atmel_sam/sam4l/
Dsoc.c90 static inline uint32_t pll_config_init(uint32_t divide, uint32_t mul) in pll_config_init() argument
98 /* Divide output frequency by two */ in pll_config_init()
115 vco_hz /= divide; in pll_config_init()
134 (divide << SCIF_PLL_PLLDIV_Pos) | in pll_config_init()
/Zephyr-Core-3.6.0/drivers/sensor/mc3419/
DKconfig44 Rate is divide by this decimation rate. If decimation rate
/Zephyr-Core-3.6.0/subsys/shell/
Dshell_help.c13 * It takes care to not divide words.
65 * divide in the way to not divide words. in formatted_text_print()
/Zephyr-Core-3.6.0/arch/x86/core/
Dia32.cmake9 zephyr_compile_options($<$<COMPILE_LANGUAGE:ASM>:-Wa,--divide>)
/Zephyr-Core-3.6.0/dts/riscv/
Driscv32-litex-vexriscv.dtsi310 litex,divclk-divide-min = <1>;
311 litex,divclk-divide-max = <107>;
316 litex,clkout-divide-min = <1>;
317 litex,clkout-divide-max = <126>;
/Zephyr-Core-3.6.0/dts/bindings/serial/
Dcdns,uart.yaml24 description: Baud Rate Divide register value.
/Zephyr-Core-3.6.0/drivers/sensor/vl53l1x/
Dvl53l1_platform_user_config.h52 * FW stream divide - value of 254
/Zephyr-Core-3.6.0/dts/bindings/pwm/
Dinfineon,xmc4xxx-ccu8-pwm.yaml24 a separate prescaler to divide the clock. The clock divider is
95 The entry in the array will divide CCU clock by (2 << value).
Dinfineon,xmc4xxx-ccu4-pwm.yaml74 The entry in the array will divide CCU clock by (2 << value).
/Zephyr-Core-3.6.0/dts/bindings/display/
Dftdi,ft800.yaml19 The value to divide the main clock by for PCLK. If the

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