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/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
19 /delete-property/ hse-bypass;
20 /delete-property/ clock-frequency;
25 /delete-property/ hsi-div;
41 /delete-property/ div-m;
42 /delete-property/ mul-n;
43 /delete-property/ div-p;
44 /delete-property/ div-q;
45 /delete-property/ div-r;
46 /delete-property/ clocks;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/
Dclear_clocks.overlay4 * SPDX-License-Identifier: Apache-2.0
14 /delete-property/ hse-bypass;
15 /delete-property/ clock-frequency;
20 /delete-property/ hsi-div;
36 /delete-property/ div-m;
37 /delete-property/ mul-n;
38 /delete-property/ div-p;
39 /delete-property/ div-q;
40 /delete-property/ div-r;
41 /delete-property/ clocks;
[all …]
Dpll_hsi_96.overlay4 * SPDX-License-Identifier: Apache-2.0
13 hsi-div = <8>; /* HSI RC: 64MHz, hsi_clk = 8MHz */
18 div-m = <1>;
19 mul-n = <24>;
20 div-p = <2>;
21 div-q = <4>;
22 div-r = <2>;
29 clock-frequency = <DT_FREQ_M(96)>;
Dpll_hsi_fracn_550.overlay4 * SPDX-License-Identifier: Apache-2.0
13 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
18 div-m = <4>;
19 mul-n = <34>;
20 div-p = <1>;
21 div-q = <4>;
22 div-r = <2>;
30 clock-frequency = <DT_FREQ_M(550)>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/
Dclear_clocks.overlay5 * SPDX-License-Identifier: Apache-2.0
13 /* Keep csi on to be the usart1-console clock */
25 /delete-property/ clock-frequency;
26 /delete-property/ hse-bypass;
31 /delete-property/ hsi-div;
39 /delete-property/ div-m;
40 /delete-property/ mul-n;
41 /delete-property/ div-p;
42 /delete-property/ div-q;
43 /delete-property/ div-r;
[all …]
Dpll_csi_100.overlay5 * SPDX-License-Identifier: Apache-2.0
17 /* Test another couple of M-div N-mul to obtain 100MHz from the CSI */
19 div-m = <1>;
20 mul-n = <50>;
21 div-p = <2>;
22 div-q = <2>;
23 div-r = <2>;
30 clock-frequency = <DT_FREQ_M(100)>;
31 ahb-prescaler = <1>;
32 apb1-prescaler = <1>;
[all …]
Dpll_csi_240.overlay5 * SPDX-License-Identifier: Apache-2.0
17 /* Test another couple of M-div N-mul to obtain 240MHz from the CSI */
19 div-m = <1>;
20 mul-n = <120>;
21 div-p = <2>;
22 div-q = <2>;
23 div-r = <2>;
30 clock-frequency = <DT_FREQ_M(240)>;
31 ahb-prescaler = <1>;
32 apb1-prescaler = <1>;
[all …]
Dpll_hsi_240.overlay5 * SPDX-License-Identifier: Apache-2.0
14 hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
19 div-m = <4>;
20 mul-n = <30>;
21 div-p = <2>;
22 div-q = <2>;
23 div-r = <2>;
30 clock-frequency = <DT_FREQ_M(240)>;
31 ahb-prescaler = <1>;
32 apb1-prescaler = <1>;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dg4_i2c1_hsi_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-p;
25 /delete-property/ div-q;
26 /delete-property/ div-r;
27 /delete-property/ clocks;
32 /delete-property/ clocks;
[all …]
Dg0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-p;
25 /delete-property/ div-q;
26 /delete-property/ div-r;
27 /delete-property/ clocks;
32 /delete-property/ clocks;
[all …]
Dg0_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
22 /delete-property/ div-m;
23 /delete-property/ mul-n;
24 /delete-property/ div-p;
25 /delete-property/ div-q;
26 /delete-property/ div-r;
27 /delete-property/ clocks;
32 /delete-property/ clocks;
[all …]
Dl4_i2c1_hsi_lptim1_lse.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
23 /delete-property/ msi-range;
27 /delete-property/ div-m;
28 /delete-property/ mul-n;
29 /delete-property/ div-p;
30 /delete-property/ div-q;
31 /delete-property/ div-r;
32 /delete-property/ clocks;
[all …]
Dl4_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
23 /delete-property/ msi-range;
27 /delete-property/ div-m;
28 /delete-property/ mul-n;
29 /delete-property/ div-p;
30 /delete-property/ div-q;
31 /delete-property/ div-r;
32 /delete-property/ clocks;
[all …]
Dwl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
/Zephyr-latest/dts/bindings/clock/
Dst,stm32u0-pll-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
14 f(PLL_P) = f(VCO clock) / PLLP --> to ADC
15 f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
22 compatible: "st,stm32u0-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27 "#clock-cells":
33 div-m:
39 Valid range: 1 - 8
41 mul-n:
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
19 /delete-property/ clock-frequency;
20 /delete-property/ hse-bypass;
33 /delete-property/ msi-range;
34 /delete-property/ msi-pll-mode;
39 /delete-property/ msi-range;
40 /delete-property/ msi-pll-mode;
44 /delete-property/ div-m;
45 /delete-property/ mul-n;
46 /delete-property/ div-q;
[all …]
/Zephyr-latest/boards/shields/x_nucleo_iks02a1/boards/
Dnucleo_f411re.overlay4 * SPDX-License-Identifier: Apache-2.0
8 div-m = <8>;
9 mul-n = <192>;
10 div-r = <3>;
11 div-q = <4>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/
Dpll_48_hsi_16.overlay4 * SPDX-License-Identifier: Apache-2.0
17 div-m = <1>;
18 mul-n = <6>;
19 div-p = <2>;
20 div-q = <2>;
21 div-r = <2>;
28 clock-frequency = <DT_FREQ_M(48)>;
Dpll_g0_64_hsi_16.overlay4 * SPDX-License-Identifier: Apache-2.0
14 hsi-div = <1>;
18 div-m = <1>;
19 mul-n = <8>;
20 div-q = <2>;
21 div-r = <2>;
28 clock-frequency = <DT_FREQ_M(64)>;
Dpll_170_hse_24.overlay4 * SPDX-License-Identifier: Apache-2.0
13 clock-frequency = <DT_FREQ_M(24)>;
18 div-m = <6>;
19 mul-n = <85>;
20 div-p = <7>;
21 div-q = <2>;
22 div-r = <2>;
29 clock-frequency = <DT_FREQ_M(170)>;
Dclear_clocks.overlay4 * SPDX-License-Identifier: Apache-2.0
14 /delete-property/ hse-bypass;
15 /delete-property/ clock-frequency;
16 /delete-property/ hse-tcxo;
17 /delete-property/ hse-div2;
22 /delete-property/ hsi-div;
26 /delete-property/ div-m;
27 /delete-property/ mul-n;
28 /delete-property/ div-p;
29 /delete-property/ div-q;
[all …]
Dwb_pll_48_hsi_16.overlay4 * SPDX-License-Identifier: Apache-2.0
14 clock-frequency = <DT_FREQ_M(16)>;
19 div-m = <1>;
20 mul-n = <9>;
21 div-p = <2>;
22 div-q = <2>;
23 div-r = <3>;
30 clock-frequency = <DT_FREQ_M(48)>;
Dwb_pll_48_msi_4.overlay4 * SPDX-License-Identifier: Apache-2.0
15 msi-range = <6>; /* default value */
19 div-m = <1>;
20 mul-n = <24>;
21 div-p = <2>;
22 div-q = <2>;
23 div-r = <2>;
30 clock-frequency = <DT_FREQ_M(48)>;
Dwb_pll_64_hse_32.overlay4 * SPDX-License-Identifier: Apache-2.0
14 clock-frequency = <DT_FREQ_M(32)>; /* X1 32MHz oscillator */
19 div-m = <2>;
20 mul-n = <8>;
21 div-p = <2>;
22 div-q = <2>;
23 div-r = <2>;
30 clock-frequency = <DT_FREQ_M(64)>;
Dwl_pll_48_hse_32.overlay4 * SPDX-License-Identifier: Apache-2.0
10 * It applies to the stm32wl where the hse prescaler is 2 and by-passed
14 hse-tcxo;
15 hse-div2;
16 clock-frequency = <DT_FREQ_M(32)>;
21 div-m = <2>;
22 mul-n = <12>;
23 div-p = <2>;
24 div-q = <2>;
25 div-r = <2>;
[all …]

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