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/Zephyr-latest/drivers/dma/
DKconfig.xilinx_axi_dma4 # SPDX-License-Identifier: Apache-2.0
15 bool "Disable data cache while accessing Scatter-Gather Descriptors."
19 Disable dcache while operating on Scatter-Gather descriptors.
29 The Xilinx AXI DMA uses a ring of in-memory DMA descriptors which reference
35 int "Number of transfer descriptors allocated for reception (RX)."
39 The AXI DMA driver currently allocates a single DMA descriptor for each RX transfer,
43 prompt "IRQs to lock when manipulating per-channel data structures during dma_start."
52 This is required when calling dma_start outside of the TX/RX callbacks.
56 bool "Lock TX and RX IRQs"
59 This is only safe when dma_start is only called from the TX/RX callbacks (and possibly
[all …]
/Zephyr-latest/dts/bindings/serial/
Dnordic,nrf-uart-common.yaml1 include: [uart-controller.yaml, pinctrl-device.yaml, nordic-clockpin.yaml]
10 pinctrl-0:
13 pinctrl-names:
16 disable-rx:
19 Disable UART reception capabilities (only required to disable reception
22 current-speed:
28 - 1200
29 - 2400
30 - 4800
31 - 9600
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Drenesas,smartbond-uart.yaml3 compatible: "renesas,smartbond-uart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
14 periph-clock-config:
19 current-speed:
24 - 4800
25 - 9600
26 - 14400
27 - 19200
28 - 28800
29 - 38400
[all …]
/Zephyr-latest/soc/nuvoton/npcx/common/
Dsoc_power.h4 * SPDX-License-Identifier: Apache-2.0
15 * @brief Disable UART RX wake-up interrupt.
20 * @brief Enable UART RX wake-up interrupt.
/Zephyr-latest/tests/drivers/uart/uart_pm/
Dnrf_rx_disable.overlay1 /* SPDX-License-Identifier: Apache-2.0 */
4 disable-rx;
/Zephyr-latest/samples/bluetooth/direction_finding_central/
Doverlay-aod.conf4 # SPDX-License-Identifier: Apache-2.0
7 # Disable AoA Feature (antenna switching) in Rx mode in Controller and Host
/Zephyr-latest/samples/bluetooth/direction_finding_connectionless_rx/
Doverlay-aod.conf4 # SPDX-License-Identifier: Apache-2.0
7 # Disable AoA Feature (antenna switching) in Rx mode in Controller and Host
/Zephyr-latest/tests/boards/nrf/qdec/boards/
Dnrf54l15dk_nrf54l15_cpuapp.overlay3 * SPDX-License-Identifier: Apache-2.0
10 disable-rx;
Dnrf54l15dk_nrf54l15_cpuflpr.overlay3 * SPDX-License-Identifier: Apache-2.0
10 disable-rx;
/Zephyr-latest/samples/drivers/spi_flash_at45/boards/
Dnrf9160dk_nrf9160.overlay4 * SPDX-License-Identifier: Apache-2.0
21 low-power-enable;
27 pinctrl-0 = <&spi3_default_alt>;
28 pinctrl-1 = <&spi3_sleep_alt>;
29 pinctrl-names = "default", "sleep";
30 cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>,
36 spi-max-frequency = <15000000>;
37 jedec-id = [1f 24 00];
39 sector-size = <65536>;
40 block-size = <2048>;
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/Zephyr-latest/dts/bindings/ethernet/
Dxlnx,gem.yaml3 # SPDX-License-Identifier: Apache-2.0
10 include: ethernet-controller.yaml
19 clock-frequency:
27 which it will be adjusted at run-time. Therefore, the value of this
29 respective GEM's TX clock - by default, this is the IO PLL.
31 mdc-divider:
42 init-mdio-phy:
45 Activates the management of a PHY associated with the controller in-
46 stance. If this parameter is activated at the board level, the de-
47 fault values of the associated parameters mdio-phy-address, phy-poll-
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Dmicrochip,lan865x.yaml2 # SPDX-License-Identifier: Apache-2.0
5 LAN865x standalone 10BASE-T1L Ethernet controller with SPI interface.
9 include: [spi-device.yaml, ethernet-controller.yaml]
12 tx-cut-through-mode:
15 rx-cut-through-mode:
17 description: Enable RX cut through mode
18 plca-enable:
20 description: Enable or disable PLCA support
21 plca-node-id:
24 plca-node-count:
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/Zephyr-latest/drivers/ethernet/
Deth_smsc91x_priv.h3 * SPDX-License-Identifier: Apache-2.0
19 #define TCR_TXENA 0x0001 /* Enable/disable transmitter */
29 #define RCR_RXEN 0x0100 /* Enable/disable receiver */
30 #define RCR_STRIP_CRC 0x0200 /* Strip CRC from RX packets */
48 #define RPCR_DPLX 0x1000 /* Put PHY in full-duplex mode */
54 #define RPCR_LED_LINK_FDX 0x3 /* Full-duplex link detect */
56 #define RPCR_LED_ACT_ANY 0x4 /* TX or RX activity detected */
57 #define RPCR_LED_ACT_RX 0x6 /* RX activity detected */
62 #define CR_EPH_POWER_EN 0x8000 /* Disable/enable low power mode */
86 #define MMUCR_CMD_RELEASE 4 /* Remove and release from RX FIFO */
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/Zephyr-latest/drivers/net/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
13 bool "Point-to-point (PPP) UART based driver"
48 PPP ring buffer size when passing data from RX ISR to worker
55 Sets the stack size which will be used by the PPP RX workqueue.
58 int "RX workqueue thread priority"
61 Sets the priority of the RX workqueue thread.
68 to disable this as it takes some time to verify the received
77 to outside system. This requires a non-PPP network connection
93 six hex 8-bit chars separated by colons (e.g.:
105 bool "Disable PPP interface auto-start"
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/Zephyr-latest/tests/drivers/can/host/pytest/
Dtest_can.py3 # SPDX-License-Identifier: Apache-2.0
15 # RX/TX timeout in seconds
55 Class for testing CAN RX/TX between Zephyr DUT and host.
59 def check_rx(tx: can.Message, rx: can.Message) -> None:
61 # pylint: disable-next=unused-variable
64 if rx is None:
67 if not tx.equals(rx, timestamp_delta=None, check_channel=False,
69 pytest.fail(f'rx message "{rx}" not equal to tx message "{tx}"')
72 def skip_if_unsupported(can_dut: BusABC, can_host: BusABC, msg: can.Message) -> None:
80 def test_dut_to_host(self, can_dut: BusABC, can_host: BusABC, msg: can.Message) -> None:
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dnuvoton,numaker-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 use this node to set UART0 RX as pin PB12 to fulfill SYS_GPB_MFP3_PB12MFP_UART0_RXD.
22 /* configure PB13 as UART0 TX and PB12 as UART0 RX */
30 To link pin configurations with a device, use a pinctrl-N property for some
33 #include "board-pinctrl.dtsi"
36 pinctrl-0 = <&uart0_default>;
37 pinctrl-names = "default";
40 compatible: "nuvoton,numaker-pinctrl"
48 child-binding:
50 child-binding:
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Dti,cc32xx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route UART0 RX to pin 55 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
37 /* configure pin 57 as UART0 RX and pin 62 as UART0 RTS */
39 /* both pin 57 and 62 have pull-up enabled */
40 bias-pull-up;
53 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
56 - drive-push-pull: Push-pull drive mode (default, not required).
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/Zephyr-latest/drivers/serial/
Duart_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
50 /* Disable interrupts on UART1 RX pin to avoid repeated interrupts. */ in uart1_wui_isr()
51 (void)gpio_pin_interrupt_configure(gpio, (find_msb_set(pins) - 1), in uart1_wui_isr()
54 /* Refresh console expired time if got UART Rx wake-up event */ in uart1_wui_isr()
63 k_work_reschedule(&uart_console_data->rx_refresh_timeout_work, delay); in uart1_wui_isr()
70 /* Disable interrupts on UART2 RX pin to avoid repeated interrupts. */ in uart2_wui_isr()
71 (void)gpio_pin_interrupt_configure(gpio, (find_msb_set(pins) - 1), in uart2_wui_isr()
74 /* Refresh console expired time if got UART Rx wake-up event */ in uart2_wui_isr()
83 k_work_reschedule(&uart_console_data->rx_refresh_timeout_work, delay); in uart2_wui_isr()
90 const struct uart_it8xxx2_config *const config = dev->config; in uart_it8xxx2_pm_action()
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/Zephyr-latest/drivers/misc/coresight/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
4 DT_COMPAT_NORDIC_NRF_TBM := nordic,nrf-tbm
75 frames. Use 0 to disable.
96 int "Size of the RX buffer"
99 Size of a single RX buffer. Together with buffer count it defines the
100 space that can hold RX data. It may be decreased if shell input is
105 int "Number of RX buffers"
109 Number of RX buffers.
/Zephyr-latest/tests/bsim/bluetooth/host/l2cap/reassembly/dut/
Dprj.conf21 # Disable auto-initiated procedures so they don't
28 # RX buffer pool, it is a good idea to constrain said buffer
/Zephyr-latest/boards/digilent/zybo/
Dzybo-pinctrl.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pinctrl/pinctrl-zynq.h>
10 pinctrl_uart1_default: uart1-default {
18 slew-rate = <IO_SPEED_SLOW>;
19 power-source = <IO_STANDARD_LVCMOS18>;
22 conf-rx {
24 bias-high-impedance;
27 conf-tx {
29 bias-disable;
/Zephyr-latest/boards/pjrc/teensy4/
Dteensy4-pinctrl.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 #include <nxp/nxp_imx/rt/mimxrt1062dvl6a-pinctrl.dtsi>
17 bias-disable;
18 drive-strength = "r0-6";
19 slew-rate = "slow";
20 nxp,speed = "100-mhz";
21 input-enable;
31 drive-strength = "r0-5";
32 bias-pull-up;
33 bias-pull-up-value = "100k";
[all …]
/Zephyr-latest/drivers/dai/nxp/sai/
Dsai.c4 * SPDX-License-Identifier: Apache-2.0
53 cfg = dev->config; in sai_mclk_config()
54 data = dev->data; in sai_mclk_config()
56 mclk_config.mclkOutputEnable = cfg->mclk_is_output; in sai_mclk_config()
65 ret = get_mclk_rate(&cfg->clk_data, bclk_source, &mclk_rate); in sai_mclk_config()
73 LOG_DBG("target MCLK is %u", bespoke->mclk_rate); in sai_mclk_config()
79 mclk_config.mclkHz = bespoke->mclk_rate; in sai_mclk_config()
82 SAI_SetMasterClockConfig(UINT_TO_I2S(data->regmap), &mclk_config); in sai_mclk_config()
84 set_msel(data->regmap, msel); in sai_mclk_config()
96 data = dev->data; in sai_isr()
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/Zephyr-latest/samples/drivers/mbox_data/remote/boards/
Dmimxrt1160_evk_mimxrt1166_cm4.overlay4 * SPDX-License-Identifier: Apache-2.0
11 zephyr,shell-uart = &lpuart2;
16 /delete-property/ zephyr,ipc;
20 /delete-node/ gpt@400f0000;
24 compatible = "nxp,gpt-hw-timer";
30 /* Delete IPM Driver node nxp,imx-mu */
31 /delete-node/ mailbox@40c4c000;
35 compatible = "nxp,mbox-imx-mu";
38 rx-channels = <4>;
39 #mbox-cells = <1>;
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Dmimxrt1170_evk_mimxrt1176_cm4.overlay4 * SPDX-License-Identifier: Apache-2.0
11 zephyr,shell-uart = &lpuart2;
16 /delete-property/ zephyr,ipc;
20 /delete-node/ gpt@400f0000;
24 compatible = "nxp,gpt-hw-timer";
30 /* Delete IPM Driver node nxp,imx-mu */
31 /delete-node/ mailbox@40c4c000;
35 compatible = "nxp,mbox-imx-mu";
38 rx-channels = <4>;
39 #mbox-cells = <1>;
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