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/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/svd/
Dpsoc6_04.svd8 <description>PSoC6_04</description>
42 <description>Peripheral interconnect</description>
52 <description>Timeout control</description>
61 …<description>This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer…
63 …rformed: a bus transfer will never be terminated and a fault will never be generated.</description>
71 <description>Trigger command</description>
80description>Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not …
86 <description>Specifies the trigger group:
88 '16'-'31': trigger 1-to-1 groups.</description>
94 …<description>Specifies if the activated trigger is treated as a level sensitive or edge sensitive…
[all …]
Dpsoc6_02.svd8 <description>PSoC6_02</description>
42 <description>Peripheral interconnect</description>
52 <description>Timeout control</description>
61 …<description>This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer…
63 …rformed: a bus transfer will never be terminated and a fault will never be generated.</description>
71 <description>Trigger command</description>
80description>Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not …
86 <description>Specifies the trigger group:
88 '16'-'31': trigger 1-to-1 groups.</description>
94 …<description>Specifies if the activated trigger is treated as a level sensitive or edge sensitive…
[all …]
Dpsoc6_01.svd8 <description>PSoC6_01</description>
42 <description>Peripheral interconnect</description>
54 <description>Peripheral group structure</description>
58 <description>Clock control</description>
67 …<description>Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group cl…
69 …l be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
77 <description>Slave control</description>
86description>Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO…
92 …<description>Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (c…
94 …MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.</description>
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Dpsoc6_03.svd8 <description>PSoC6_03</description>
42 <description>Peripheral interconnect</description>
52 <description>Timeout control</description>
61 …<description>This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer…
63 …rformed: a bus transfer will never be terminated and a fault will never be generated.</description>
71 <description>Trigger command</description>
80description>Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not …
86 <description>Specifies the trigger group:
88 '16'-'31': trigger 1-to-1 groups.</description>
94 …<description>Specifies if the activated trigger is treated as a level sensitive or edge sensitive…
[all …]
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/svd/
Dcyw20829.svd8 <description>CYW20829</description>
42 <description>Peripheral interconnect</description>
52 <description>Timeout control</description>
61 …<description>This field specifies a number of peripheral group root undivided (clk_group_root[i]) …
63 …are excluded from timeout (Refer Timeout section in mxsperi.1 BROS for more details).</description>
69 …<description>This field provides control for HW to reset the slave that is causing the timeout to …
74 …are excluded from timeout (Refer Timeout section in mxsperi.1 BROS for more details).</description>
84 <description>AHB error status1</description>
93description>This field indicates the AHB transaction address[31:0] that the AHB error response is …
103 <description>AHB error status2</description>
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/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/svd/
Dcat1c8m.svd8 <description>XMC7200</description>
42 <description>Peripheral interconnect</description>
52 <description>Timeout control</description>
61 …<description>This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer…
63 …rformed: a bus transfer will never be terminated and a fault will never be generated.</description>
71 <description>Trigger command</description>
80description>Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not …
86 <description>Specifies the trigger group:
88 '16'-'31': trigger 1-to-1 groups.</description>
94 …<description>Specifies if the activated trigger is treated as a level sensitive or edge sensitive…
[all …]
Dcat1c4m.svd8 <description>XMC7100</description>
42 <description>Peripheral interconnect</description>
52 <description>Timeout control</description>
61 …<description>This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer…
63 …rformed: a bus transfer will never be terminated and a fault will never be generated.</description>
71 <description>Trigger command</description>
80description>Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not …
86 <description>Specifies the trigger group:
88 '16'-'31': trigger 1-to-1 groups.</description>
94 …<description>Specifies if the activated trigger is treated as a level sensitive or edge sensitive…
[all …]
/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_fault.h124 CY_SYSFAULT_MPU_1 = 1, /* Bus master 1 MPU. See MPU_0 description. */
125 CY_SYSFAULT_MPU_2 = 2, /* Bus master 2 MPU. See MPU_0 description. */
126 CY_SYSFAULT_MPU_3 = 3, /* Bus master 3 MPU. See MPU_0 description. */
127 CY_SYSFAULT_MPU_4 = 4, /* Bus master 4 MPU. See MPU_0 description. */
128 CY_SYSFAULT_MPU_5 = 5, /* Bus master 5 MPU. See MPU_0 description. */
129 CY_SYSFAULT_MPU_6 = 6, /* Bus master 6 MPU. See MPU_0 description. */
130 CY_SYSFAULT_MPU_7 = 7, /* Bus master 7 MPU. See MPU_0 description. */
131 CY_SYSFAULT_MPU_8 = 8, /* Bus master 8 MPU. See MPU_0 description. */
132 CY_SYSFAULT_MPU_9 = 9, /* Bus master 9 MPU. See MPU_0 description. */
133 CY_SYSFAULT_MPU_10 = 10, /* Bus master 10 MPU. See MPU_0 description. */
[all …]
/hal_infineon-3.5.0/XMCLib/drivers/inc/
Dxmc_eth_mac.h411 * \par<b>Description: </b><br>
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Dxmc4_scu.h975 * \par<b>Description</b><br>
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Dxmc_can.h609 * \par<b>Description:</b><br>
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Dxmc_bccu.h50 * <b>Detailed description of file:</b><br>
521 * \par<b>Description:</b><br>
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Dxmc_vadc.h1393 * \par<b>Description:</b><br>
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Dxmc_dma.h461 * \par<b>Description: </b><br>
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Dxmc_usic.h599 * \par<b>Description</b><br>
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Dxmc_sdmmc.h643 * \par<b>Description: </b><br>
656 * \par<b>Description: </b><br>
668 * \par<b>Description: </b><br>
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Dxmc_ccu4.h818 * \par<b>Description:</b><br>
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Dxmc_spi.h349 * \par<b>Description:</b><br>
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Dxmc_ccu8.h1110 * \par<b>Description:</b><br>
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Dxmc_math.h255 * \par<b>Description:</b><br>
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Dxmc_hrpwm.h48 * - Driver description updated<br>
877 * \par<b>Description </b>
893 * \par<b>Description </b>
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Dxmc_fce.h43 * - Description updated <br>
248 * \par<b>Description: </b><br>
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Dxmc_i2c.h43 * - Description updated <br>
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Dxmc_dac.h50 * - Driver description added
363 * \par<b>Description:</b><br>
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/hal_infineon-3.5.0/zephyr/
Dmodule.yml14 description: "PSoC 6 Cortex M0+ DeepSleep prebuilt image (CM0P_SLEEP)"
22 description: "PSoC 6 Cortex M0+ DeepSleep prebuilt image (CM0P_SLEEP)"
30 description: "PSoC 6 Cortex M0+ DeepSleep prebuilt image (CM0P_SLEEP)"
38 description: "PSoC 6 Cortex M0+ DeepSleep prebuilt image (CM0P_SLEEP)"
50 description: "Wi-Fi Firmware for CYW43012 Device"
59 description: "Wi-Fi Firmware (mfgtest) for CYW43012 Device"
68 description: "Wi-Fi CLM for CYW43012 Device"
77 description: "Wi-Fi CLM (mfgtest) for CYW43012 Device"
88 description: "Wi-Fi Firmware for CYW4343W (mfgtest) Device"
97 description: "Wi-Fi Firmware for CYW4343W Device"
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