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/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1A/svd/ |
D | psoc6_04.svd | 8 <description>PSoC6_04</description> 42 <description>Peripheral interconnect</description> 52 <description>Timeout control</description> 61 …<description>This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer… 63 …rformed: a bus transfer will never be terminated and a fault will never be generated.</description> 71 <description>Trigger command</description> 80 …description>Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not … 86 <description>Specifies the trigger group: 88 '16'-'31': trigger 1-to-1 groups.</description> 94 …<description>Specifies if the activated trigger is treated as a level sensitive or edge sensitive… [all …]
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D | psoc6_02.svd | 8 <description>PSoC6_02</description> 42 <description>Peripheral interconnect</description> 52 <description>Timeout control</description> 61 …<description>This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer… 63 …rformed: a bus transfer will never be terminated and a fault will never be generated.</description> 71 <description>Trigger command</description> 80 …description>Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not … 86 <description>Specifies the trigger group: 88 '16'-'31': trigger 1-to-1 groups.</description> 94 …<description>Specifies if the activated trigger is treated as a level sensitive or edge sensitive… [all …]
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D | psoc6_01.svd | 8 <description>PSoC6_01</description> 42 <description>Peripheral interconnect</description> 54 <description>Peripheral group structure</description> 58 <description>Clock control</description> 67 …<description>Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group cl… 69 …l be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description> 77 <description>Slave control</description> 86 …description>Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO… 92 …<description>Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (c… 94 …MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.</description> [all …]
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D | psoc6_03.svd | 8 <description>PSoC6_03</description> 42 <description>Peripheral interconnect</description> 52 <description>Timeout control</description> 61 …<description>This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer… 63 …rformed: a bus transfer will never be terminated and a fault will never be generated.</description> 71 <description>Trigger command</description> 80 …description>Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not … 86 <description>Specifies the trigger group: 88 '16'-'31': trigger 1-to-1 groups.</description> 94 …<description>Specifies if the activated trigger is treated as a level sensitive or edge sensitive… [all …]
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/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1B/svd/ |
D | cyw20829.svd | 8 <description>CYW20829</description> 42 <description>Peripheral interconnect</description> 52 <description>Timeout control</description> 61 …<description>This field specifies a number of peripheral group root undivided (clk_group_root[i]) … 63 …are excluded from timeout (Refer Timeout section in mxsperi.1 BROS for more details).</description> 69 …<description>This field provides control for HW to reset the slave that is causing the timeout to … 74 …are excluded from timeout (Refer Timeout section in mxsperi.1 BROS for more details).</description> 84 <description>AHB error status1</description> 93 …description>This field indicates the AHB transaction address[31:0] that the AHB error response is … 103 <description>AHB error status2</description> [all …]
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/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/svd/ |
D | cat1c8m.svd | 8 <description>XMC7200</description> 42 <description>Peripheral interconnect</description> 52 <description>Timeout control</description> 61 …<description>This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer… 63 …rformed: a bus transfer will never be terminated and a fault will never be generated.</description> 71 <description>Trigger command</description> 80 …description>Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not … 86 <description>Specifies the trigger group: 88 '16'-'31': trigger 1-to-1 groups.</description> 94 …<description>Specifies if the activated trigger is treated as a level sensitive or edge sensitive… [all …]
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D | cat1c4m.svd | 8 <description>XMC7100</description> 42 <description>Peripheral interconnect</description> 52 <description>Timeout control</description> 61 …<description>This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer… 63 …rformed: a bus transfer will never be terminated and a fault will never be generated.</description> 71 <description>Trigger command</description> 80 …description>Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not … 86 <description>Specifies the trigger group: 88 '16'-'31': trigger 1-to-1 groups.</description> 94 …<description>Specifies if the activated trigger is treated as a level sensitive or edge sensitive… [all …]
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/hal_infineon-3.5.0/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/ |
D | cyip_fault.h | 124 CY_SYSFAULT_MPU_1 = 1, /* Bus master 1 MPU. See MPU_0 description. */ 125 CY_SYSFAULT_MPU_2 = 2, /* Bus master 2 MPU. See MPU_0 description. */ 126 CY_SYSFAULT_MPU_3 = 3, /* Bus master 3 MPU. See MPU_0 description. */ 127 CY_SYSFAULT_MPU_4 = 4, /* Bus master 4 MPU. See MPU_0 description. */ 128 CY_SYSFAULT_MPU_5 = 5, /* Bus master 5 MPU. See MPU_0 description. */ 129 CY_SYSFAULT_MPU_6 = 6, /* Bus master 6 MPU. See MPU_0 description. */ 130 CY_SYSFAULT_MPU_7 = 7, /* Bus master 7 MPU. See MPU_0 description. */ 131 CY_SYSFAULT_MPU_8 = 8, /* Bus master 8 MPU. See MPU_0 description. */ 132 CY_SYSFAULT_MPU_9 = 9, /* Bus master 9 MPU. See MPU_0 description. */ 133 CY_SYSFAULT_MPU_10 = 10, /* Bus master 10 MPU. See MPU_0 description. */ [all …]
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/hal_infineon-3.5.0/XMCLib/drivers/inc/ |
D | xmc_eth_mac.h | 411 * \par<b>Description: </b><br> 424 * \par<b>Description: </b><br> 439 * \par<b>Description: </b><br> 452 * \par<b>Description: </b><br> 465 * \par<b>Description: </b><br> 477 * \par<b>Description: </b><br> 489 * \par<b>Description: </b><br> 502 * \par<b>Description: </b><br> 523 * \par<b>Description: </b><br> 539 * \par<b>Description: </b><br> [all …]
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D | xmc4_scu.h | 975 * \par<b>Description</b><br> 994 * \par<b>Description</b><br> 1005 * \par<b>Description</b><br> 1017 * \par<b>Description</b><br> 1031 * \par<b>Description</b><br> 1049 * \par<b>Description</b><br> 1080 * \par<b>Description</b><br> 1103 * \par<b>Description</b><br> 1117 * \par<b>Description</b><br> 1130 * \par<b>Description</b><br> [all …]
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D | xmc_can.h | 609 * \par<b>Description:</b><br> 626 * \par<b>Description:</b><br> 647 * \par<b>Description:</b><br> 666 * \par<b>Description:</b><br> 689 * \par<b>Description:</b><br> 722 * \par<b>Description:</b><br> 751 * \par<b>Description:</b><br> 772 * \par<b>Description:</b><br> 783 * \par<b>Description:</b><br> 794 * \par<b>Description:</b><br> [all …]
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D | xmc_bccu.h | 50 * <b>Detailed description of file:</b><br> 521 * \par<b>Description:</b><br> 543 * \par<b>Description:</b><br> 560 * \par<b>Description:</b><br> 580 * \par<b>Description:</b><br> 596 * \par<b>Description:</b><br> 616 * \par<b>Description:</b><br> 631 * \par<b>Description:</b><br> 651 * \par<b>Description:</b><br> 667 * \par<b>Description:</b><br> [all …]
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D | xmc_vadc.h | 1393 * \par<b>Description:</b><br> 1410 * \par<b>Description:</b><br> 1428 * \par<b>Description:</b><br> 1446 * \par<b>Description:</b><br> 1466 * \par<b>Description:</b><br> 1486 * \par<b>Description:</b><br> 1505 * \par<b>Description:</b><br> 1527 * \par<b>Description:</b><br> 1553 * \par<b>Description:</b><br> 1575 * \par<b>Description:</b><br> [all …]
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D | xmc_dma.h | 461 * \par<b>Description: </b><br> 474 * \par<b>Description: </b><br> 488 * \par<b>Description: </b><br> 502 * \par<b>Description: </b><br> 517 * \par<b>Description: </b><br> 542 * \par<b>Description: </b><br> 557 * \par<b>Description: </b><br> 572 * \par<b>Description: </b><br> 591 * \par<b>Description: </b><br> 610 * \par<b>Description: </b><br> [all …]
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D | xmc_usic.h | 599 * \par<b>Description</b><br> 613 * \par<b>Description</b><br> 627 * \par<b>Description</b><br> 641 * \par<b>Description</b><br> 662 * \par<b>Description</b><br> 684 * \par<b>Description</b><br> 701 * \par<b>Description</b><br> 716 * \par<b>Description</b><br> 731 * \par<b>Description</b><br> 753 * \par<b>Description</b><br> [all …]
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D | xmc_sdmmc.h | 643 * \par<b>Description: </b><br> 656 * \par<b>Description: </b><br> 668 * \par<b>Description: </b><br> 682 * \par<b>Description: </b><br> 697 * \par<b>Description: </b><br> 714 * \par<b>Description: </b><br> 734 * \par<b>Description: </b><br> 749 * \par<b>Description: </b><br> 764 * \par<b>Description: </b><br> 779 * \par<b>Description: </b><br> [all …]
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D | xmc_ccu4.h | 818 * \par<b>Description:</b><br> 836 * \par<b>Description:</b><br> 851 * \par<b>Description:</b><br> 866 * \par<b>Description:</b><br> 882 * \par<b>Description:</b><br> 903 * \par<b>Description:</b><br> 923 * \par<b>Description:</b><br> 945 * \par<b>Description:</b><br> 969 * \par<b>Description:</b><br> 993 * \par<b>Description:</b><br> [all …]
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D | xmc_spi.h | 349 * \par<b>Description:</b><br> 378 * \par<b>Description:</b><br> 399 * \par<b>Description:</b><br> 417 * \par<b>Description:</b><br> 434 * \par<b>Description:</b><br> 449 * \par<b>Description:</b><br> 465 * \par<b>Description:</b><br> 481 * \par<b>Description:</b><br> 503 * \par<b>Description:</b><br> 523 * \par<b>Description:</b><br> [all …]
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D | xmc_ccu8.h | 1110 * \par<b>Description:</b><br> 1127 * \par<b>Description:</b><br> 1142 * \par<b>Description:</b><br> 1159 * \par<b>Description:</b><br> 1174 * \par<b>Description:</b><br> 1195 * \par<b>Description:</b><br> 1213 * \par<b>Description:</b><br> 1232 * \par<b>Description:</b><br> 1249 * \par<b>Description:</b><br> 1267 * \par<b>Description:</b><br> [all …]
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D | xmc_math.h | 255 * \par<b>Description:</b><br> 275 * \par<b>Description:</b><br> 297 * \par<b>Description:</b><br> 312 * \par<b>Description:</b><br> 328 * \par<b>Description:</b><br> 345 * \par<b>Description:</b><br> 365 * \par<b>Description:</b><br> 385 * \par<b>Description:</b><br> 405 * \par<b>Description:</b><br> 423 * \par<b>Description:</b><br> [all …]
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D | xmc_hrpwm.h | 48 * - Driver description updated<br> 877 * \par<b>Description </b> 893 * \par<b>Description </b> 907 * \par<b>Description </b> 922 * \par<b>Description </b> 941 * \par<b>Description </b> 962 * \par<b>Description </b> 976 * \par<b>Description</b> 1003 * \par<b>Description </b> 1025 * \par<b>Description </b> [all …]
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D | xmc_fce.h | 43 * - Description updated <br> 248 * \par<b>Description: </b><br> 264 * \par<b>Description: </b><br> 279 * \par<b>Description: </b><br> 295 * \par<b>Description: </b><br> 311 * \par<b>Description: </b><br> 328 * \par<b>Description: </b><br> 340 * \par<b>Description: </b><br> 358 * \par<b>Description: </b><br> 374 * \par<b>Description: </b><br> [all …]
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D | xmc_i2c.h | 43 * - Description updated <br> 283 * \par<b>Description:</b><br> 302 * \par<b>Description:</b><br> 320 * \par<b>Description:</b><br> 336 * \par<b>Description:</b><br> 355 * \par<b>Description:</b><br> 371 * \par<b>Description:</b><br> 401 * \par<b>Description</b><br> 425 * \par<b>Description</b><br> 444 * \par<b>Description:</b><br> [all …]
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D | xmc_dac.h | 50 * - Driver description added 363 * \par<b>Description:</b><br> 382 * \par<b>Description:</b><br> 401 * \par<b>Description:</b><br> 418 * \par<b>Description:</b><br> 444 * \par<b>Description:</b><br> 469 * \par<b>Description:</b><br> 494 * \par<b>Description:</b><br> 510 * \par<b>Description:</b><br> 535 * \par<b>Description:</b><br> [all …]
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/hal_infineon-3.5.0/zephyr/ |
D | module.yml | 14 description: "PSoC 6 Cortex M0+ DeepSleep prebuilt image (CM0P_SLEEP)" 22 description: "PSoC 6 Cortex M0+ DeepSleep prebuilt image (CM0P_SLEEP)" 30 description: "PSoC 6 Cortex M0+ DeepSleep prebuilt image (CM0P_SLEEP)" 38 description: "PSoC 6 Cortex M0+ DeepSleep prebuilt image (CM0P_SLEEP)" 50 description: "Wi-Fi Firmware for CYW43012 Device" 59 description: "Wi-Fi Firmware (mfgtest) for CYW43012 Device" 68 description: "Wi-Fi CLM for CYW43012 Device" 77 description: "Wi-Fi CLM (mfgtest) for CYW43012 Device" 88 description: "Wi-Fi Firmware for CYW4343W (mfgtest) Device" 97 description: "Wi-Fi Firmware for CYW4343W Device" [all …]
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