Lines Matching full:description
8 <description>PSoC6_01</description>
42 <description>Peripheral interconnect</description>
54 <description>Peripheral group structure</description>
58 <description>Clock control</description>
67 …<description>Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group cl…
69 …l be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
77 <description>Slave control</description>
86 …description>Peripheral group, slave 0 enable. This field is for the peripheral group internal MMIO…
92 …<description>Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (c…
94 …MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.</description>
100 …<description>Peripheral group, slave 2 enable. If the slave is disabled, its clock is gated off (c…
102 …MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.</description>
108 <description>N/A</description>
114 <description>N/A</description>
120 <description>N/A</description>
126 <description>N/A</description>
132 <description>N/A</description>
138 <description>N/A</description>
144 <description>N/A</description>
150 <description>N/A</description>
156 <description>N/A</description>
162 <description>N/A</description>
168 <description>N/A</description>
174 <description>N/A</description>
180 <description>N/A</description>
188 <description>Timeout control</description>
197 …<description>This field specifies a number of peripheral group (clk_group) clock cycles. If an AHB…
199 …rformed: a bus transfer will never be terminated and a fault will never be generated.</description>
208 <description>Divider command register</description>
217 …<description>(TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is pe…
219 … (default/reset value), no divider is specified and no clock signal(s) are generated.</description>
225 … <description>Specifies the divider type of the divider on which the command is performed:
229 3: 24.5 (fractional) clock dividers.</description>
235 …<description>(PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed…
237 If PA_DIV_SEL is '63' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference.</description>
243 …<description>Specifies the divider type of the divider to which phase alignment is performed for t…
247 3: 24.5 (fractional) clock dividers.</description>
253 …<description>Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to…
257 …mediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately.</description>
263 …<description>Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets th…
272 …y. SW can set this field to '0' during phase alignment to abort the enabling process.</description>
282 <description>Divider control register (for 8.0 divider)</description>
291 …<description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets …
293 …es NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
299 …<description>Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256].…
305 …l be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
315 <description>Divider control register (for 16.0 divider)</description>
324 …<description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets …
326 …es NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
332 …<description>Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,5…
338 …l be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
348 <description>Divider control register (for 16.5 divider)</description>
357 …<description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets …
359 …es NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
365 …<description>Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range […
367 …l be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
373 …<description>Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,5…
379 …l be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
389 <description>Divider control register (for 24.5 divider)</description>
398 …<description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets …
400 …es NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
406 …<description>Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range […
408 …l be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
414 …<description>Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,7…
420 …l be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
430 <description>Clock control register</description>
439 <description>Specifies one of the dividers of the divider type specified by TYPE_SEL.
443 …3') for a transition time that is larger than the smaller of the two divider periods.</description>
449 <description>Specifies divider type:
453 3: 24.5 (fractional) clock dividers.</description>
461 <description>Trigger command register</description>
470 …description>Specifies the activated trigger when ACTIVATE is '1'. OUT_SEL specifies whether the ac…
476 <description>Specifies the trigger group.</description>
482 …description>Amount of 'clk_peri' cycles a specific trigger is activated. During activation (ACTIVA…
488 …<description>Specifies whether trigger activation is for a specific input or ouput trigger of the …
490 …lection and trigger activation is for an output trigger from the trigger multiplexer.</description>
496 …description>SW sets this field to '1' by to activate (set to '1') a trigger as identified by TR_SE…
506 <description>Trigger group</description>
512 <description>Trigger control register</description>
521 …description>Specifies input trigger. This field is typically set during the setup of a chip use ca…
527 <description>Specifies if the output trigger is inverted.</description>
533 …<description>Specifies if the (inverted) output trigger is treated as a level sensitive or edge se…
535 …nized to the consumer clock and a two cycle pulse is generated on the consumer clock.</description>
546 <description>PPU structure with programmable address</description>
550 <description>PPU region address 0 (slave structure)</description>
559 …<description>This field is used to individually disabled the eight equally sized subregions in whi…
568 … Note that the smallest region size is 256 B and the smallest subregion size is 32 B.</description>
574 …description>This field specifies the most significant bits of the 32-bit address of an address reg…
582 <description>PPU region attributes 0 (slave structure)</description>
591 <description>User read enable:
593 '1': Enabled (user, read accesses are allowed).</description>
599 <description>User write enable:
601 '1': Enabled (user, write accesses are allowed).</description>
607 <description>User execute enable:
609 '1': Enabled (user, execute accesses are allowed).</description>
615 <description>Privileged read enable:
617 '1': Enabled (privileged, read accesses are allowed).</description>
623 <description>Privileged write enable:
625 '1': Enabled (privileged, write accesses are allowed).</description>
631 <description>Privileged execute enable:
633 '1': Enabled (privileged, execute accesses are allowed).</description>
639 <description>Non-secure:
641 '1': Non-secure (both secure and non-secure accesses allowed).</description>
647 …<description>This field specifies protection context identifier based access control for protectio…
653 … <description>This field specifies protection context identifier based access control.
654 …ed; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.</description>
660 <description>This field specifies the region size:
686 '31': 4 GB region</description>
692 …<description>This field specifies if the PC field participates in the 'matching' process or the 'a…
696 … multiple protection structures with the same address region and PC_MATCH set to '1'.</description>
702 <description>Region enable:
706 … a disabled address region performs logic gating to reduce dynamic power consumption.</description>
714 <description>PPU region address 1 (master structure)</description>
723 <description>See corresponding field for PPU structure with programmable address.
727 Note: this field is read-only.</description>
733 <description>See corresponding field for PPU structure with programmable address.
737 Note: this field is read-only.</description>
745 <description>PPU region attributes 1 (master structure)</description>
754 <description>See corresponding field for PPU structure with programmable address.
756 Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.</description>
762 … <description>See corresponding field for PPU structure with programmable address.</description>
768 <description>See corresponding field for PPU structure with programmable address.
770 Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.</description>
776 <description>See corresponding field for PPU structure with programmable address.
778 …that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.</description>
784 … <description>See corresponding field for PPU structure with programmable address.</description>
790 <description>See corresponding field for PPU structure with programmable address.
792 …at this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.</description>
798 … <description>See corresponding field for PPU structure with programmable address.</description>
804 … <description>See corresponding field for PPU structure with programmable address.</description>
810 … <description>See corresponding field for PPU structure with programmable address.</description>
816 <description>See corresponding field for PPU structure with programmable address.
818 '7': 256 B region</description>
824 … <description>See corresponding field for PPU structure with programmable address.</description>
830 … <description>See corresponding field for PPU structure with programmable address.</description>
841 … <description>PPU structure with fixed/constant address for a peripheral group</description>
845 <description>PPU region address 0 (slave structure)</description>
854 <description>See corresponding field for PPU structure with programmable address.
856 Note: this field is read-only. Its value is chip specific.</description>
862 <description>See corresponding field for PPU structure with programmable address.
866 Note: this field is read-only. Its value is chip specific.</description>
874 <description>PPU region attributes 0 (slave structure)</description>
883 … <description>See corresponding field for PPU structure with programmable address.</description>
889 … <description>See corresponding field for PPU structure with programmable address.</description>
895 <description>See corresponding field for PPU structure with programmable address.
897 …te that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.</description>
903 … <description>See corresponding field for PPU structure with programmable address.</description>
909 … <description>See corresponding field for PPU structure with programmable address.</description>
915 <description>See corresponding field for PPU structure with programmable address.
917 …te that this register is constant '1'; i.e. user execute accesses are ALWAYS allowed.</description>
923 … <description>See corresponding field for PPU structure with programmable address.</description>
929 … <description>See corresponding field for PPU structure with programmable address.</description>
935 … <description>See corresponding field for PPU structure with programmable address.</description>
941 <description>See corresponding field for PPU structure with programmable address.
943 Note: this field is read-only. Its value is chip specific.</description>
949 … <description>See corresponding field for PPU structure with programmable address.</description>
955 … <description>See corresponding field for PPU structure with programmable address.</description>
963 <description>PPU region address 1 (master structure)</description>
972 <description>See corresponding field for PPU structure with programmable address.
976 Note: this field is read-only.</description>
982 <description>See corresponding field for PPU structure with programmable address.
986 Note: this field is read-only.</description>
994 <description>PPU region attributes 1 (master structure)</description>
1003 <description>See corresponding field for PPU structure with programmable address.
1005 Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.</description>
1011 … <description>See corresponding field for PPU structure with programmable address.</description>
1017 <description>See corresponding field for PPU structure with programmable address.
1019 Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.</description>
1025 <description>See corresponding field for PPU structure with programmable address.
1027 …that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.</description>
1033 … <description>See corresponding field for PPU structure with programmable address.</description>
1039 <description>See corresponding field for PPU structure with programmable address.
1041 …at this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.</description>
1047 … <description>See corresponding field for PPU structure with programmable address.</description>
1053 … <description>See corresponding field for PPU structure with programmable address.</description>
1059 … <description>See corresponding field for PPU structure with programmable address.</description>
1065 <description>See corresponding field for PPU structure with programmable address.
1067 '7': 256 B region</description>
1073 … <description>See corresponding field for PPU structure with programmable address.</description>
1079 … <description>See corresponding field for PPU structure with programmable address.</description>
1090 <description>CPU subsystem (CPUSS)</description>
1099 <description>GPIO Port Interrupt #0</description>
1104 <description>GPIO Port Interrupt #1</description>
1109 <description>GPIO Port Interrupt #2</description>
1114 <description>GPIO Port Interrupt #3</description>
1119 <description>GPIO Port Interrupt #4</description>
1124 <description>GPIO Port Interrupt #5</description>
1129 <description>GPIO Port Interrupt #6</description>
1134 <description>GPIO Port Interrupt #7</description>
1139 <description>GPIO Port Interrupt #8</description>
1144 <description>GPIO Port Interrupt #9</description>
1149 <description>GPIO Port Interrupt #10</description>
1154 <description>GPIO Port Interrupt #11</description>
1159 <description>GPIO Port Interrupt #12</description>
1164 <description>GPIO Port Interrupt #13</description>
1169 <description>GPIO Port Interrupt #14</description>
1174 <description>GPIO All Ports</description>
1179 <description>GPIO Supply Detect Interrupt</description>
1184 <description>Low Power Comparator Interrupt</description>
1189 <description>Serial Communication Block #8 (DeepSleep capable)</description>
1194 <description>Multi Counter Watchdog Timer interrupt</description>
1199 <description>Multi Counter Watchdog Timer interrupt</description>
1204 <description>Backup domain interrupt</description>
1209 <description>Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)</description>
1214 <description>CTBm Interrupt (all CTBms)</description>
1219 <description>Bluetooth Radio interrupt</description>
1224 <description>CPUSS Inter Process Communication Interrupt #0</description>
1229 <description>CPUSS Inter Process Communication Interrupt #1</description>
1234 <description>CPUSS Inter Process Communication Interrupt #2</description>
1239 <description>CPUSS Inter Process Communication Interrupt #3</description>
1244 <description>CPUSS Inter Process Communication Interrupt #4</description>
1249 <description>CPUSS Inter Process Communication Interrupt #5</description>
1254 <description>CPUSS Inter Process Communication Interrupt #6</description>
1259 <description>CPUSS Inter Process Communication Interrupt #7</description>
1264 <description>CPUSS Inter Process Communication Interrupt #8</description>
1269 <description>CPUSS Inter Process Communication Interrupt #9</description>
1274 <description>CPUSS Inter Process Communication Interrupt #10</description>
1279 <description>CPUSS Inter Process Communication Interrupt #11</description>
1284 <description>CPUSS Inter Process Communication Interrupt #12</description>
1289 <description>CPUSS Inter Process Communication Interrupt #13</description>
1294 <description>CPUSS Inter Process Communication Interrupt #14</description>
1299 <description>CPUSS Inter Process Communication Interrupt #15</description>
1304 <description>Serial Communication Block #0</description>
1309 <description>Serial Communication Block #1</description>
1314 <description>Serial Communication Block #2</description>
1319 <description>Serial Communication Block #3</description>
1324 <description>Serial Communication Block #4</description>
1329 <description>Serial Communication Block #5</description>
1334 <description>Serial Communication Block #6</description>
1339 <description>Serial Communication Block #7</description>
1344 <description>CSD (Capsense) interrupt</description>
1349 <description>CPUSS DataWire #0, Channel #0</description>
1354 <description>CPUSS DataWire #0, Channel #1</description>
1359 <description>CPUSS DataWire #0, Channel #2</description>
1364 <description>CPUSS DataWire #0, Channel #3</description>
1369 <description>CPUSS DataWire #0, Channel #4</description>
1374 <description>CPUSS DataWire #0, Channel #5</description>
1379 <description>CPUSS DataWire #0, Channel #6</description>
1384 <description>CPUSS DataWire #0, Channel #7</description>
1389 <description>CPUSS DataWire #0, Channel #8</description>
1394 <description>CPUSS DataWire #0, Channel #9</description>
1399 <description>CPUSS DataWire #0, Channel #10</description>
1404 <description>CPUSS DataWire #0, Channel #11</description>
1409 <description>CPUSS DataWire #0, Channel #12</description>
1414 <description>CPUSS DataWire #0, Channel #13</description>
1419 <description>CPUSS DataWire #0, Channel #14</description>
1424 <description>CPUSS DataWire #0, Channel #15</description>
1429 <description>CPUSS DataWire #1, Channel #0</description>
1434 <description>CPUSS DataWire #1, Channel #1</description>
1439 <description>CPUSS DataWire #1, Channel #2</description>
1444 <description>CPUSS DataWire #1, Channel #3</description>
1449 <description>CPUSS DataWire #1, Channel #4</description>
1454 <description>CPUSS DataWire #1, Channel #5</description>
1459 <description>CPUSS DataWire #1, Channel #6</description>
1464 <description>CPUSS DataWire #1, Channel #7</description>
1469 <description>CPUSS DataWire #1, Channel #8</description>
1474 <description>CPUSS DataWire #1, Channel #9</description>
1479 <description>CPUSS DataWire #1, Channel #10</description>
1484 <description>CPUSS DataWire #1, Channel #11</description>
1489 <description>CPUSS DataWire #1, Channel #12</description>
1494 <description>CPUSS DataWire #1, Channel #13</description>
1499 <description>CPUSS DataWire #1, Channel #14</description>
1504 <description>CPUSS DataWire #1, Channel #15</description>
1509 <description>CPUSS Fault Structure Interrupt #0</description>
1514 <description>CPUSS Fault Structure Interrupt #1</description>
1519 <description>CRYPTO Accelerator Interrupt</description>
1524 <description>FLASH Macro Interrupt</description>
1529 <description>CM0+ CTI #0</description>
1534 <description>CM0+ CTI #1</description>
1539 <description>CM4 CTI #0</description>
1544 <description>CM4 CTI #1</description>
1549 <description>TCPWM #0, Counter #0</description>
1554 <description>TCPWM #0, Counter #1</description>
1559 <description>TCPWM #0, Counter #2</description>
1564 <description>TCPWM #0, Counter #3</description>
1569 <description>TCPWM #0, Counter #4</description>
1574 <description>TCPWM #0, Counter #5</description>
1579 <description>TCPWM #0, Counter #6</description>
1584 <description>TCPWM #0, Counter #7</description>
1589 <description>TCPWM #1, Counter #0</description>
1594 <description>TCPWM #1, Counter #1</description>
1599 <description>TCPWM #1, Counter #2</description>
1604 <description>TCPWM #1, Counter #3</description>
1609 <description>TCPWM #1, Counter #4</description>
1614 <description>TCPWM #1, Counter #5</description>
1619 <description>TCPWM #1, Counter #6</description>
1624 <description>TCPWM #1, Counter #7</description>
1629 <description>TCPWM #1, Counter #8</description>
1634 <description>TCPWM #1, Counter #9</description>
1639 <description>TCPWM #1, Counter #10</description>
1644 <description>TCPWM #1, Counter #11</description>
1649 <description>TCPWM #1, Counter #12</description>
1654 <description>TCPWM #1, Counter #13</description>
1659 <description>TCPWM #1, Counter #14</description>
1664 <description>TCPWM #1, Counter #15</description>
1669 <description>TCPWM #1, Counter #16</description>
1674 <description>TCPWM #1, Counter #17</description>
1679 <description>TCPWM #1, Counter #18</description>
1684 <description>TCPWM #1, Counter #19</description>
1689 <description>TCPWM #1, Counter #20</description>
1694 <description>TCPWM #1, Counter #21</description>
1699 <description>TCPWM #1, Counter #22</description>
1704 <description>TCPWM #1, Counter #23</description>
1709 <description>UDB Interrupt #0</description>
1714 <description>UDB Interrupt #1</description>
1719 <description>UDB Interrupt #2</description>
1724 <description>UDB Interrupt #3</description>
1729 <description>UDB Interrupt #4</description>
1734 <description>UDB Interrupt #5</description>
1739 <description>UDB Interrupt #6</description>
1744 <description>UDB Interrupt #7</description>
1749 <description>UDB Interrupt #8</description>
1754 <description>UDB Interrupt #9</description>
1759 <description>UDB Interrupt #10</description>
1764 <description>UDB Interrupt #11</description>
1769 <description>UDB Interrupt #12</description>
1774 <description>UDB Interrupt #13</description>
1779 <description>UDB Interrupt #14</description>
1784 <description>UDB Interrupt #15</description>
1789 <description>SAR ADC interrupt</description>
1794 <description>I2S Audio interrupt</description>
1799 <description>PDM/PCM Audio interrupt</description>
1804 <description>Energy Profiler interrupt</description>
1809 <description>Serial Memory Interface interrupt</description>
1814 <description>USB Interrupt</description>
1819 <description>USB Interrupt</description>
1824 <description>USB Interrupt</description>
1829 <description>Consolidated interrrupt for all DACs</description>
1835 <description>CM0+ control</description>
1844 <description>Processor debug access control:
1848 …s useful to protect execution of code that needs to be protected from debug accesses.</description>
1854 <description>Processor enable:
1859 …er need to be written with a 0x05fa key value; see CPU user manual for more details).</description>
1865 <description>Register key (to prevent accidental writes).
1867 - Always reads as 0xfa05.</description>
1875 <description>CM0+ status</description>
1884 <description>Specifies if the CPU is in Active, Sleep or DeepSleep power mode:
1887 - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.</description>
1893 …<description>Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.</descri…
1901 <description>CM0+ clock control</description>
1910 …<description>Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow cl…
1912 …l be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
1918 …<description>Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the…
1922 …han Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'.</description>
1930 <description>CM0+ interrupt control 0</description>
1939 …description>System interrupt select for CPU interrupt source 0. If the field value is 240, no syst…
1945 <description>System interrupt select for CPU interrupt source 1.</description>
1951 <description>System interrupt select for CPU interrupt source 2.</description>
1957 <description>System interrupt select for CPU interrupt source 3.</description>
1965 <description>CM0+ interrupt control 1</description>
1974 <description>System interrupt select for CPU interrupt source 4.</description>
1980 <description>System interrupt select for CPU interrupt source 5.</description>
1986 <description>System interrupt select for CPU interrupt source 6.</description>
1992 <description>System interrupt select for CPU interrupt source 7.</description>
2000 <description>CM0+ interrupt control 2</description>
2009 <description>System interrupt select for CPU interrupt source 8.</description>
2015 <description>System interrupt select for CPU interrupt source 9.</description>
2021 <description>System interrupt select for CPU interrupt source 10.</description>
2027 <description>System interrupt select for CPU interrupt source 11.</description>
2035 <description>CM0+ interrupt control 3</description>
2044 <description>System interrupt select for CPU interrupt source 12.</description>
2050 <description>System interrupt select for CPU interrupt source 13.</description>
2056 <description>System interrupt select for CPU interrupt source 14.</description>
2062 <description>System interrupt select for CPU interrupt source 15.</description>
2070 <description>CM0+ interrupt control 4</description>
2079 <description>System interrupt select for CPU interrupt source 16.</description>
2085 <description>System interrupt select for CPU interrupt source 17.</description>
2091 <description>System interrupt select for CPU interrupt source 18.</description>
2097 <description>System interrupt select for CPU interrupt source 19.</description>
2105 <description>CM0+ interrupt control 5</description>
2114 <description>System interrupt select for CPU interrupt source 20.</description>
2120 <description>System interrupt select for CPU interrupt source 21.</description>
2126 <description>System interrupt select for CPU interrupt source 22.</description>
2132 <description>System interrupt select for CPU interrupt source 23.</description>
2140 <description>CM0+ interrupt control 6</description>
2149 <description>System interrupt select for CPU interrupt source 24.</description>
2155 <description>System interrupt select for CPU interrupt source 25.</description>
2161 <description>System interrupt select for CPU interrupt source 26.</description>
2167 <description>System interrupt select for CPU interrupt source 27.</description>
2175 <description>CM0+ interrupt control 7</description>
2184 <description>System interrupt select for CPU interrupt source 28.</description>
2190 <description>System interrupt select for CPU interrupt source 29.</description>
2196 <description>System interrupt select for CPU interrupt source 30.</description>
2202 <description>System interrupt select for CPU interrupt source 31.</description>
2210 <description>CM4 power control</description>
2219 <description>Set Power mode for CM4</description>
2225 <description>Switch CM4 off
2226 Power off, clock off, isolate, reset and no retain.</description>
2231 <description>Reset CM4
2234 …4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot.</description>
2239 <description>Put CM4 in Retained mode
2241 Power off, clock off, isolate, no reset and retain.</description>
2246 <description>Switch CM4 on.
2247 Power on, clock on, no isolate, no reset and no retain.</description>
2254 <description>Register key (to prevent accidental writes).
2256 - Always reads as 0xfa05.</description>
2264 <description>CM4 power control</description>
2273 … <description>Number clock cycles delay needed after power domain power up</description>
2281 <description>CM4 status</description>
2290 <description>Specifies if the CPU is in Active, Sleep or DeepSleep power mode:
2293 - DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.</description>
2299 …<description>Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.</descri…
2305 …<description>After a PWR_MODE change this flag indicates if the new power mode has taken effect or…
2306 Note: this flag can also change as a result of a change in debug power up req</description>
2314 <description>CM4 clock control</description>
2323 …<description>Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the perip…
2325 …l be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
2333 <description>CM4 NMI control</description>
2342 …description>System interrupt select for CPU NMI. The reset value ensure that the CPU NMI is NOT co…
2350 <description>RAM 0 control 0</description>
2359 …description>Memory wait states for the slow clock domain ('clk_slow'). The number of wait states i…
2365 …description>Memory wait states for the fast clock domain ('clk_fast'). The number of wait states i…
2375 <description>RAM 0 power control</description>
2384 <description>Set Power mode for 1 SRAM0 Macro</description>
2390 <description>See CM4_PWR_CTL</description>
2395 <description>undefined</description>
2400 <description>See CM4_PWR_CTL</description>
2405 <description>See CM4_PWR_CTL</description>
2412 <description>Register key (to prevent accidental writes).
2414 - Always reads as 0xfa05.</description>
2422 <description>RAM 1 control 0</description>
2431 …description>Memory wait states for the slow clock domain ('clk_slow'). The number of wait states i…
2437 …description>Memory wait states for the fast clock domain ('clk_fast'). The number of wait states i…
2445 <description>RAM1 power control</description>
2454 <description>Set Power mode for SRAM1</description>
2460 <description>See CM4_PWR_CTL</description>
2465 <description>undefined</description>
2470 <description>See CM4_PWR_CTL</description>
2475 <description>See CM4_PWR_CTL</description>
2482 <description>Register key (to prevent accidental writes).
2484 - Always reads as 0xfa05.</description>
2492 <description>RAM 2 control 0</description>
2501 …description>Memory wait states for the slow clock domain ('clk_slow'). The number of wait states i…
2507 …description>Memory wait states for the fast clock domain ('clk_fast'). The number of wait states i…
2515 <description>RAM2 power control</description>
2524 <description>Set Power mode for SRAM2</description>
2530 <description>See CM4_PWR_CTL</description>
2535 <description>undefined</description>
2540 <description>See CM4_PWR_CTL</description>
2545 <description>See CM4_PWR_CTL</description>
2552 <description>Register key (to prevent accidental writes).
2554 - Always reads as 0xfa05.</description>
2562 <description>Power up delay used for all SRAM power domains</description>
2571 … <description>Number clock cycles delay needed after power domain power up</description>
2579 <description>ROM control</description>
2588 …<description>Memory wait states for the slow clock domain ('clk_slow'). The number of wait states …
2590 …/formula will be provided for this field's values for different 'clk_hf' frequencies.</description>
2596 …description>Memory wait states for the fast clock domain ('clk_fast'). The number of wait states i…
2604 <description>UDB power control</description>
2613 <description>Set Power mode for UDBs</description>
2619 <description>See CM4_PWR_CTL</description>
2624 <description>See CM4_PWR_CTL</description>
2629 <description>See CM4_PWR_CTL</description>
2634 <description>See CM4_PWR_CTL</description>
2641 <description>Register key (to prevent accidental writes).
2643 - Always reads as 0xfa05.</description>
2651 <description>UDB power control</description>
2660 … <description>Number clock cycles delay needed after power domain power up</description>
2668 <description>Debug port status</description>
2677 … <description>Specifies if the SWJ debug port is connected; i.e. debug host interface is active:
2679 '1': Connected/active.</description>
2685 …<description>Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are…
2687 '1': Enabled.</description>
2693 …<description>Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.…
2695 '1': JTAG selected.</description>
2703 <description>Buffer control</description>
2712 … <description>Specifies if write transfer can be buffered in the bus infrastructure bridges:
2714 …sfer's bufferable attribute indicates that the transfer is a bufferable/posted write.</description>
2722 <description>DDFT control</description>
2731 <description>Select signal for CPUSS DDFT[0]
2753 21: mmio_ram0_ctl1_isolate_n[0] (Isolation control for SRAM0 macro0)</description>
2759 <description>Select signal for CPUSS DDFT[0]
2781 21: mmio_ram0_ctl1_isolate_n[0] (Isolation control for SRAM0 macro0)</description>
2789 <description>SysTick timer control</description>
2798 …description>Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a …
2804 <description>Specifies an external clock source:
2811 …provide the correct NOREF, SKEW and TENMS field values for the selected clock source.</description>
2817 …<description>Specifies the precision of the clock source and if the TENMS field represents exactly…
2819 '1': Imprecise.</description>
2825 <description>Specifies if an external clock source is provided:
2827 …T provided and only the CPU internal clock can be used as SysTick timer clock source.</description>
2835 <description>CM0+ vector table base</description>
2844 <description>Address of CM0+ vector table.
2846 Note: the CM0+ vector table is at an address that is a 256 B multiple.</description>
2854 <description>CM4 vector table base</description>
2863 <description>Address of CM4 vector table.
2865 Note: the CM4 vector table is at an address that is a 1024 B multiple.</description>
2873 <description>CM0+ protection context 0 handler</description>
2882 …description>Address of the protection context 0 handler. This field is used to detect entry to Cyp…
2890 <description>Identity</description>
2899 …<description>This field specifies the privileged setting ('0': user mode; '1': privileged mode) of…
2905 …<description>This field specifies the security setting ('0': secure mode; '1': non-secure mode) of…
2911 …<description>This field specifies the protection context of the transfer that reads the register.<…
2917 …<description>This field specifies the bus master identifier of the transfer that reads the registe…
2925 <description>Protection status</description>
2934 <description>Protection state:
2945 An attempt to make a NOT allowed state transition will NOT affect this register field.</description>
2953 <description>CM0+ NMI control</description>
2962 …description>System interrupt select for CPU NMI. The reset value ensures that the CPU NMI is NOT c…
2970 <description>Access port control</description>
2979 <description>Enables the CM0 AP interface:
2981 '1': Enabled.</description>
2987 <description>Enables the CM4 AP interface:
2989 '1': Enabled.</description>
2995 <description>Enables the system AP interface:
2997 '1': Enabled.</description>
3003 <description>Disables the CM0 AP interface:
3007 …eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'.</description>
3013 <description>Disables the CM4 AP interface:
3017 …eFUSE. The access port is only enabled when CM4_DISABLE is '0' and CM4_ENABLE is '1'.</description>
3023 <description>Disables the system AP interface:
3027 …eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'.</description>
3035 <description>Memory BIST status</description>
3044 …description>Flag indicating the BIST run is done. Note that after starting a BIST run this flag mu…
3050 <description>Report status of the BIST run, only valid if SFP_READY=1</description>
3058 <description>ROM trim control</description>
3067 <description>N/A</description>
3073 …description>Read-Write margin enable control. This selects between the default Read-Write margin s…
3081 <description>RAM trim control</description>
3090 <description>N/A</description>
3096 …description>Read-Write margin enable control. This selects between the default Read-Write margin s…
3102 …<description>Write Assist Pulse to control pulse width of negative voltage on SRAM bitline.</descr…
3108 <description>Read Assist control for WL under-drive.</description>
3114 <description>Write assist enable control (Active High).
3115 - WA[1:0] Write Assist pins to control negative voltage on SRAM bitline.</description>
3125 <description>Fault structures</description>
3137 <description>Fault structure</description>
3141 <description>Fault control</description>
3150 <description>Trigger output enable:
3152 … to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3).</description>
3158 <description>IO output signal enable:
3160 …'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'.</description>
3166 <description>Reset request enable:
3170 …structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal.</description>
3178 <description>Fault status</description>
3187 …<description>The fault source index for which fault information is captured in DATA0 through DATA3…
3189 …urce data in DATA0 through DATA3) should only be considered valid, when VALID is '1'.</description>
3195 <description>Valid indication:
3197 … when VALID is '0'. SW can clear this field to '0' when the fault is handled (by SW).</description>
3207 <description>Fault data</description>
3216 <description>Captured fault source data.
3218 Note: the fault source index STATUS.IDX specifies the format of the DATA registers.</description>
3226 <description>Fault pending 0</description>
3235 <description>This field specifies the following sources:
3249 Bit 31: Peripheral master interface 3 PPU.</description>
3257 <description>Fault pending 1</description>
3266 <description>This field specifies the following sources:
3278 Bit 18: Flash controller, main interface, bus error.</description>
3286 <description>Fault pending 2</description>
3295 <description>This field specifies the following sources:
3296 Bit 0 - 31: TBD.</description>
3304 <description>Fault mask 0</description>
3313 <description>Fault source enables:
3314 Bits 31-0: Fault sources 31 to 0.</description>
3322 <description>Fault mask 1</description>
3331 <description>Fault source enables:
3332 Bits 31-0: Fault sources 63 to 32.</description>
3340 <description>Fault mask 2</description>
3349 <description>Fault source enables:
3350 Bits 31-0: Fault sources 95 to 64.</description>
3358 <description>Interrupt</description>
3367 …<description>This interrupt cause field is activated (HW sets the field to '1') when an enabled (M…
3372 SW writes a '1' to these field to clear the interrupt cause to '0'.</description>
3380 <description>Interrupt set</description>
3389 …<description>SW writes a '1' to this field to set the corresponding field in the INTR register.</d…
3397 <description>Interrupt mask</description>
3406 <description>Mask bit for corresponding field in the INTR register.</description>
3414 <description>Interrupt masked</description>
3423 <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
3434 <description>IPC</description>
3446 <description>IPC structure</description>
3450 <description>IPC acquire</description>
3459 <description>User/privileged access control:
3463 …the user/privileged access control of the access that successfully acquired the lock.</description>
3469 <description>Secure/on-secure access control:
3473 …e secure/non-secure access control of the access that successfully acquired the lock.</description>
3479 …<description>This field specifies the protection context that successfully acquired the lock.</des…
3485 …<description>This field specifies the bus master identifier that successfully acquired the lock.</…
3491 …<description>Specifies if the lock is successfully acquired or not (reading the ACQUIRE register c…
3495 …ased by writing to the associated RELEASE register (irrespective of the write value).</description>
3503 <description>IPC release</description>
3512 …<description>This field allows for the generation of release events to the IPC interrupt structure…
3516 …UIRED to '0' (even when no release event is generated; i.e. the written data is '0').</description>
3524 <description>IPC notification</description>
3533 …<description>This field allows for the generation of notification events to the IPC interrupt stru…
3535 …nt. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
3543 <description>IPC data</description>
3552 …<description>This field holds a 32-bit data element that is associated with the IPC structure.</de…
3560 <description>IPC lock status</description>
3569 <description>This field specifies the user/privileged access control:
3571 '1': privileged mode.</description>
3577 <description>This field specifies the cecure/on-secure access control:
3579 '1': non-secure.</description>
3585 …<description>This field specifies the protection context that successfully acquired the lock.</des…
3591 …<description>This field specifies the bus master identifier that successfully acquired the lock.</…
3597 …description>Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfe…
3608 <description>IPC interrupt structure</description>
3612 <description>Interrupt</description>
3621 …description>These interrupt cause fields are activated (HW sets the field to '1') when a IPC relea…
3627 …description>These interrupt cause fields are activated (HW sets the field to '1') when a IPC notif…
3635 <description>Interrupt set</description>
3644 …<description>SW writes a '1' to this field to set the corresponding field in the INTR register.</d…
3650 …<description>SW writes a '1' to this field to set the corresponding field in the INTR register.</d…
3658 <description>Interrupt mask</description>
3667 <description>Mask bit for corresponding field in the INTR register.</description>
3673 <description>Mask bit for corresponding field in the INTR register.</description>
3681 <description>Interrupt masked</description>
3690 <description>Logical and of corresponding request and mask bits.</description>
3696 <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
3707 <description>Protection</description>
3717 <description>SMPU</description>
3721 <description>Master 0 protection context control</description>
3730 <description>Privileged setting ('0': user mode; '1': privileged mode).
3734 The default/reset field value provides privileged mode access capabilities.</description>
3740 <description>Security setting ('0': secure mode; '1': non-secure mode).
3744 …efault/reset field value provides non-secure mode access capabilities to all masters.</description>
3750 …<description>Device wide bus arbitration priority setting ('0': highest priority, '3': lowest prio…
3755 … a 'priority group'. Within a 'priority group', round robin arbitration is performed.</description>
3761 … <description>Protection context mask for protection context '0'. This field is a constant '0':
3762 …t of the write transfer is '0', protection is not applied and PC[3:0] can be changed.</description>
3768 …<description>Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1…
3772 … possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]).</description>
3780 <description>Master 1 protection context control</description>
3789 <description>See MS0_CTL.P.</description>
3795 <description>See MS0_CTL.NS.</description>
3801 <description>See MS0_CTL.PRIO</description>
3807 <description>See MS0_CTL.PC_MASK_0.</description>
3813 <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
3821 <description>Master 2 protection context control</description>
3830 <description>See MS0_CTL.P.</description>
3836 <description>See MS0_CTL.NS.</description>
3842 <description>See MS0_CTL.PRIO</description>
3848 <description>See MS0_CTL.PC_MASK_0.</description>
3854 <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
3862 <description>Master 3 protection context control</description>
3871 <description>See MS0_CTL.P.</description>
3877 <description>See MS0_CTL.NS.</description>
3883 <description>See MS0_CTL.PRIO</description>
3889 <description>See MS0_CTL.PC_MASK_0.</description>
3895 <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
3903 <description>Master 4 protection context control</description>
3912 <description>See MS0_CTL.P.</description>
3918 <description>See MS0_CTL.NS.</description>
3924 <description>See MS0_CTL.PRIO</description>
3930 <description>See MS0_CTL.PC_MASK_0.</description>
3936 <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
3944 <description>Master 5 protection context control</description>
3953 <description>See MS0_CTL.P.</description>
3959 <description>See MS0_CTL.NS.</description>
3965 <description>See MS0_CTL.PRIO</description>
3971 <description>See MS0_CTL.PC_MASK_0.</description>
3977 <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
3985 <description>Master 6 protection context control</description>
3994 <description>See MS0_CTL.P.</description>
4000 <description>See MS0_CTL.NS.</description>
4006 <description>See MS0_CTL.PRIO</description>
4012 <description>See MS0_CTL.PC_MASK_0.</description>
4018 <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
4026 <description>Master 7 protection context control</description>
4035 <description>See MS0_CTL.P.</description>
4041 <description>See MS0_CTL.NS.</description>
4047 <description>See MS0_CTL.PRIO</description>
4053 <description>See MS0_CTL.PC_MASK_0.</description>
4059 <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
4067 <description>Master 8 protection context control</description>
4076 <description>See MS0_CTL.P.</description>
4082 <description>See MS0_CTL.NS.</description>
4088 <description>See MS0_CTL.PRIO</description>
4094 <description>See MS0_CTL.PC_MASK_0.</description>
4100 <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
4108 <description>Master 9 protection context control</description>
4117 <description>See MS0_CTL.P.</description>
4123 <description>See MS0_CTL.NS.</description>
4129 <description>See MS0_CTL.PRIO</description>
4135 <description>See MS0_CTL.PC_MASK_0.</description>
4141 <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
4149 <description>Master 10 protection context control</description>
4158 <description>See MS0_CTL.P.</description>
4164 <description>See MS0_CTL.NS.</description>
4170 <description>See MS0_CTL.PRIO</description>
4176 <description>See MS0_CTL.PC_MASK_0.</description>
4182 <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
4190 <description>Master 11 protection context control</description>
4199 <description>See MS0_CTL.P.</description>
4205 <description>See MS0_CTL.NS.</description>
4211 <description>See MS0_CTL.PRIO</description>
4217 <description>See MS0_CTL.PC_MASK_0.</description>
4223 <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
4231 <description>Master 12 protection context control</description>
4240 <description>See MS0_CTL.P.</description>
4246 <description>See MS0_CTL.NS.</description>
4252 <description>See MS0_CTL.PRIO</description>
4258 <description>See MS0_CTL.PC_MASK_0.</description>
4264 <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
4272 <description>Master 13 protection context control</description>
4281 <description>See MS0_CTL.P.</description>
4287 <description>See MS0_CTL.NS.</description>
4293 <description>See MS0_CTL.PRIO</description>
4299 <description>See MS0_CTL.PC_MASK_0.</description>
4305 <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
4313 <description>Master 14 protection context control</description>
4322 <description>See MS0_CTL.P.</description>
4328 <description>See MS0_CTL.NS.</description>
4334 <description>See MS0_CTL.PRIO</description>
4340 <description>See MS0_CTL.PC_MASK_0.</description>
4346 <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
4354 <description>Master 15 protection context control</description>
4363 <description>See MS0_CTL.P.</description>
4369 <description>See MS0_CTL.NS.</description>
4375 <description>See MS0_CTL.PRIO</description>
4381 <description>See MS0_CTL.PC_MASK_0.</description>
4387 <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
4397 <description>SMPU structure</description>
4401 <description>SMPU region address 0 (slave structure)</description>
4410 …<description>This field is used to individually disabled the eight equally sized subregions in whi…
4419 … Note that the smallest region size is 256 B and the smallest subregion size is 32 B.</description>
4425 …description>This field specifies the most significant bits of the 32-bit address of an address reg…
4433 <description>SMPU region attributes 0 (slave structure)</description>
4442 <description>User read enable:
4444 '1': Enabled (user, read accesses are allowed).</description>
4450 <description>User write enable:
4452 '1': Enabled (user, write accesses are allowed).</description>
4458 <description>User execute enable:
4460 '1': Enabled (user, execute accesses are allowed).</description>
4466 <description>Privileged read enable:
4468 '1': Enabled (privileged, read accesses are allowed).</description>
4474 <description>Privileged write enable:
4476 '1': Enabled (privileged, write accesses are allowed).</description>
4482 <description>Privileged execute enable:
4484 '1': Enabled (privileged, execute accesses are allowed).</description>
4490 <description>Non-secure:
4492 '1': Non-secure (both secure and non-secure accesses allowed).</description>
4498 …<description>This field specifies protection context identifier based access control for protectio…
4504 … <description>This field specifies protection context identifier based access control.
4505 …ed; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.</description>
4511 <description>This field specifies the region size:
4537 '31': 4 GB region</description>
4543 …<description>This field specifies if the PC field participates in the 'matching' process or the 'a…
4550 … multiple protection structures with the same address region and PC_MATCH set to '1'.</description>
4556 <description>Region enable:
4560 … a disabled address region performs logic gating to reduce dynamic power consumption.</description>
4568 <description>SMPU region address 1 (master structure)</description>
4577 …<description>This field is used to individually disabled the eight equally sized subregions in whi…
4589 Note: this field is read-only.</description>
4595 …<description>This field specifies the most significant bits of the 32-bit address of an address re…
4599 Note: this field is read-only.</description>
4607 <description>SMPU region attributes 1 (master structure)</description>
4616 <description>User read enable:
4620 Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.</description>
4626 <description>User write enable:
4628 '1': Enabled (user, write accesses are allowed).</description>
4634 <description>User execute enable:
4638 Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.</description>
4644 <description>Privileged read enable:
4648 …that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.</description>
4654 <description>Privileged write enable:
4656 '1': Enabled (privileged, write accesses are allowed).</description>
4662 <description>Privileged execute enable:
4666 …at this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.</description>
4672 <description>Non-secure:
4674 '1': Non-secure (both secure and non-secure accesses allowed).</description>
4680 …<description>This field specifies protection context identifier based access control for protectio…
4686 … <description>This field specifies protection context identifier based access control.
4687 …ed; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.</description>
4693 <description>This field specifies the region size:
4696 Note: this field is read-only.</description>
4702 …<description>This field specifies if the PC field participates in the 'matching' process or the 'a…
4709 … multiple protection structures with the same address region and PC_MATCH set to '1'.</description>
4715 <description>Region enable:
4717 '1': Enabled.</description>
4729 <description>MPU</description>
4733 <description>Master control</description>
4742 <description>N/A</description>
4748 …description>Saved protection context. Modifications to this field are constrained by the associat…
4758 <description>Master control read mirror</description>
4767 <description>Read-only mirror of MS_CTL.PC</description>
4773 <description>Read-only mirror of MS_CTL.PC_SAVED</description>
4783 <description>MPU structure</description>
4787 <description>MPU region address</description>
4796 …<description>This field is used to individually disabled the eight equally sized subregions in whi…
4805 … Note that the smallest region size is 256 B and the smallest subregion size is 32 B.</description>
4811 …description>This field specifies the most significant bits of the 32-bit address of an address reg…
4819 <description>MPU region attrributes</description>
4828 <description>User read enable:
4830 '1': Enabled (user, read accesses are allowed).</description>
4836 <description>User write enable:
4838 '1': Enabled (user, write accesses are allowed).</description>
4844 <description>User execute enable:
4846 '1': Enabled (user, execute accesses are allowed).</description>
4852 <description>Privileged read enable:
4854 '1': Enabled (privileged, read accesses are allowed).</description>
4860 <description>Privileged write enable:
4862 '1': Enabled (privileged, write accesses are allowed).</description>
4868 <description>Privileged execute enable:
4870 '1': Enabled (privileged, execute accesses are allowed).</description>
4876 <description>Non-secure:
4878 '1': Non-secure (both secure and non-secure accesses allowed).</description>
4884 <description>This field specifies the region size:
4910 '31': 4 GB region</description>
4916 <description>Region enable:
4920 … a disabled address region performs logic gating to reduce dynamic power consumption.</description>
4932 <description>Flash controller</description>
4942 <description>Control</description>
4951 <description>FLASH macro main interface wait states:
4954 15: 15 wait states</description>
4960 <description>Specifies remapping of FLASH macro main region.
4977 Note: when the REMAP is changed, SW should invalidate the caches and buffers.</description>
4985 <description>Flash power control</description>
4994 <description>Controls 'enable' pin of the Flash memory.</description>
5000 <description>Controls 'enable_hv' pin of the Flash memory.</description>
5008 <description>Command</description>
5017 …description>FLASH cache and buffer invalidation for ALL cache and buffers. SW writes a '1' to clea…
5025 <description>BIST control</description>
5034 …<description>This field specifies how the data check should be performed after reading the data fr…
5037 … is BIST_DATA, fourth read expected data is binary compliment of BIST_DATA and so on.</description>
5043 <description>Specifies direction in which Flash BIST steps through addresses:
5045 …T_ADDR_START when ADDR_START_ENABLED is '1'' to the maximum row and column addresses.</description>
5051 <description>Specifies how the Flash BIST addresses are generated:
5053 …ts minimum/maximum value and only then is the column address incremented/decremented.</description>
5059 <description>Specifies Flash BIST start addresses:
5063 …rements both row address and column address (BIST_CTL.INCR_DECR_BOTH) for every read.</description>
5069 <description>Specifies to generate address compliment patterns.
5079 ...</description>
5085 …<description>Specifies to generate patterns where both column address and row address are incremen…
5098 ...</description>
5104 …<description>Specifies the BIST to continue indefinitely, regardless of occurrence of errors or no…
5106 1: BIST controller stops on when the first data failure is encountered.</description>
5114 <description>BIST command</description>
5123 …<description>1: Start FLASH BIST. Hardware set this field to '0' when BIST is completed.</descript…
5131 <description>BIST address start register</description>
5140 …description>Column start address. Useful to apply BIST to a part of an Flash. The value of this fi…
5146 …description>Row start address. Useful to apply BIST to a part of an Flash. The value of this fiel…
5156 <description>BIST data register(s)</description>
5165 <description>BIST data register to store the expected value for data comparison.
5166 …r a 128-bit Flash memory, there will be 4 BIST_DATA registers to store 128-bit value.</description>
5176 <description>BIST data actual register(s)</description>
5185 …<description>This field specified the actual Flash data output that caused the BIST failure.</desc…
5195 <description>BIST data expected register(s)</description>
5204 <description>This field specified the expected Flash data output.</description>
5212 <description>BIST address register</description>
5221 <description>Current column address.</description>
5227 <description>Current row address.</description>
5235 <description>BIST status register</description>
5244 <description>0: BIST passed.
5245 1: BIST failed.</description>
5253 <description>CM0+ cache control</description>
5262 …<description>Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2…
5268 …<description>Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2…
5274 <description>Prefetch enable:
5278 Prefetching requires the cache to be enabled; i.e. ENABLED is '1'.</description>
5284 <description>Cache enable:
5286 1: Enabled.</description>
5294 <description>CM0+ cache control</description>
5303 <description>Set Power mode for CM0 cache</description>
5309 <description>See CM4_PWR_CTL</description>
5314 <description>undefined</description>
5319 <description>See CM4_PWR_CTL</description>
5324 <description>See CM4_PWR_CTL</description>
5331 <description>Register key (to prevent accidental writes).
5333 - Always reads as 0xfa05.</description>
5341 <description>CM0+ cache control</description>
5350 … <description>Number clock cycles delay needed after power domain power up</description>
5358 <description>CM0+ cache command</description>
5367 …description>FLASH cache invalidation. SW writes a '1' to clear the cache. W sets this field to '0'…
5375 <description>CM0+ cache status 0</description>
5384 …<description>Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_A…
5392 <description>CM0+ cache status 1</description>
5401 …<description>Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_A…
5409 <description>CM0+ cache status 2</description>
5418 …<description>Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The enc…
5424 Bit 0: 2_LRU_3.</description>
5432 <description>CM4 cache control</description>
5441 <description>See CM0_CA_CTL.</description>
5447 <description>See CM0_CA_CTL.</description>
5453 <description>See CM0_CA_CTL.</description>
5459 <description>See CM0_CA_CTL.</description>
5467 <description>CM4 cache control</description>
5476 <description>Set Power mode for CM4 cache</description>
5482 <description>See CM4_PWR_CTL</description>
5487 <description>undefined</description>
5492 <description>See CM4_PWR_CTL</description>
5497 <description>See CM4_PWR_CTL</description>
5504 <description>Register key (to prevent accidental writes).
5506 - Always reads as 0xfa05.</description>
5514 <description>CM4 cache control</description>
5523 … <description>Number clock cycles delay needed after power domain power up</description>
5531 <description>CM4 cache command</description>
5540 <description>See CM0_CA_CMD.</description>
5548 <description>CM4 cache status 0</description>
5557 <description>See CM0_CA_STATUS0.</description>
5565 <description>CM4 cache status 1</description>
5574 <description>See CM0_CA_STATUS1.</description>
5582 <description>CM4 cache status 2</description>
5591 <description>See CM0_CA_STATUS2.</description>
5599 <description>Cryptography buffer control</description>
5608 <description>Prefetch enable:
5612 Prefetching requires the buffer to be enabled; i.e. ENABLED is '1'.</description>
5618 <description>Cache enable:
5620 1: Enabled.</description>
5628 <description>Cryptography buffer command</description>
5637 …<description>FLASH buffer invalidation. SW writes a '1' to clear the buffer. HW sets this field to…
5645 <description>Datawire 0 buffer control</description>
5654 <description>See CRYPTO_BUFF_CTL.</description>
5660 <description>See CRYPTO_BUFF_CTL.</description>
5668 <description>Datawire 0 buffer command</description>
5677 <description>See CRYPTO_BUFF_CMD.</description>
5685 <description>Datawire 1 buffer control</description>
5694 <description>See CRYPTO_BUFF_CTL.</description>
5700 <description>See CRYPTO_BUFF_CTL.</description>
5708 <description>Datawire 1 buffer command</description>
5717 <description>See CRYPTO_BUFF_CMD.</description>
5725 <description>Debug access port buffer control</description>
5734 <description>See CRYPTO_BUFF_CTL.</description>
5740 <description>See CRYPTO_BUFF_CTL.</description>
5748 <description>Debug access port buffer command</description>
5757 <description>See CRYPTO_BUFF_CMD.</description>
5765 <description>External master 0 buffer control</description>
5774 <description>See CRYPTO_BUFF_CTL.</description>
5780 <description>See CRYPTO_BUFF_CTL.</description>
5788 <description>External master 0 buffer command</description>
5797 <description>See CRYPTO_BUFF_CMD.</description>
5805 <description>External master 1 buffer control</description>
5814 <description>See CRYPTO_BUFF_CTL.</description>
5820 <description>See CRYPTO_BUFF_CTL.</description>
5828 <description>External master 1 buffer command</description>
5837 <description>See CRYPTO_BUFF_CMD.</description>
5845 <description>Flash Macro Registers</description>
5849 <description>Flash macro control</description>
5858 <description>Flash macro mode selection:
5863 '15': TBD</description>
5869 <description>Flash macro sequence select:
5873 '3': TBD</description>
5879 <description>Direct memory cell access address.</description>
5885 …<description>Interface selection. Specifies the interface that is used for flash memory read opera…
5887 …(the page address) and by the C interface access offset in the FM_MEM_DATA structure.</description>
5893 <description>'0': normal mode
5894 '1': Fm Write Enable</description>
5902 <description>Status</description>
5911 <description>Indicates if the high voltage timer is running:
5913 '1': running</description>
5919 … <description>Indicates the isolation status at HV trim and redundancy registers inputs
5921 '1' - isolated writing disabled</description>
5927 <description>Indicates a bulk, sector erase, program has been requested when axa=1
5929 '1' - illegal HV operation error</description>
5935 …<description>After FM power up indicates the analog blocks currents are boosted to faster reach th…
5938 '1' - normal mode</description>
5944 <description>FM_CTL.WR_EN bit after being synchronized in clk_r domain</description>
5950 … <description>FM_CTL.IF_SEL bit after being synchronized in clk_r domain</description>
5958 <description>Flash macro address</description>
5967 <description>Row address.</description>
5973 <description>Bank address.</description>
5979 <description>Auxiliary address field:
5981 '1': supervisory flash memory.</description>
5989 <description>Regular flash geometry</description>
5998 …<description>Number of Bytes per word (log 2). A word is defined as the data that is read from the…
6005 …, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively.</description>
6011 <description>Number of Bytes per page (log 2):
6018 …r 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively.</description>
6024 <description>Number of rows (minus 1):
6029 '65535': 65536 rows</description>
6035 <description>Number of banks (minus 1):
6039 '255': 256 banks</description>
6047 <description>Supervisory flash geometry</description>
6056 …<description>Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_L…
6062 …<description>Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_L…
6068 …<description>Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT</descri…
6074 …<description>Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT.</descr…
6082 <description>Timer control</description>
6091 …<description>Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is…
6097 <description>Timer tick scale:
6099 '1': 100 microseconds.</description>
6105 <description>Pump clock select:
6107 '1': external clock.</description>
6113 <description>'1' during pre-program operation</description>
6119 <description>'0' CSL lines driven by CSL_DAC
6120 '1' CSL lines driven by VNEG_G</description>
6126 <description>Pump enable:
6130 HW clears this field when timer is expired.</description>
6136 <description>ACLK enable (generates a single cycle pulse for the FM):
6138 …generate a single cycle pulse. HW sets this field to '0' when the pulse is generated.</description>
6144 <description>Timer enable:
6146 …field to '1' to start the timer. HW sets this field to '0' when the timer is expired.</description>
6154 <description>Analog control 0</description>
6163 <description>Trimming of common source line DAC.</description>
6169 <description>Vcc select:
6172 …iler has a configuration option that specifies the default/reset value of this field.</description>
6178 <description>Flips amuxbusa and amuxbusb
6180 '1': amuxbusb, amuxbusb</description>
6188 <description>Analog control 1</description>
6197 … <description>Trimming of the output margin Voltage as a function of Vpos and Vneg.</description>
6203 <description>Trimming of positive pump output Voltage:</description>
6209 <description>Trimming of negative pump output Voltage:</description>
6215 <description>'0': vprot = BG.vprot.
6216 '1': vprot = vcc</description>
6222 <description>r_grant control:
6224 '1': forces r_grant LO synchronized on clk_r</description>
6230 <description>'1': Page Latches Soft Reset</description>
6238 <description>N/A, DNU</description>
6247 <description>N/A</description>
6253 <description>N/A</description>
6259 <description>N/A</description>
6267 <description>Test mode control</description>
6276 <description>Test mode control:
6277 '0'-'31': TBD</description>
6283 <description>Positive/negative margin mode control:
6285 '1': positive margin control</description>
6291 <description>PUMP_EN override: Pump Enable =PUMP_EN | PE_TM</description>
6297 <description>Test mode positive pump disable</description>
6303 <description>Test mode negative pump disable</description>
6309 <description>1: enables the oscillator output monitor</description>
6315 <description>Engineering Debug Register</description>
6321 … <description>0': the oscillator enable logic has control over the internal oscillator
6322 '1': forces oscillator enable HI</description>
6328 <description>See BSN-242 memo
6330 '1': disables the Word Address scrambling</description>
6338 <description>Wiat State control</description>
6347 …<description>Number of C interface wait cycles (on 'clk_c') for a read from the memory</descriptio…
6353 …<description>Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page …
6354 Common for reading HV Page Latches and the DATA_COMP_RESULT bit</description>
6360 …<description>Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page l…
6368 <description>Monitor Status</description>
6377 <description>POS pump VLO</description>
6383 <description>NEG pump VHI</description>
6391 <description>Scratch Control</description>
6400 <description>Scratchpad register fields. Provided for test purposes.</description>
6408 <description>High voltage control</description>
6417 …description>Specifies the frequency in MHz of the timer clock 'clk_t' as provide to the flash macr…
6425 <description>Aclk control</description>
6434 …<description>A write to this register generates a ACLK pulse for the flash macro (also requires FM…
6442 <description>Interrupt</description>
6451 …<description>Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write IN…
6459 <description>Interrupt set</description>
6468 …<description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no …
6476 <description>Interrupt mask</description>
6485 <description>Mask for corresponding field in INTR register.</description>
6493 <description>Interrupt masked</description>
6502 <description>Logical and of corresponding request and mask fields.</description>
6510 … <description>Flash macro high Voltage page latches data (for all page latches)</description>
6519 …<description>Write all high Voltage page latches with the same 32-bit data in a single write cycle…
6527 <description>Cal control BG LO trim bits</description>
6536 <description>LO Bandgap Voltage Temperature Compensation trim control.</description>
6542 … <description>LO Temperature compensated trim DAC. To control Vcstat slope for Vpos.</description>
6548 <description>LO Bandgap Voltage trim control.</description>
6554 <description>LO Bandgap Voltage Temperature Compensation trim control</description>
6560 <description>LO Bandgap IPTAT trim control.</description>
6568 <description>Cal control BG HI trim bits</description>
6577 <description>HI Bandgap Voltage Temperature Compensation trim control.</description>
6583 … <description>HI Temperature compensated trim DAC. To control Vcstat slope for Vpos.</description>
6589 <description>HI Bandgap Voltage trim control.</description>
6595 <description>HI Bandgap Voltage Temperature Compensation trim control.</description>
6601 <description>HI Bandgap IPTAT trim control.</description>
6609 … <description>Cal control BG LO&HI ipref trim, ref sel, fm_active, turbo_ext</description>
6618 <description>LO Bandgap Current trim control.</description>
6624 <description>LO Bandgap Current Temperature Compensation trim control</description>
6630 <description>HI Bandgap Current trim control.</description>
6636 <description>HI Bandgap Current Temperature Compensation trim control.</description>
6642 <description>Voltage reference:
6644 '1': external voltage reference</description>
6650 <description>Current reference:
6652 '1': external current reference</description>
6658 <description>0: No Action
6659 1: Forces FM SYS in active mode</description>
6665 <description>0: turbo signal generated internally
6666 1: turbo cleared by clk_pump_ext HI</description>
6674 <description>Cal control osc trim bits, idac, sdac, itim, bdac.</description>
6683 <description>Flash macro pump clock trim control.</description>
6689 <description>0: Oscillator High Frequency Range
6690 1: Oscillator Low Frequency range</description>
6696 <description>N/A</description>
6702 <description>N/A</description>
6708 <description>Trimming of timing current</description>
6714 <description>0': vdd<2.3V
6715 '1': vdd>=2.3V</description>
6721 <description>Turbo pulse width trim</description>
6727 <description>LO Bandgap Enable</description>
6733 <description>HI Bandgap Enable</description>
6741 <description>Bookmark register - keeps the current FW HV seq</description>
6750 <description>Used by FW. Keeps the Current HV cycle sequence</description>
6758 <description>Redundancy Control normal sectors 0,1</description>
6767 <description>Bad Row Pair Address for Sector 0</description>
6773 <description>'1': Redundancy Enable for Sector 0</description>
6779 <description>Bad Row Pair Address for Sector 1</description>
6785 <description>'1': Redundancy Enable for Sector 1</description>
6793 <description>Redundancy Controll normal sectors 2,3</description>
6802 <description>Bad Row Pair Address for Sector 2</description>
6808 <description>1': Redundancy Enable for Sector 2</description>
6814 <description>Bad Row Pair Address for Sector 3</description>
6820 <description>1': Redundancy Enable for Sector 3</description>
6828 <description>Redundancy Controll normal sectors 4,5</description>
6837 <description>Not Used</description>
6843 <description>Forces the VBST regulator in active mode all the time</description>
6849 <description>Not Used</description>
6855 <description>'2b00' F = 1MHz see fdiv_trim_hv<1> value as well
6858 '2b11' F = 4Mhz</description>
6864 <description>Not Used</description>
6870 <description>'2b00' F = 1MHz see fdiv_trim_hv<0> value as well
6873 '2b11' F = 4Mhz</description>
6879 <description>Not Used</description>
6885 <description>'2b00' V2 = 650mV see vlim_trim_hv<1> value as well
6888 '2b11' V2 = 700mV</description>
6894 <description>Not Used</description>
6900 <description>Not Used</description>
6908 <description>Redundancy Controll normal sectors 6,7</description>
6917 <description>'2b00' V2 = 650mV see vlim_trim_hv<0> value as well
6920 '2b11' V2 = 700mV</description>
6926 <description>Not Used</description>
6932 <description>Forces VPROT in active mode all the time</description>
6938 <description>Not Used</description>
6944 …<description>Reduces the IPREF Tempco by not subtracting ICREF form IPREF - IPREF will be 1uA</des…
6950 <description>Not Used</description>
6956 <description>Adds 200-300nA boost on IPREF_HI</description>
6962 <description>Not Used</description>
6968 <description>Adds 200-300nA boost on IPREF_LO</description>
6974 <description>Not Used</description>
6982 <description>Redundancy Controll special sectors 0,1</description>
6991 <description>Bad Row Pair Address for Special Sector 0</description>
6997 <description>Redundancy Enable for Special Sector 0</description>
7003 <description>Bad Row Pair Address for Special Sector 1</description>
7009 <description>Redundancy Enable for Special Sector 1</description>
7015 <description>Sense Amp Control tracking delay</description>
7021 <description>'0': r_grant handshake disabled, r_grant always 1.
7022 '1': r_grand handshake enabled</description>
7032 <description>Do Not Use</description>
7041 …<description>The result of a comparison between the flash macro data output and the content of the…
7046 '1': TRUE (equal)</description>
7056 <description>Flash macro high Voltage page latches data</description>
7065 …<description>Four page latch Bytes (when writing to the page latches, it also requires FM_CTL.IF_S…
7067 Note: the high Voltage page latches are readable for test mode functionality.</description>
7077 <description>Flash macro memory sense amplifier and column decoder data</description>
7086 …<description>Sense amplifier and column multiplexer structure Bytes. The read data is dependent on…
7088 …data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.</description>
7099 <description>SRSS Core Registers</description>
7109 <description>Power Mode Control</description>
7118 …<description>Current power mode of the device. Note that this field cannot be read in all power m…
7124 <description>System is resetting.</description>
7129 <description>At least one CPU is running.</description>
7134 <description>No CPUs are running. Peripherals may be running.</description>
7139 …<description>Main high-frequency clock is off; low speed clocks are available. Communication inte…
7146 … <description>Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)</description>
7152 <description>No debug session active</description>
7157 …<description>Debug session is active. Power modes behave differently to keep the debug session ac…
7164 …<description>Indicates whether certain low power functions are ready. The low current circuits ta…
7166 …operation. DEEPSLEEP and low power circuits operate as requested in other registers.</description>
7172 …<description>Control the power mode of the reference current generator. The value in this registe…
7174 …time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less.</description>
7180 …description>Indicates that the voltage reference buffer is ready. Due to synchronization delays, …
7186 …<description>Disable the DeepSleep regulator. This is only legal when the on-chip buck regulator …
7188 1: DeepSleep Regulator is off.</description>
7194 …<description>Disable the Retention regulator. This is only legal when the on-chip buck regulator …
7196 1: Retention Regulator is off.</description>
7202 …<description>Disable the Nwell regulator. This is only legal when the on-chip buck regulator supp…
7204 1: Nwell Regulator is off.</description>
7210 …<description>Disable the linear Core Regulator. This is only legal when the on-chip buck regulato…
7212 1: Linear regulator is off.</description>
7218 …<description>Control the power mode of the Linear Regulator. The value in this register is ignore…
7220 …rrent capability is 25mA. Firmware must ensure the current is kept within the limit.</description>
7226 …<description>Control the power mode of the POR/BOD circuits. The value in this register is ignore…
7228 …ime is reduced to save current, and they work for vddd ramp rates of 10mV/us or less.</description>
7234 …<description>Control the power mode of the Bandgap Voltage and Current References. This applies t…
7236 … rates of 10mV/us or less. The Active Reference may be disabled using ACT_REF_DIS=0.</description>
7242 <description>Bypass level shifter inside the PLL.
7244 …d to 1.1V nominal. Otherwise, it can result in clock degradation and static current.</description>
7250 …<description>Control the power mode of the 800mV voltage reference buffer. The value in this regi…
7252 …ion is reduced to save current, and they work for vddd ramp rates of 10mV/us or less.</description>
7258 …description>Disable the 800mV voltage reference buffer. Firmware should only disable the buffer w…
7264 …<description>Disables the Active Reference. Firmware must ensure that LPM_READY==1 and BGREF_LPMO…
7266 1: Active Reference is disabled</description>
7272 … <description>Indicates that the normal mode of the Active Reference is ready.</description>
7280 <description>HIBERNATE Mode Register</description>
7289 …description>Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can b…
7295 …description>This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate. Any other va…
7301 …description>Firmware sets this bit to freeze the configuration, mode and state of all GPIOs and SI…
7307 <description>When set, HIBERNATE will wakeup for a RTC interrupt</description>
7313 <description>When set, HIBERNATE will wakeup if WDT matches</description>
7319 <description>Each bit sets the active polarity of the corresponding wakeup pin.
7321 1: Pin input of 1 will wakeup the part from HIBERNATE</description>
7327 …description>When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HI…
7333 <description>Hibernate disable bit.
7336 …de. Also, it is recommended to clear the UNLOCK code, if it was previously written..</description>
7342 …description>Firmware sets this bit to enter HIBERNATE mode. The system will enter HIBERNATE mode …
7350 <description>Low Voltage Detector (LVD) Configuration Register</description>
7359 …<description>Threshold selection for HVLVD1. Disable the LVD (HVLVD1_EN=0) before changing the th…
7375 15: rise=3.125V (nom), fall=3.1V (nom)</description>
7381 <description>Source selection for HVLVD1</description>
7387 <description>Select VDDD</description>
7392 <description>Select AMUXBUSA (VDDD branch)</description>
7397 <description>N/A</description>
7402 <description>N/A</description>
7407 <description>Select AMUXBUSB (VDDD branch)</description>
7414 …description>Enable HVLVD1 voltage monitor. When the LVD is enabled, it takes 20us for it to settl…
7422 <description>Buck Control Register</description>
7431 …<description>Voltage output selection for vccbuck1 output. This register is only reset by XRES/PO…
7439 7: 1.20V</description>
7445 …<description>Master enable for buck converter. This register is only reset by XRES/POR/BOD/HIBE…
7451 …description>Enable for vccbuck1 output. The value in this register is ignored unless PWR_BUCK_CTL…
7459 <description>Buck Control Register 2</description>
7468 …<description>Voltage output selection for vccbuck2 output. When increasing the voltage, it can ta…
7476 7: 1.50V</description>
7482 …description>Hardware control for vccbuck2 output. When this bit is set, the value in BUCK_OUT2_EN…
7488 …description>Enable for vccbuck2 output. The value in this register is ignored unless PWR_BUCK_CTL…
7496 <description>Low Voltage Detector (LVD) Status Register</description>
7505 <description>HVLVD1 output.
7507 1: above voltage threshold</description>
7517 <description>HIBERNATE Data Register</description>
7526 …description>Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used …
7534 <description>Watchdog Counter Control Register</description>
7543 …<description>Enable this watchdog timer. This field is retained during DEEPSLEEP and HIBERNATE mo…
7549 …<description>Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CT…
7550 …DEEPSLEEP or HIBERNATE mode, so the WDT will be locked after wakeup from these modes.</description>
7556 <description>No effect</description>
7561 <description>Clears bit 0</description>
7566 <description>Clears bit 1</description>
7571 <description>Sets both bits 0 and 1</description>
7580 <description>Watchdog Counter Count Register</description>
7589 …description>Current value of WDT Counter. The write feature of this register is for engineering u…
7597 <description>Watchdog Counter Match Register</description>
7606 …description>Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt i…
7612 …description>The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This…
7622 <description>Multi-Counter Watchdog Timer</description>
7627 <description>Multi-Counter Watchdog Sub-counters 0/1</description>
7636 …<description>Current value of sub-counter 0 for this MCWDT. Software writes are ignored when the …
7642 …<description>Current value of sub-counter 1 for this MCWDT. Software writes are ignored when the …
7650 <description>Multi-Counter Watchdog Sub-counter 2</description>
7659 …<description>Current value of sub-counter 2 for this MCWDT. Software writes are ignored when the …
7667 <description>Multi-Counter Watchdog Counter Match Register</description>
7676 <description>Match value for sub-counter 0 of this MCWDT</description>
7682 <description>Match value for sub-counter 1 of this MCWDT</description>
7690 <description>Multi-Counter Watchdog Counter Configuration</description>
7699 …<description>Watchdog Counter Action on Match. Action is taken on the next increment after the va…
7705 <description>Do nothing</description>
7710 <description>Assert WDT_INTx</description>
7715 <description>Assert WDT Reset</description>
7720 … <description>Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt</description>
7727 …<description>Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCL…
7729 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1.</description>
7735 …<description>Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MAT…
7737 1: Cascaded counters</description>
7743 …<description>Watchdog Counter Action on Match. Action is taken on the next increment after the va…
7749 <description>Do nothing</description>
7754 <description>Assert WDT_INTx</description>
7759 <description>Assert WDT Reset</description>
7764 … <description>Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt</description>
7771 …<description>Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFC…
7773 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1.</description>
7779 …<description>Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MAT…
7781 1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1.</description>
7787 <description>Watchdog Counter 2 Mode.</description>
7793 <description>Free running counter with no interrupt requests</description>
7798 …description>Free running counter with interrupt request that occurs one LFCLK cycle after the spec…
7805 <description>Bit to observe for WDT_INT2:
7808 31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks)</description>
7816 <description>Multi-Counter Watchdog Counter Control</description>
7825 <description>Enable subcounter 0. May take up to 2 LFCLK cycles to take effect.
7827 1: Counter is enabled (counting up)</description>
7833 …<description>Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles.</d…
7839 …description>Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. …
7845 <description>Enable subcounter 1. May take up to 2 LFCLK cycles to take effect.
7847 1: Counter is enabled (counting up)</description>
7853 …<description>Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles.</d…
7859 …description>Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. …
7865 <description>Enable subcounter 2. May take up to 2 LFCLK cycles to take effect.
7867 1: Counter is enabled (counting up)</description>
7873 …<description>Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles.</d…
7879 …description>Resets counter 2 back to 0000. Hardware will reset this bit after counter was reset. …
7887 <description>Multi-Counter Watchdog Counter Interrupt Register</description>
7896 …description>MCWDT Interrupt Request for sub-counter 0. This bit is set by hardware as configured …
7902 …description>MCWDT Interrupt Request for sub-counter 1. This bit is set by hardware as configured …
7908 …description>MCWDT Interrupt Request for sub-counter 2. This bit is set by hardware as configured …
7916 <description>Multi-Counter Watchdog Counter Interrupt Set Register</description>
7925 <description>Set interrupt for MCWDT_INT0</description>
7931 <description>Set interrupt for MCWDT_INT1</description>
7937 <description>Set interrupt for MCWDT_INT2</description>
7945 <description>Multi-Counter Watchdog Counter Interrupt Mask Register</description>
7954 <description>Mask for sub-counter 0</description>
7960 <description>Mask for sub-counter 1</description>
7966 <description>Mask for sub-counter 2</description>
7974 <description>Multi-Counter Watchdog Counter Interrupt Masked Register</description>
7983 <description>Logical and of corresponding request and mask bits.</description>
7989 <description>Logical and of corresponding request and mask bits.</description>
7995 <description>Logical and of corresponding request and mask bits.</description>
8003 <description>Multi-Counter Watchdog Counter Lock Register</description>
8012 …<description>Prohibits writing control and configuration registers related to this MCWDT when not …
8013 … are locked by the global WDT_LOCK register, and this register has no effect on that.</description>
8019 <description>No effect</description>
8024 <description>Clears bit 0</description>
8029 <description>Clears bit 1</description>
8034 <description>Sets both bits 0 and 1</description>
8046 <description>Clock DSI Select Register</description>
8055 …description>Selects a DSI source or low frequency clock for use in a clock path. The output of th…
8061 <description>DSI0 - dsi_out[0]</description>
8066 <description>DSI1 - dsi_out[1]</description>
8071 <description>DSI2 - dsi_out[2]</description>
8076 <description>DSI3 - dsi_out[3]</description>
8081 <description>DSI4 - dsi_out[4]</description>
8086 <description>DSI5 - dsi_out[5]</description>
8091 <description>DSI6 - dsi_out[6]</description>
8096 <description>DSI7 - dsi_out[7]</description>
8101 <description>DSI8 - dsi_out[8]</description>
8106 <description>DSI9 - dsi_out[9]</description>
8111 <description>DSI10 - dsi_out[10]</description>
8116 <description>DSI11 - dsi_out[11]</description>
8121 <description>DSI12 - dsi_out[12]</description>
8126 <description>DSI13 - dsi_out[13]</description>
8131 <description>DSI14 - dsi_out[14]</description>
8136 <description>DSI15 - dsi_out[15]</description>
8141 <description>ILO - Internal Low-speed Oscillator</description>
8146 <description>WCO - Watch-Crystal Oscillator</description>
8151 <description>ALTLF - Alternate Low-Frequency Clock</description>
8156 <description>PILO - Precision Internal Low-speed Oscillator</description>
8167 <description>Clock Path Select Register</description>
8176 …description>Selects a source for clock PATH<i>. Note that not all products support all cloc…
8182 <description>IMO - Internal R/C Oscillator</description>
8187 <description>EXTCLK - External Clock Pin</description>
8192 <description>ECO - External-Crystal Oscillator</description>
8197 … <description>ALTHF - Alternate High-Frequency clock input (product-specific clock)</description>
8202 …<description>DSI_MUX - Output of DSI mux for this path. Using a DSI source directly as root of HF…
8213 <description>Clock Root Select Register</description>
8222 …description>Selects a clock path as the root of HFCLK<k> and for SRSS DSI input <k>. …
8228 <description>Select PATH0 (can be configured for FLL)</description>
8233 … <description>Select PATH1 (can be configured for PLL0, if available in the product)</description>
8238 … <description>Select PATH2 (can be configured for PLL1, if available in the product)</description>
8243 … <description>Select PATH3 (can be configured for PLL2, if available in the product)</description>
8248 … <description>Select PATH4 (can be configured for PLL3, if available in the product)</description>
8253 … <description>Select PATH5 (can be configured for PLL4, if available in the product)</description>
8258 … <description>Select PATH6 (can be configured for PLL5, if available in the product)</description>
8263 … <description>Select PATH7 (can be configured for PLL6, if available in the product)</description>
8268 … <description>Select PATH8 (can be configured for PLL7, if available in the product)</description>
8273 … <description>Select PATH9 (can be configured for PLL8, if available in the product)</description>
8278 … <description>Select PATH10 (can be configured for PLL9, if available in the product)</description>
8283 …<description>Select PATH11 (can be configured for PLL10, if available in the product)</description>
8288 …<description>Select PATH12 (can be configured for PLL11, if available in the product)</description>
8293 …<description>Select PATH13 (can be configured for PLL12, if available in the product)</description>
8298 …<description>Select PATH14 (can be configured for PLL13, if available in the product)</description>
8303 …<description>Select PATH15 (can be configured for PLL14, if available in the product)</description>
8310 <description>Selects predivider value for this clock root and DSI input.</description>
8316 … <description>Transparent mode, feed through selected clock source w/o dividing.</description>
8321 <description>Divide selected clock source by 2</description>
8326 <description>Divide selected clock source by 4</description>
8331 <description>Divide selected clock source by 8</description>
8338 …<description>Enable for this clock root. All clock roots default to disabled (ENABLE==0) except H…
8346 <description>Clock selection register</description>
8355 …description>Select source for LFCLK. Note that not all products support all clock sources. Selec…
8361 <description>ILO - Internal Low-speed Oscillator</description>
8366 …description>WCO - Watch-Crystal Oscillator. Requires Backup domain to be present and properly con…
8371 … <description>ALTLF - Alternate Low-Frequency Clock. Capability is product-specific</description>
8376 …<description>PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes. Does not w…
8383 …description>Selects clock PATH<k>, where k=PUMP_SEL. The output of this mux goes to the PUM…
8389 …<description>Division ratio for PUMPCLK. Uses selected PUMP_SEL clock as the source.</description>
8395 … <description>Transparent mode, feed through selected clock source w/o dividing.</description>
8400 <description>Divide selected clock source by 2</description>
8405 <description>Divide selected clock source by 4</description>
8410 <description>Divide selected clock source by 8</description>
8415 <description>Divide selected clock source by 16</description>
8422 …<description>Enable the pump clock. PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minim…
8425 3) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV.</description>
8433 <description>Timer Clock Control Register</description>
8442 …<description>Select source for TIMERCLK. The output of this mux can be further divided using TIME…
8448 <description>IMO - Internal Main Oscillator</description>
8453 … <description>Select the output of the predivider configured by TIMER_HF0_DIV.</description>
8460 …description>Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less th…
8466 …<description>Transparent mode, feed through selected clock source w/o dividing or correcting duty …
8471 <description>Divide HFCLK0 by 2.</description>
8476 <description>Divide HFCLK0 by 4.</description>
8481 <description>Divide HFCLK0 by 8.</description>
8488 …description>Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TI…
8494 <description>Enable for TIMERCLK.
8496 1: TIMERCLK is enabled</description>
8504 <description>ILO Configuration</description>
8513 …<description>If backup domain is present on this product, this register indicates that ILO should …
8515 …ains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry.</description>
8521 …description>Master enable for ILO. Writes to this field are ignored unless the WDT is unlocked us…
8529 <description>IMO Configuration</description>
8538 …description>Master enable for IMO oscillator. This bit must be high at all times for all function…
8546 <description>Fast Clock Output Select Register</description>
8555 <description>Select signal for fast clock output #0</description>
8561 …<description>Disabled - output is 0. For power savings, clocks are blocked before entering any mu…
8566 <description>External Crystal Oscillator (ECO)</description>
8571 <description>External clock input (EXTCLK)</description>
8576 <description>Alternate High-Frequency (ALTHF) clock input to SRSS</description>
8581 …description>Timer clock. It is grouped with the fast clocks because it may be a gated version of …
8586 <description>Selects the clock path chosen by PATH_SEL0 field</description>
8591 <description>Selects the output of the HFCLK_SEL0 mux</description>
8596 <description>Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0</description>
8603 <description>Selects a clock path to use in fast clock output #0 logic. 0: FLL output
8604 1-15: PLL output on path1-path15 (if available)</description>
8610 <description>Selects a HFCLK tree for use in fast clock output #0</description>
8616 <description>Select signal for fast clock output #1</description>
8622 …<description>Disabled - output is 0. For power savings, clocks are blocked before entering any mu…
8627 <description>External Crystal Oscillator (ECO)</description>
8632 <description>External clock input (EXTCLK)</description>
8637 <description>Alternate High-Frequency (ALTHF) clock input to SRSS</description>
8642 …description>Timer clock. It is grouped with the fast clocks because it may be a gated version of …
8647 <description>Selects the clock path chosen by PATH_SEL1 field</description>
8652 <description>Selects the output of the HFCLK_SEL1 mux</description>
8657 <description>Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1</description>
8664 <description>Selects a clock path to use in fast clock output #1 logic. 0: FLL output
8665 1-15: PLL output on path1-path15 (if available)</description>
8671 <description>Selects a HFCLK tree for use in fast clock output #1 logic</description>
8679 <description>Slow Clock Output Select Register</description>
8688 <description>Select signal for slow clock output #0</description>
8694 …<description>Disabled - output is 0. For power savings, clocks are blocked before entering any mu…
8699 <description>Internal Low Speed Oscillator (ILO)</description>
8704 <description>Watch-Crystal Oscillator (WCO)</description>
8709 <description>Root of the Backup domain clock tree (BAK)</description>
8714 <description>Alternate low-frequency clock input to SRSS (ALTLF)</description>
8719 <description>Root of the low-speed clock tree (LFCLK)</description>
8724 …<description>Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be ob…
8729 …<description>Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be …
8734 <description>Precision Internal Low Speed Oscillator (PILO)</description>
8741 <description>Select signal for slow clock output #1</description>
8747 …<description>Disabled - output is 0. For power savings, clocks are blocked before entering any mu…
8752 <description>Internal Low Speed Oscillator (ILO)</description>
8757 <description>Watch-Crystal Oscillator (WCO)</description>
8762 <description>Root of the Backup domain clock tree (BAK)</description>
8767 <description>Alternate low-frequency clock input to SRSS (ALTLF)</description>
8772 <description>Root of the low-speed clock tree (LFCLK)</description>
8777 …<description>Internal Main Oscillator (IMO). This is grouped with the slow clocks so it can be ob…
8782 …<description>Sleep Controller clock (SLPCTRL). This is grouped with the slow clocks so it can be …
8787 <description>Precision Internal Low Speed Oscillator (PILO)</description>
8796 <description>Clock Calibration Counter 1</description>
8805 …description>Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register alwa…
8811 …<description>Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_C…
8819 <description>Clock Calibration Counter 2</description>
8828 …description>Up-counter clocked on fast clock output #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.C…
8836 <description>ECO Configuration Register</description>
8845 …description>Automatic Gain Control (AGC) enable. When set, the oscillation amplitude is controlle…
8851 <description>Master enable for ECO oscillator.</description>
8859 <description>ECO Status Register</description>
8868 …<description>Indicates the ECO internal oscillator circuit has sufficient amplitude. It may not m…
8874 …description>Indicates the ECO internal oscillator circuit has had enough time to fully stabilize. …
8882 <description>Precision ILO Configuration Register</description>
8891 …<description>Fine frequency trim allowing +/-250ppm accuracy with periodic calibration. The nomin…
8897 …<description>Enable the PILO clock output. See PILO_EN field for required sequencing.</descriptio…
8903 <description>Reset the PILO. See PILO_EN field for required sequencing.</description>
8909 …description>Enable PILO. When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PIL…
8917 <description>FLL Configuration Register</description>
8926 …<description>Multiplier to determine CCO frequency in multiples of the frequency of the selected r…
8928 Ffll = (FLL_MULT) * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1)</description>
8934 …<description>Control bits for Output divider. Set the divide value before enabling the FLL, and d…
8936 1: divide by 2</description>
8942 …<description>Master enable for FLL. The FLL requires firmware sequencing when enabling, disabling…
8951 1: Block is powered on</description>
8959 <description>FLL Configuration Register 2</description>
8968 …<description>Control bits for reference divider. Set the divide value before enabling the FLL, an…
8972 8191: divide by 8191</description>
8978 …<description>Lock tolerance sets the error threshold for when the FLL output is considered locked …
8982 511: tolerate error of 512 count values</description>
8990 <description>FLL Configuration Register 3</description>
8999 …<description>FLL Loop Filter Gain Setting #1. The proportional gain is the sum of FLL_LF_IGAIN an…
9012 >=12: illegal</description>
9018 …<description>FLL Loop Filter Gain Setting #2. The proportional gain is the sum of FLL_LF_IGAIN an…
9031 >=12: illegal</description>
9037 …<description>Number of undivided reference clock cycles to wait after changing the CCO trim until …
9041 8191: wait 8191 reference clock cycles</description>
9047 …description>Bypass mux located just after FLL output. See FLL_ENABLE description for instructions…
9053 <description>N/A</description>
9058 <description>N/A</description>
9063 … <description>Select FLL reference input (bypass mode). Ignores lock indicator</description>
9068 <description>Select FLL output. Ignores lock indicator.</description>
9077 <description>FLL Configuration Register 4</description>
9086 …<description>Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO freque…
9092 <description>Frequency range of CCO</description>
9098 <description>Target frequency is in range [48, 64) MHz</description>
9103 <description>Target frequency is in range [64, 85) MHz</description>
9108 <description>Target frequency is in range [85, 113) MHz</description>
9113 <description>Target frequency is in range [113, 150) MHz</description>
9118 <description>Target frequency is in range [150, 200] MHz</description>
9125 …description>CCO frequency code. This is updated by HW when the FLL is enabled. It can be manuall…
9131 <description>Disable CCO frequency update by FLL hardware
9133 …re update of CCO settings is disabled. Use this setting for open-loop FLL operation.</description>
9139 <description>Enable the CCO. It is required to enable the CCO before using the FLL.
9141 1: Block is powered on</description>
9149 <description>FLL Status Register</description>
9158 …description>FLL Lock Indicator. LOCKED is high when FLL is within CLK_FLL_CONFIG2.LOCK_TOL. If F…
9164 <description>N/A</description>
9170 … <description>This indicates that the CCO is internally settled and ready to use.</description>
9180 <description>PLL Configuration Register</description>
9189 …<description>Control bits for feedback divider. Set the divide value before enabling the PLL, and…
9194 >112: illegal (undefined behavior)</description>
9200 …<description>Control bits for reference divider. Set the divide value before enabling the PLL, an…
9205 others: illegal (undefined behavior)</description>
9211 …<description>Control bits for Output divider. Set the divide value before enabling the PLL, and d…
9217 >16: illegal (undefined behavior)</description>
9223 …<description>VCO frequency range selection. Configure this bit according to the targeted VCO freq…
9225 1: VCO frequency is [170MHz, 200MHz)</description>
9231 …<description>Bypass mux located just after PLL output. This selection is glitch-free and can be c…
9237 …description>Automatic using lock indicator. When unlocked, automatically selects PLL reference in…
9242 <description>Same as AUTO</description>
9247 … <description>Select PLL reference input (bypass mode). Ignores lock indicator</description>
9252 <description>Select PLL output. Ignores lock indicator.</description>
9259 …<description>Master enable for PLL. Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least on…
9264 1: Block is enabled</description>
9274 <description>PLL Status Register</description>
9283 <description>PLL Lock Indicator</description>
9289 …<description>This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firm…
9297 <description>SRSS Interrupt Register</description>
9306 …description>WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. W1C also fee…
9312 <description>Interrupt for low voltage detector HVLVD1</description>
9318 …<description>Clock calibration counter is done. This field is reset during DEEPSLEEP mode.</descr…
9326 <description>SRSS Interrupt Set Register</description>
9335 <description>Set interrupt for low voltage detector WDT_MATCH</description>
9341 <description>Set interrupt for low voltage detector HVLVD1</description>
9347 …<description>Set interrupt for clock calibration counter done. This field is reset during DEEPSLE…
9355 <description>SRSS Interrupt Mask Register</description>
9364 …description>Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU.…
9370 <description>Mask for low voltage detector HVLVD1</description>
9376 <description>Mask for clock calibration done</description>
9384 <description>SRSS Interrupt Masked Register</description>
9393 <description>Logical and of corresponding request and mask bits.</description>
9399 <description>Logical and of corresponding request and mask bits.</description>
9405 <description>Logical and of corresponding request and mask bits.</description>
9413 <description>SRSS Interrupt Configuration Register</description>
9422 <description>Sets which edge(s) will trigger an IRQ for HVLVD1</description>
9428 <description>Disabled</description>
9433 <description>Rising edge</description>
9438 <description>Falling edge</description>
9443 <description>Both rising and falling edges</description>
9452 <description>Reset Cause Observation Register</description>
9461 … <description>A basic WatchDog Timer (WDT) reset has occurred since last power cycle.</description>
9467 … <description>Fault logging system requested a reset from its Active logic.</description>
9473 … <description>Fault logging system requested a reset from its DeepSleep logic.</description>
9479 …<description>Clock supervision logic requested a reset due to loss of a watch-crystal clock.</desc…
9485 …<description>A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debu…
9491 …<description>Multi-Counter Watchdog timer reset #0 has occurred since last power cycle.</descripti…
9497 …<description>Multi-Counter Watchdog timer reset #1 has occurred since last power cycle.</descripti…
9503 …<description>Multi-Counter Watchdog timer reset #2 has occurred since last power cycle.</descripti…
9509 …<description>Multi-Counter Watchdog timer reset #3 has occurred since last power cycle.</descripti…
9517 <description>Reset Cause Observation Register 2</description>
9526 …description>Clock supervision logic requested a reset due to loss of a high-frequency clock. Each…
9532 …description>Clock supervision logic requested a reset due to frequency error of high-frequency clo…
9540 <description>Reference Trim Register</description>
9549 …<description>Active-Reference temperature trim. This register is only reset by XRES/POR/BOD/HIBER…
9551 others -> normal trim range</description>
9557 …<description>Active-Reference current trim. This register is only reset by XRES/POR/BOD/HIBERNAT…
9559 others -> normal trim range</description>
9565 …<description>Active-Reference absolute voltage trim. This register is only reset by XRES/POR/BOD/…
9567 others -> normal trim range</description>
9573 …<description>Active-Reference current boost. This register is only reset by XRES/POR/BOD/HIBERNA…
9575 others: risk mitigation</description>
9581 …<description>DeepSleep-Reference temperature trim. This register is only reset by XRES/POR/BOD/HI…
9583 others -> normal trim range</description>
9589 …<description>DeepSleep-Reference absolute voltage trim. This register is only reset by XRES/POR/B…
9595 …<description>DeepSleep current reference trim. This register is only reset by XRES/POR/BOD/HIBER…
9603 <description>BOD/OVP Trim Register</description>
9612 …<description>HVPORBOD trip point selection. Monitors vddd. This register is only reset by XRES/P…
9618 …<description>HVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE.</descri…
9624 …<description>HVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE.</descr…
9630 …<description>LVPORBOD trip point selection. Monitors vccd. This register is only reset by XRES/P…
9636 …<description>LVPORBOD offset trim. This register is only reset by XRES/POR/BOD/HIBERNATE.</descri…
9642 …<description>LVPORBOD current trim. This register is only reset by XRES/POR/BOD/HIBERNATE.</descr…
9650 <description>CCO Trim Register</description>
9659 <description>CCO reference current source trim.</description>
9665 …<description>Terminal count for the stabilization counter from CCO_ENABLE until stable.</descripti…
9671 <description>Enables the automatic stabilization counter.</description>
9679 <description>CCO Trim Register 2</description>
9688 <description>CCO frequency 1st range calibration</description>
9694 <description>CCO frequency 2nd range calibration</description>
9700 <description>CCO frequency 3rd range calibration</description>
9706 <description>CCO frequency 4th range calibration</description>
9712 <description>CCO frequency 5th range calibration</description>
9720 <description>Wakeup Trim Register</description>
9729 …description>Wakeup holdoff. Spec (fastest) wake time is achieved with a setting of 0. Additional…
9737 <description>LVD Trim Register</description>
9746 <description>HVLVD1 offset trim</description>
9752 <description>HVLVD1 current trim</description>
9760 <description>ILO Trim Register</description>
9769 …<description>ILO frequency trims. LSB step size is 1.5 percent (typical) of the frequency.</descr…
9777 <description>Power System Trim Register</description>
9786 …description>Trim for the Active-Regulator. This sets the output voltage level. This register is …
9792 …<description>Controls the tradeoff between output current and internal operating current for the A…
9806 This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
9814 <description>ECO Trim Register</description>
9823 <description>Watch Dog Trim - Delta voltage below steady state level
9831 0x7 - 225mV</description>
9837 …<description>Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use…
9853 0xF - 525mV</description>
9859 <description>Filter Trim - 3rd harmonic oscillation</description>
9865 <description>Feedback resistor Trim</description>
9871 <description>Gain Trim - Startup time</description>
9877 <description>Current Trim</description>
9885 <description>PILO Trim Register</description>
9894 …description>Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration. …
9900 <description>Trim for current in oscillator block.</description>
9906 <description>Trim for comparator bias current.</description>
9912 … <description>Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier</description>
9918 <description>Trim for beta-multiplier branch current</description>
9924 <description>Trim for beta-multiplier current slope</description>
9930 <description>Trim for VT-DIFF output (internal power supply)</description>
9938 <description>PILO Trim Register 2</description>
9947 <description>Trim for voltage reference</description>
9953 <description>Trim for beta-multiplier current reference</description>
9959 <description>Trim for current reference</description>
9967 <description>PILO Trim Register 3</description>
9976 <description>Engineering options for PILO circuits
9988 15-11: Frequency fine trim. See AKK-444 for an overview of the trim strategy.</description>
9998 <description>SRSS Backup Domain</description>
10008 <description>Control</description>
10017 …<description>Watch-crystal oscillator (WCO) enable. If there is a write in progress when this bit…
10018 …e for example RTC or WDTs. Follow the procedure in BACKUP_RTC_RW to access this bit.</description>
10024 <description>Clock select for BAK clock</description>
10030 <description>Watch-crystal oscillator input.</description>
10035 …description>This allows to use the LFCLK selection as an alternate backup domain clock. Note that…
10042 <description>N/A</description>
10048 …<description>Configures the WCO for different board-level connections to the WCO pins. For exampl…
10050 …, either a square wave or sine wave. See PRESCALER field for connection information.</description>
10056 … <description>Controls the behavior of the switch that generates vddbak from vbackup or vddd.
10058 1,2,3: force vddbak and vmax to select vbackup, regardless of its voltage.</description>
10064 …description>Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached t…
10070 …description>When set to 3C, the supercap charger circuit is enabled. Any other code disables the …
10078 <description>RTC Read Write register</description>
10087 <description>Read bit
10089 …e bit is set. Do not set the Read bit at the same time that the Write bit is cleared.</description>
10095 <description>Write bit
10101 …e RTC_BUSY). Do not set the Write bit at the same time that the Read bit is cleared.</description>
10109 <description>Oscillator calibration for absolute frequency</description>
10118 …<description>Calibration value for absolute frequency (at a fixed temperature). Each step causes …
10121 …d applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments.</description>
10127 <description>Calibration sign:
10129 1= Positive sign: add pulses (it takes less clock ticks to count one second)</description>
10135 …description>Output enable for 512Hz signal for calibration and allow CALIB_VAL to be written. Note…
10143 <description>Status</description>
10152 <description>pending RTC write</description>
10158 <description>Indicates that output has transitioned.</description>
10166 <description>Calendar Seconds, Minutes, Hours, Day of Week</description>
10175 <description>Calendar seconds in BCD, 0-59</description>
10181 <description>Calendar minutes in BCD, 0-59</description>
10187 <description>Calendar hours in BCD, value depending on 12/24HR mode
10189 1=12HR: [21]:0=AM, 1=PM, [20:16]=1-12</description>
10195 <description>Select 12/24HR mode: 1=12HR, 0=24HR</description>
10201 <description>Calendar Day of the week in BCD, 1-7
10202 It is up to the user to define the meaning of the values, but 1=Monday is recommended</description>
10210 <description>Calendar Day of Month, Month, Year</description>
10219 <description>Calendar Day of the Month in BCD, 1-31
10220 Automatic Leap Year Correction</description>
10226 <description>Calendar Month in BCD, 1-12</description>
10232 <description>Calendar year in BCD, 0-99</description>
10240 <description>Alarm 1 Seconds, Minute, Hours, Day of Week</description>
10249 <description>Alarm seconds in BCD, 0-59</description>
10255 <description>Alarm second enable: 0=ignore, 1=match</description>
10261 <description>Alarm minutes in BCD, 0-59</description>
10267 <description>Alarm minutes enable: 0=ignore, 1=match</description>
10273 <description>Alarm hours in BCD, value depending on 12/24HR mode
10275 24HR: [5:0]=0-23</description>
10281 <description>Alarm hour enable: 0=ignore, 1=match</description>
10287 <description>Alarm Day of the week in BCD, 1-7
10288 It is up to the user to define the meaning of the values, but 1=Monday is recommended</description>
10294 <description>Alarm Day of the Week enable: 0=ignore, 1=match</description>
10302 <description>Alarm 1 Day of Month, Month</description>
10311 <description>Alarm Day of the Month in BCD, 1-31
10312 Leap Year corrected</description>
10318 <description>Alarm Day of the Month enable: 0=ignore, 1=match</description>
10324 <description>Alarm Month in BCD, 1-12</description>
10330 <description>Alarm Month enable: 0=ignore, 1=match</description>
10336 <description>Master enable for alarm 1.
10338 … of the date and time fields are enabled, then this alarm triggers once every second.</description>
10346 <description>Alarm 2 Seconds, Minute, Hours, Day of Week</description>
10355 <description>Alarm seconds in BCD, 0-59</description>
10361 <description>Alarm second enable: 0=ignore, 1=match</description>
10367 <description>Alarm minutes in BCD, 0-59</description>
10373 <description>Alarm minutes enable: 0=ignore, 1=match</description>
10379 <description>Alarm hours in BCD, value depending on 12/24HR mode
10381 24HR: [5:0]=0-23</description>
10387 <description>Alarm hour enable: 0=ignore, 1=match</description>
10393 <description>Alarm Day of the week in BCD, 1-7
10394 It is up to the user to define the meaning of the values, but 1=Monday is recommended</description>
10400 <description>Alarm Day of the Week enable: 0=ignore, 1=match</description>
10408 <description>Alarm 2 Day of Month, Month</description>
10417 <description>Alarm Day of the Month in BCD, 1-31
10418 Leap Year corrected</description>
10424 <description>Alarm Day of the Month enable: 0=ignore, 1=match</description>
10430 <description>Alarm Month in BCD, 1-12</description>
10436 <description>Alarm Month enable: 0=ignore, 1=match</description>
10442 <description>Master enable for alarm 2.
10444 … of the date and time fields are enabled, then this alarm triggers once every second.</description>
10452 <description>Interrupt request register</description>
10461 <description>Alarm 1 Interrupt</description>
10467 <description>Alarm 2 Interrupt</description>
10473 <description>Century overflow interrupt</description>
10481 <description>Interrupt set request register</description>
10490 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
10496 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
10502 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
10510 <description>Interrupt mask register</description>
10519 … <description>Mask bit for corresponding bit in interrupt request register.</description>
10525 … <description>Mask bit for corresponding bit in interrupt request register.</description>
10531 … <description>Mask bit for corresponding bit in interrupt request register.</description>
10539 <description>Interrupt masked request register</description>
10548 <description>Logical and of corresponding request and mask bits.</description>
10554 <description>Logical and of corresponding request and mask bits.</description>
10560 <description>Logical and of corresponding request and mask bits.</description>
10568 <description>32kHz oscillator counter</description>
10577 …<description>32kHz oscillator count (msb=128Hz), calibration can cause bit 6 to skip. Reset when …
10585 <description>128Hz tick counter</description>
10594 <description>128Hz counter (msb=2Hz)
10595 When SECONDS is written this field will be reset.</description>
10603 <description>PMIC control register</description>
10612 …description>This byte must be set to 0x3A for PMIC to be disabled. When the UNLOCK code is not pr…
10618 <description>N/A</description>
10624 <description>Output enable for the output driver in the PMIC_EN pad.
10626 1: Output pad is enabled for PMIC_EN pin.</description>
10632 …<description>Override normal PMIC controls to prevent accidentally turning off the PMIC by errant …
10635 Note: This bit is a write-once bit until the next backup reset.</description>
10641 …description>Enable for external PMIC that supplies vddd (if present). This bit will only clear if…
10649 <description>Backup reset register</description>
10658 …description>Writing 1 to this register resets the backup logic. Hardware clears it when the reset…
10668 <description>Backup register region</description>
10677 …<description>Backup memory that contains application-specific data. Memory is retained on vbackup…
10685 <description>Trim Register</description>
10694 <description>WCO trim</description>
10704 <description>Datawire Controller</description>
10715 <description>Control</description>
10724 <description>IP enable:
10726 '1': Enabled.</description>
10734 <description>Status</description>
10743 <description>Active channel, user/privileged access control:
10745 '1': privileged mode.</description>
10751 <description>Active channel, secure/non-secure access control:
10753 '1': non-secure.</description>
10759 <description>Active channel, non-bufferable/bufferable access control:
10761 '1': bufferable.</description>
10767 <description>Active channel protection context.</description>
10773 <description>Active channel index.</description>
10779 <description>Active channel priority.</description>
10785 <description>Active channel preemptable.</description>
10791 <description>State of the DW controller.
10797 '5': Wait for trigger de-activation.</description>
10803 <description>Active channel present:
10805 '1': Yes.</description>
10813 <description>Pending channels</description>
10822 …description>Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This…
10830 <description>System interrupt control</description>
10839 <description>Reflects the INTR.CH bit fields of all channels.</description>
10847 <description>Status of interrupts masked</description>
10856 <description>Reflects the INTR_MASKED.CH bit fields of all channels.</description>
10864 <description>Active descriptor control</description>
10873 <description>Copy of DESCR_CTL of the currently active descriptor.</description>
10881 <description>Active descriptor source</description>
10890 <description>Copy of DESCR_SRC of the currently active descriptor.</description>
10898 <description>Active descriptor destination</description>
10907 <description>Copy of DESCR_DST of the currently active descriptor.</description>
10915 <description>Active descriptor X loop control</description>
10924 <description>Copy of DESCR_X_CTL of the currently active descriptor.</description>
10932 <description>Active descriptor Y loop control</description>
10941 <description>Copy of DESCR_Y_CTL of the currently active descriptor.</description>
10949 <description>Active descriptor next pointer</description>
10958 <description>Copy of DESCR_NEXT_PTR of the currently active descriptor.</description>
10966 <description>Active source</description>
10975 <description>Current address of source location.</description>
10983 <description>Active destination</description>
10992 <description>Current address of destination location.</description>
11002 <description>DW channel structure</description>
11006 <description>Channel control</description>
11015 <description>User/privileged access control:
11021 …for this channel use the P field for the user/privileged access control ('hprot[1]').</description>
11027 <description>Secure/on-secure access control:
11033 … this channel use the NS field for the secure/non-secure access control ('hprot[4]').</description>
11039 <description>Non-bufferable/bufferable access control:
11045 …annel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').</description>
11051 <description>Protection context.
11055 All transactions for this channel uses the PC field for the protection context.</description>
11061 <description>Channel priority:
11067 … gives the highest priority to the lower channel indices (within the priority group).</description>
11073 <description>Specifies if the channel is preemptable.
11075 …etion of a higher priority activated channel, the current channel may be reactivated.</description>
11081 <description>Channel enable:
11087 …n an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).</description>
11095 <description>Channel status</description>
11104 <description>Specifies the source of the interrupt cause:
11116 …AUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').</description>
11124 <description>Channel current indices</description>
11133 …<description>Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the…
11137 Note: SW should set this field to '0' when it updates CH_CURR_PTR.</description>
11143 … <description>Specifies the Y loop index, with X_COUNT taken from the current descriptor.
11147 Note: SW should set this field to '0' when it updates CH_CURR_PTR.</description>
11155 <description>Channel current descriptor pointer</description>
11164 … <description>Address of current descriptor. When this field is '0', there is no valid descriptor.
11168 …nt descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.</description>
11176 <description>Interrupt</description>
11185 …description>Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.…
11193 <description>Interrupt set</description>
11202 …<description>Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has …
11210 <description>Interrupt mask</description>
11219 <description>Mask for corresponding field in INTR register.</description>
11227 <description>Interrupt masked</description>
11236 <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
11251 <description>EFUSE MXS40 registers</description>
11261 <description>Control</description>
11270 <description>IP enable:
11272 '1': Enabled.</description>
11280 <description>Command</description>
11289 …description>Bit data. This field specifies the bit value that is to be programmed into the eFUSE m…
11295 <description>Bit address. This field specifies a bit within a Byte.</description>
11301 …<description>Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B).…
11307 <description>Macro address. This field specifies an eFUSE macro.</description>
11313 …<description>FW sets this field to '1' to start a program operation. HW sets this field to '0' to …
11319 …sfer to the eFUSE memory during a program operation results in an AHB-Lite bus error.</description>
11327 <description>Sequencer Default value</description>
11336 <description>Specifies value of eFUSE control signal strobe_f</description>
11342 <description>Specifies value of eFUSEcontrol signal strobe_b</description>
11348 <description>Specifies value of eFUSE control signal strobe_c</description>
11354 <description>Specifies value of eFUSE control signal strobe_d</description>
11360 <description>Specifies value of eFUSE control signal strobe_e</description>
11366 <description>Specifies value of eFUSE control signal strobe_f</description>
11372 <description>Specifies value of eFUSE control signal strobe_g</description>
11380 <description>Sequencer read control 0</description>
11389 …description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing…
11395 <description>Specifies value of eFUSE control signal strobe_f</description>
11401 <description>Specifies value of eFUSEcontrol signal strobe_b</description>
11407 <description>Specifies value of eFUSE control signal strobe_c</description>
11413 <description>Specifies value of eFUSE control signal strobe_d</description>
11419 <description>Specifies value of eFUSE control signal strobe_e</description>
11425 <description>Specifies value of eFUSE control signal strobe_f</description>
11431 <description>Specifies value of eFUSE control signal strobe_g</description>
11437 …<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches…
11445 <description>Sequencer read control 1</description>
11454 …description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing…
11460 <description>Specifies value of eFUSE control signal strobe_f</description>
11466 <description>Specifies value of eFUSEcontrol signal strobe_b</description>
11472 <description>Specifies value of eFUSE control signal strobe_c</description>
11478 <description>Specifies value of eFUSE control signal strobe_d</description>
11484 <description>Specifies value of eFUSE control signal strobe_e</description>
11490 <description>Specifies value of eFUSE control signal strobe_f</description>
11496 <description>Specifies value of eFUSE control signal strobe_g</description>
11502 …<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches…
11510 <description>Sequencer read control 2</description>
11519 …description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing…
11525 <description>Specifies value of eFUSE control signal strobe_f</description>
11531 <description>Specifies value of eFUSEcontrol signal strobe_b</description>
11537 <description>Specifies value of eFUSE control signal strobe_c</description>
11543 <description>Specifies value of eFUSE control signal strobe_d</description>
11549 <description>Specifies value of eFUSE control signal strobe_e</description>
11555 <description>Specifies value of eFUSE control signal strobe_f</description>
11561 <description>Specifies value of eFUSE control signal strobe_g</description>
11567 …<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches…
11575 <description>Sequencer read control 3</description>
11584 …description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing…
11590 <description>Specifies value of eFUSE control signal strobe_f</description>
11596 <description>Specifies value of eFUSEcontrol signal strobe_b</description>
11602 <description>Specifies value of eFUSE control signal strobe_c</description>
11608 <description>Specifies value of eFUSE control signal strobe_d</description>
11614 <description>Specifies value of eFUSE control signal strobe_e</description>
11620 <description>Specifies value of eFUSE control signal strobe_f</description>
11626 <description>Specifies value of eFUSE control signal strobe_g</description>
11632 …<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches…
11640 <description>Sequencer read control 4</description>
11649 …description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing…
11655 <description>Specifies value of eFUSE control signal strobe_f</description>
11661 <description>Specifies value of eFUSEcontrol signal strobe_b</description>
11667 <description>Specifies value of eFUSE control signal strobe_c</description>
11673 <description>Specifies value of eFUSE control signal strobe_d</description>
11679 <description>Specifies value of eFUSE control signal strobe_e</description>
11685 <description>Specifies value of eFUSE control signal strobe_f</description>
11691 <description>Specifies value of eFUSE control signal strobe_g</description>
11697 …<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches…
11705 <description>Sequencer read control 5</description>
11714 …description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing…
11720 <description>Specifies value of eFUSE control signal strobe_f</description>
11726 <description>Specifies value of eFUSEcontrol signal strobe_b</description>
11732 <description>Specifies value of eFUSE control signal strobe_c</description>
11738 <description>Specifies value of eFUSE control signal strobe_d</description>
11744 <description>Specifies value of eFUSE control signal strobe_e</description>
11750 <description>Specifies value of eFUSE control signal strobe_f</description>
11756 <description>Specifies value of eFUSE control signal strobe_g</description>
11762 …<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches…
11770 <description>Sequencer program control 0</description>
11779 …description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing…
11785 <description>Specifies value of eFUSE control signal strobe_a</description>
11791 <description>Specifies value of eFUSEcontrol signal strobe_b</description>
11797 <description>Specifies value of eFUSE control signal strobe_c</description>
11803 <description>Specifies value of eFUSE control signal strobe_d</description>
11809 <description>Specifies value of eFUSE control signal strobe_e</description>
11815 <description>Specifies value of eFUSE control signal strobe_f</description>
11821 <description>Specifies value of eFUSE control signal strobe_g</description>
11827 …<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches…
11835 <description>Sequencer program control 1</description>
11844 …description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing…
11850 <description>Specifies value of eFUSE control signal strobe_a</description>
11856 <description>Specifies value of eFUSEcontrol signal strobe_b</description>
11862 <description>Specifies value of eFUSE control signal strobe_c</description>
11868 <description>Specifies value of eFUSE control signal strobe_d</description>
11874 <description>Specifies value of eFUSE control signal strobe_e</description>
11880 <description>Specifies value of eFUSE control signal strobe_f</description>
11886 <description>Specifies value of eFUSE control signal strobe_g</description>
11892 …<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches…
11900 <description>Sequencer program control 2</description>
11909 …description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing…
11915 <description>Specifies value of eFUSE control signal strobe_a</description>
11921 <description>Specifies value of eFUSEcontrol signal strobe_b</description>
11927 <description>Specifies value of eFUSE control signal strobe_c</description>
11933 <description>Specifies value of eFUSE control signal strobe_d</description>
11939 <description>Specifies value of eFUSE control signal strobe_e</description>
11945 <description>Specifies value of eFUSE control signal strobe_f</description>
11951 <description>Specifies value of eFUSE control signal strobe_g</description>
11957 …<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches…
11965 <description>Sequencer program control 3</description>
11974 …description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing…
11980 <description>Specifies value of eFUSE control signal strobe_a</description>
11986 <description>Specifies value of eFUSEcontrol signal strobe_b</description>
11992 <description>Specifies value of eFUSE control signal strobe_c</description>
11998 <description>Specifies value of eFUSE control signal strobe_d</description>
12004 <description>Specifies value of eFUSE control signal strobe_e</description>
12010 <description>Specifies value of eFUSE control signal strobe_f</description>
12016 <description>Specifies value of eFUSE control signal strobe_g</description>
12022 …<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches…
12030 <description>Sequencer program control 4</description>
12039 …description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing…
12045 <description>Specifies value of eFUSE control signal strobe_a</description>
12051 <description>Specifies value of eFUSEcontrol signal strobe_b</description>
12057 <description>Specifies value of eFUSE control signal strobe_c</description>
12063 <description>Specifies value of eFUSE control signal strobe_d</description>
12069 <description>Specifies value of eFUSE control signal strobe_e</description>
12075 <description>Specifies value of eFUSE control signal strobe_f</description>
12081 <description>Specifies value of eFUSE control signal strobe_g</description>
12087 …<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches…
12095 <description>Sequencer program control 5</description>
12104 …description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing…
12110 <description>Specifies value of eFUSE control signal strobe_a</description>
12116 <description>Specifies value of eFUSEcontrol signal strobe_b</description>
12122 <description>Specifies value of eFUSE control signal strobe_c</description>
12128 <description>Specifies value of eFUSE control signal strobe_d</description>
12134 <description>Specifies value of eFUSE control signal strobe_e</description>
12140 <description>Specifies value of eFUSE control signal strobe_f</description>
12146 <description>Specifies value of eFUSE control signal strobe_g</description>
12152 …<description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches…
12162 <description>Energy Profiler IP</description>
12172 <description>Profile control</description>
12181 <description>Specifies the profiling time window mode:
12184 … long as the start 'trigger' signal is active. The stop trigger signal has no effect.</description>
12190 <description>Enables the profiling block:
12192 '1': Enabled.</description>
12200 <description>Profile status</description>
12209 <description>Indicates if the profiling time window is active.
12211 '1': Active.</description>
12219 <description>Profile command</description>
12228 …<description>Software start trigger for the profiling time window. When written with '1', the prof…
12230 Has no effect in enable mode (PROFILE_WIN_MODE=1).</description>
12236 …<description>Software stop trigger for the profiling time window. When written with '1', the profi…
12238 Has no effect in enable mode (PROFILE_WIN_MODE=1).</description>
12244 …<description>Counter clear. When written with '1', all profiling counter registers are cleared to …
12252 <description>Profile interrupt</description>
12261 …<description>This interrupt cause field is activated (HW sets the field to '1') when an profiling …
12263 …eld to clear this bit to '0' (writing 0xFFFFFFFF clears all interrupt causes to '0').</description>
12271 <description>Profile interrupt set</description>
12280 …<description>SW writes a '1' to a bit of this field to set the corresponding bit in the INTR regis…
12288 <description>Profile interrupt mask</description>
12297 <description>Mask bit for corresponding field in the INTR register.</description>
12305 <description>Profile interrupt masked</description>
12314 <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
12324 <description>Profile counter structure</description>
12328 <description>Profile counter configuration</description>
12337 …<description>This field specifies if events (edges) or a duration of the monitor signal is counted.
12341 …are, therefore a selection of CTL.CNT_DURATION=1 will not produce meaningful results.</description>
12347 …description>This field specifies the reference clock used for a counting time base when counting d…
12353 …description>Timer clock (divided or undivided high frequency clock, e.g. from IMO). Selection is d…
12358 <description>IMO - Internal Main Oscillator</description>
12363 <description>ECO - External-Crystal Oscillator</description>
12368 <description>Low frequency clock (ILO, WCO or ALTLF).
12369 Selection is done in SRSS register CLK_SELECT.LFCLK_SEL.</description>
12374 <description>High frequuency clock ('clk_hfx').</description>
12379 <description>Peripheral clock ('clk_peri').</description>
12384 <description>N/A</description>
12389 <description>N/A</description>
12396 …<description>This field specifies the montior input signal to be observed by the profiling counter.
12397 …s are product specific, see product definition spreadsheet tab 'Monitor' for details.</description>
12403 <description>Enables the profiling counter:
12405 '1': Enabled.</description>
12413 <description>Profile counter value</description>
12422 …description>This field shows / specifies the actual value of the profiling counter. It allows read…
12433 <description>High Speed IO Matrix (HSIOM)</description>
12445 <description>HSIOM port registers</description>
12449 <description>Port selection 0</description>
12458 <description>Selects connection for IO pin 0 route.</description>
12464 <description>GPIO controls 'out'</description>
12469 <description>GPIO controls 'out', DSI controls 'output enable'</description>
12474 <description>DSI controls 'out' and 'output enable'</description>
12479 <description>DSI controls 'out', GPIO controls 'output enable'</description>
12484 <description>Analog mux bus A</description>
12489 <description>Analog mux bus B</description>
12494 <description>Analog mux bus A, DSI control</description>
12499 <description>Analog mux bus B, DSI control</description>
12504 <description>Active functionality 0</description>
12509 <description>Active functionality 1</description>
12514 <description>Active functionality 2</description>
12519 <description>Active functionality 3</description>
12524 <description>DeepSleep functionality 0</description>
12529 <description>DeepSleep functionality 1</description>
12534 <description>DeepSleep functionality 2</description>
12539 <description>DeepSleep functionality 3</description>
12544 <description>Active functionality 4</description>
12549 <description>Active functionality 5</description>
12554 <description>Active functionality 6</description>
12559 <description>Active functionality 7</description>
12564 <description>Active functionality 8</description>
12569 <description>Active functionality 9</description>
12574 <description>Active functionality 10</description>
12579 <description>Active functionality 11</description>
12584 <description>Active functionality 12</description>
12589 <description>Active functionality 13</description>
12594 <description>Active functionality 14</description>
12599 <description>Active functionality 15</description>
12604 <description>DeepSleep functionality 4</description>
12609 <description>DeepSleep functionality 5</description>
12614 <description>DeepSleep functionality 6</description>
12619 <description>DeepSleep functionality 7</description>
12626 <description>Selects connection for IO pin 1 route.</description>
12632 <description>Selects connection for IO pin 2 route.</description>
12638 <description>Selects connection for IO pin 3 route.</description>
12646 <description>Port selection 1</description>
12655 <description>Selects connection for IO pin 4 route.
12656 See PORT_SEL0 for connection details.</description>
12662 <description>Selects connection for IO pin 5 route.</description>
12668 <description>Selects connection for IO pin 6 route.</description>
12674 <description>Selects connection for IO pin 7 route.</description>
12685 <description>AMUX splitter cell control</description>
12694 <description>T-switch control for Left AMUXBUSA switch:
12696 '1': switch closed.</description>
12702 <description>T-switch control for Right AMUXBUSA switch:
12704 '1': switch closed.</description>
12710 <description>T-switch control for AMUXBUSA vssa/ground switch:
12712 '1': switch closed.</description>
12718 <description>T-switch control for Left AMUXBUSB switch.</description>
12724 <description>T-switch control for Right AMUXBUSB switch.</description>
12730 <description>T-switch control for AMUXBUSB vssa/ground switch.</description>
12740 <description>GPIO port control/configuration</description>
12752 <description>GPIO port registers</description>
12756 <description>Port output data register</description>
12765 <description>IO output data for pin 0
12767 '1': Output state set to '1'</description>
12773 <description>IO output data for pin 1</description>
12779 <description>IO output data for pin 2</description>
12785 <description>IO output data for pin 3</description>
12791 <description>IO output data for pin 4</description>
12797 <description>IO output data for pin 5</description>
12803 <description>IO output data for pin 6</description>
12809 <description>IO output data for pin 7</description>
12817 <description>Port output data clear register</description>
12826 <description>IO clear output for pin 0:
12828 '1': Output state set to '0'.</description>
12834 <description>IO clear output for pin 1</description>
12840 <description>IO clear output for pin 2</description>
12846 <description>IO clear output for pin 3</description>
12852 <description>IO clear output for pin 4</description>
12858 <description>IO clear output for pin 5</description>
12864 <description>IO clear output for pin 6</description>
12870 <description>IO clear output for pin 7</description>
12878 <description>Port output data set register</description>
12887 <description>IO set output for pin 0:
12889 '1': Output state set to '1'.</description>
12895 <description>IO set output for pin 1</description>
12901 <description>IO set output for pin 2</description>
12907 <description>IO set output for pin 3</description>
12913 <description>IO set output for pin 4</description>
12919 <description>IO set output for pin 5</description>
12925 <description>IO set output for pin 6</description>
12931 <description>IO set output for pin 7</description>
12939 <description>Port output data invert register</description>
12948 <description>IO invert output for pin 0:
12950 '1': Output state inverted ('0' => '1', '1' => '0').</description>
12956 <description>IO invert output for pin 1</description>
12962 <description>IO invert output for pin 2</description>
12968 <description>IO invert output for pin 3</description>
12974 <description>IO invert output for pin 4</description>
12980 <description>IO invert output for pin 5</description>
12986 <description>IO invert output for pin 6</description>
12992 <description>IO invert output for pin 7</description>
13000 <description>Port input state register</description>
13009 <description>IO pin state for pin 0
13012 …to be reflected into IN Register. It's value then depends on the external pin value.</description>
13018 <description>IO pin state for pin 1</description>
13024 <description>IO pin state for pin 2</description>
13030 <description>IO pin state for pin 3</description>
13036 <description>IO pin state for pin 4</description>
13042 <description>IO pin state for pin 5</description>
13048 <description>IO pin state for pin 6</description>
13054 <description>IO pin state for pin 7</description>
13060 …<description>Reads of this register return the logical state of the filtered pin as selected in th…
13068 <description>Port interrupt status register</description>
13077 <description>Edge detect for IO pin 0
13079 '1': An edge was detected on pin.</description>
13085 <description>Edge detect for IO pin 1</description>
13091 <description>Edge detect for IO pin 2</description>
13097 <description>Edge detect for IO pin 3</description>
13103 <description>Edge detect for IO pin 4</description>
13109 <description>Edge detect for IO pin 5</description>
13115 <description>Edge detect for IO pin 6</description>
13121 <description>Edge detect for IO pin 7</description>
13127 … <description>Edge detected on filtered pin selected by INTR_CFG.FLT_SEL</description>
13133 <description>IO pin state for pin 0</description>
13139 <description>IO pin state for pin 1</description>
13145 <description>IO pin state for pin 2</description>
13151 <description>IO pin state for pin 3</description>
13157 <description>IO pin state for pin 4</description>
13163 <description>IO pin state for pin 5</description>
13169 <description>IO pin state for pin 6</description>
13175 <description>IO pin state for pin 7</description>
13181 <description>Filtered pin state for pin selected by INTR_CFG.FLT_SEL</description>
13189 <description>Port interrupt mask register</description>
13198 <description>Masks edge interrupt on IO pin 0
13200 '1': Pin interrupt forwarding enabled</description>
13206 <description>Masks edge interrupt on IO pin 1</description>
13212 <description>Masks edge interrupt on IO pin 2</description>
13218 <description>Masks edge interrupt on IO pin 3</description>
13224 <description>Masks edge interrupt on IO pin 4</description>
13230 <description>Masks edge interrupt on IO pin 5</description>
13236 <description>Masks edge interrupt on IO pin 6</description>
13242 <description>Masks edge interrupt on IO pin 7</description>
13248 … <description>Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL</description>
13256 <description>Port interrupt masked status register</description>
13265 <description>Edge detected AND masked on IO pin 0
13267 '1': Interrupt occurred and was forwarded to CPU</description>
13273 <description>Edge detected and masked on IO pin 1</description>
13279 <description>Edge detected and masked on IO pin 2</description>
13285 <description>Edge detected and masked on IO pin 3</description>
13291 <description>Edge detected and masked on IO pin 4</description>
13297 <description>Edge detected and masked on IO pin 5</description>
13303 <description>Edge detected and masked on IO pin 6</description>
13309 <description>Edge detected and masked on IO pin 7</description>
13315 … <description>Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL</description>
13323 <description>Port interrupt set register</description>
13332 <description>Sets edge detect interrupt for IO pin 0
13334 '1': Interrupt set</description>
13340 <description>Sets edge detect interrupt for IO pin 1</description>
13346 <description>Sets edge detect interrupt for IO pin 2</description>
13352 <description>Sets edge detect interrupt for IO pin 3</description>
13358 <description>Sets edge detect interrupt for IO pin 4</description>
13364 <description>Sets edge detect interrupt for IO pin 5</description>
13370 <description>Sets edge detect interrupt for IO pin 6</description>
13376 <description>Sets edge detect interrupt for IO pin 7</description>
13382 …<description>Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL</description>
13390 <description>Port interrupt configuration register</description>
13399 <description>Sets which edge will trigger an IRQ for IO pin 0</description>
13405 <description>Disabled</description>
13410 <description>Rising edge</description>
13415 <description>Falling edge</description>
13420 <description>Both rising and falling edges</description>
13427 <description>Sets which edge will trigger an IRQ for IO pin 1</description>
13433 <description>Sets which edge will trigger an IRQ for IO pin 2</description>
13439 <description>Sets which edge will trigger an IRQ for IO pin 3</description>
13445 <description>Sets which edge will trigger an IRQ for IO pin 4</description>
13451 <description>Sets which edge will trigger an IRQ for IO pin 5</description>
13457 <description>Sets which edge will trigger an IRQ for IO pin 6</description>
13463 <description>Sets which edge will trigger an IRQ for IO pin 7</description>
13469 …<description>Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG…
13475 <description>Disabled</description>
13480 <description>Rising edge</description>
13485 <description>Falling edge</description>
13490 <description>Both rising and falling edges</description>
13497 …<description>Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe i…
13505 <description>Port configuration register</description>
13514 …<description>The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the …
13517 Note: D_OUT, D_OUT_EN are pins of GPIO cell.</description>
13523 <description>Output buffer is off creating a high impedance input
13525 D_OUT = '1': High Impedance</description>
13530 <description>N/A</description>
13535 <description>Resistive pull up
13551 D_OUT = '1': Weak/resistive pull up</description>
13556 <description>Resistive pull down
13572 D_OUT = '1': Weak/resistive pull down</description>
13577 <description>Open drain, drives low
13593 D_OUT = '1': High Impedance</description>
13598 <description>Open drain, drives high
13614 D_OUT = '1': High Impedance</description>
13619 <description>Strong D_OUTput buffer
13635 D_OUT = '1': High Impedance</description>
13640 <description>Pull up or pull down
13654 D_OUT = '1': Weak/resistive pull up</description>
13661 …<description>Enables the input buffer for IO pin 0. This bit should be cleared when analog signal…
13663 '1': Input buffer enabled</description>
13669 <description>The GPIO drive mode for IO pin 1</description>
13675 <description>Enables the input buffer for IO pin 1</description>
13681 <description>The GPIO drive mode for IO pin 2</description>
13687 <description>Enables the input buffer for IO pin 2</description>
13693 <description>The GPIO drive mode for IO pin 3</description>
13699 <description>Enables the input buffer for IO pin 3</description>
13705 <description>The GPIO drive mode for IO pin4</description>
13711 <description>Enables the input buffer for IO pin 4</description>
13717 <description>The GPIO drive mode for IO pin 5</description>
13723 <description>Enables the input buffer for IO pin 5</description>
13729 <description>The GPIO drive mode for IO pin 6</description>
13735 <description>Enables the input buffer for IO pin 6</description>
13741 <description>The GPIO drive mode for IO pin 7</description>
13747 <description>Enables the input buffer for IO pin 7</description>
13755 <description>Port input buffer configuration register</description>
13764 … <description>Configures the pin 0 input buffer mode (trip points and hysteresis)</description>
13770 … <description>S40S: Input buffer compatible with CMOS and I2C interfaces</description>
13775 … <description>S40S: Input buffer compatible with TTL and MediaLB interfaces</description>
13782 … <description>Configures the pin 1 input buffer mode (trip points and hysteresis)</description>
13788 … <description>Configures the pin 2 input buffer mode (trip points and hysteresis)</description>
13794 … <description>Configures the pin 3 input buffer mode (trip points and hysteresis)</description>
13800 … <description>Configures the pin 4 input buffer mode (trip points and hysteresis)</description>
13806 … <description>Configures the pin 5 input buffer mode (trip points and hysteresis)</description>
13812 … <description>Configures the pin 6 input buffer mode (trip points and hysteresis)</description>
13818 … <description>Configures the pin 7 input buffer mode (trip points and hysteresis)</description>
13826 <description>Port output buffer configuration register</description>
13835 <description>Enables slow slew rate for IO pin 0
13837 '1': Slow slew rate</description>
13843 <description>Enables slow slew rate for IO pin 1</description>
13849 <description>Enables slow slew rate for IO pin 2</description>
13855 <description>Enables slow slew rate for IO pin 3</description>
13861 <description>Enables slow slew rate for IO pin 4</description>
13867 <description>Enables slow slew rate for IO pin 5</description>
13873 <description>Enables slow slew rate for IO pin 6</description>
13879 <description>Enables slow slew rate for IO pin 7</description>
13885 <description>Sets the GPIO drive strength for IO pin 0</description>
13891 … <description>Full drive strength: GPIO drives current at its max rated spec.</description>
13896 … <description>1/2 drive strength: GPIO drives current at 1/2 of its max rated spec</description>
13901 … <description>1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.</description>
13906 … <description>1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.</description>
13913 <description>Sets the GPIO drive strength for IO pin 1</description>
13919 <description>Sets the GPIO drive strength for IO pin 2</description>
13925 <description>Sets the GPIO drive strength for IO pin 3</description>
13931 <description>Sets the GPIO drive strength for IO pin 4</description>
13937 <description>Sets the GPIO drive strength for IO pin 5</description>
13943 <description>Sets the GPIO drive strength for IO pin 6</description>
13949 <description>Sets the GPIO drive strength for IO pin 7</description>
13957 <description>Port SIO configuration register</description>
13966 <description>Selects the output buffer mode:
13969 …regulated output buffer will be disabled and the standard CMOS output buffer is used.</description>
13975 <description>Selects the input buffer mode:
13977 1: Differential input buffer</description>
13983 …<description>Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'…
13988 '1': Trip-point is 0.4*Vddio or 1.0*Vref (depends on VREF_SEL)</description>
13994 <description>Selects reference voltage (Vref) trip-point of the input buffer:
13998 '3': Trip-point reference of AMUXBUS_B</description>
14004 …<description>Selects the regulated Voh output level and trip point of the input buffer for a speci…
14013 Note: The upper value on Voh is limited to Vddio - 400mV</description>
14019 <description>See corresponding definition for IO pins 0 and 1</description>
14025 <description>See corresponding definition for IO pins 0 and 1</description>
14031 <description>See corresponding definition for IO pins 0 and 1</description>
14037 <description>See corresponding definition for IO pins 0 and 1</description>
14043 <description>See corresponding definition for IO pins 0 and 1</description>
14049 <description>See corresponding definition for IO pins 0 and 1</description>
14055 <description>See corresponding definition for IO pins 0 and 1</description>
14061 <description>See corresponding definition for IO pins 0 and 1</description>
14067 <description>See corresponding definition for IO pins 0 and 1</description>
14073 <description>See corresponding definition for IO pins 0 and 1</description>
14079 <description>See corresponding definition for IO pins 0 and 1</description>
14085 <description>See corresponding definition for IO pins 0 and 1</description>
14091 <description>See corresponding definition for IO pins 0 and 1</description>
14097 <description>See corresponding definition for IO pins 0 and 1</description>
14103 <description>See corresponding definition for IO pins 0 and 1</description>
14111 <description>Port GPIO5V input buffer configuration register</description>
14120 …<description>Configures the input buffer mode (trip points and hysteresis) for GPIO5V upper bit. …
14124 Use CFG_IN.VTRIP_SEL0_0 fields set as CMOS only when this bit needs to be set.</description>
14130 … <description>Input buffer not compatible with automotive (elevated Vil) interfaces.</description>
14135 … <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
14142 … <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
14148 … <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
14154 … <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
14160 … <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
14166 … <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
14172 … <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
14178 … <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
14187 <description>Interrupt port cause register 0</description>
14196 …<description>Each IO port has an associated bit field in this register. The bit field reflects the…
14198 '1': Port has pending interrupt</description>
14206 <description>Interrupt port cause register 1</description>
14215 …<description>Each IO port has an associated bit field in this register. The bit field reflects the…
14217 '1': Port has pending interrupt</description>
14225 <description>Interrupt port cause register 2</description>
14234 …<description>Each IO port has an associated bit field in this register. The bit field reflects the…
14236 '1': Port has pending interrupt</description>
14244 <description>Interrupt port cause register 3</description>
14253 …<description>Each IO port has an associated bit field in this register. The bit field reflects the…
14255 '1': Port has pending interrupt</description>
14263 <description>Extern power supply detection register</description>
14272 …<description>Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the d…
14283 5: vddusb'</description>
14289 <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
14295 …description>This bit indicates presence of the VDDD supply. This bit will always read-back 1. Th…
14303 <description>Supply detection interrupt register</description>
14312 <description>Supply state change detected.
14314 '1': Change to supply detected</description>
14320 <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
14326 …<description>The VDDD supply is always present during operation so a supply transition can not occ…
14334 <description>Supply detection interrupt mask register</description>
14343 <description>Masks supply interrupt on VDDIO.
14345 '1': VDDIO interrupt forwarding enabled</description>
14351 <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
14357 <description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
14365 <description>Supply detection interrupt masked register</description>
14374 <description>Supply transition detected AND masked
14376 '1': Interrupt occurred and was forwarded to CPU</description>
14382 <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
14388 <description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
14396 <description>Supply detection interrupt set register</description>
14405 <description>Sets supply interrupt.
14407 '1': Interrupt set</description>
14413 <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
14419 <description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
14429 <description>Programmable IO configuration</description>
14441 <description>Programmable IO port registers</description>
14445 <description>Control register</description>
14454 …<description>Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. Wh…
14456 '1': Bypass (programmable SMARTIOIO fabric is hidden).</description>
14462 <description>Clock ('clk_fabric') and reset ('rst_fabric_n') source selection:
14476 …ockless) mode clk_sys is used to enable the block, but is not available for clocking.</description>
14482 …<description>IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO …
14486 …ctionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode).</description>
14492 <description>Enable for pipeline register:
14494 '1': Enabled.</description>
14500 …<description>Enable for programmable IO. Should only be set to '1' when the programmable IO is com…
14507 …e IO pins' input synchronizer states are flushed when the fabric is fully functional.</description>
14515 <description>Synchronization control register</description>
14524 …<description>Synchronization of the IO pin input signals to 'clk_fabric', one bit for each IO pin:…
14526 '1': Synchronization.</description>
14532 …<description>Synchronization of the chip input signals to 'clk_fabric', one bit for each input: CH…
14534 '1': Synchronization.</description>
14544 <description>LUT component input selection</description>
14553 <description>LUT input signal 'tr0_in' source selection:
14569 '15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7).</description>
14575 <description>LUT input signal 'tr1_in' source selection:
14591 '15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7).</description>
14597 …<description>LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL.<…
14607 <description>LUT component control register</description>
14616 …description>LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (ca…
14622 <description>LUT opcode specifies the LUT operation:
14640 lut_reg <= if (clr) '0' else if (set) '1'</description>
14648 <description>Data unit component input selection</description>
14657 <description>Data unit input signal 'tr0_in' source selection:
14662 Otherwise: Undefined.</description>
14668 …<description>Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_…
14674 …<description>Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_…
14680 <description>Data unit input data 'data0_in' source selection:
14684 '3': DATA.DATA MMIO register field.</description>
14690 …<description>Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA…
14698 <description>Data unit component control register</description>
14707 …<description>Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is…
14713 <description>Data unit opcode specifies the data unit operation:
14725 Otherwise: Undefined.</description>
14733 <description>Data register</description>
14742 <description>Data unit input data source.</description>
14753 <description>Low Power Comparators</description>
14763 <description>LPCOMP Configuration Register</description>
14772 …description>Enable the local reference generator circuit to generate the local Vref and ibias. Thi…
14778 …<description>- 0: IP disabled (put analog in power down, open all switches, all clocks off, leakag…
14779 - 1: IP enabled</description>
14787 <description>LPCOMP Status Register</description>
14796 <description>Current output value of the comparator 0.</description>
14802 <description>Current output value of the comparator 1.</description>
14810 <description>LPCOMP Interrupt request register</description>
14819 …<description>Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Writ…
14825 …<description>Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Writ…
14833 <description>LPCOMP Interrupt set register</description>
14842 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
14848 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
14856 <description>LPCOMP Interrupt request mask</description>
14865 … <description>Mask bit for corresponding bit in interrupt request register.</description>
14871 … <description>Mask bit for corresponding bit in interrupt request register.</description>
14879 <description>LPCOMP Interrupt request masked</description>
14888 <description>Logical and of corresponding request and mask bits.</description>
14894 <description>Logical and of corresponding request and mask bits.</description>
14902 <description>Comparator 0 control Register</description>
14911 <description>Operating mode for the comparator</description>
14917 <description>Off</description>
14922 …description>Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSlee…
14927 …<description>Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref f…
14932 …<description>Normal, full speed power operating mode (uses <150uA). In this mode the iref from …
14939 <description>Add 30mV hysteresis to the comparator
14941 1= Enable Hysteresis</description>
14947 <description>Sets which edge will trigger an IRQ</description>
14953 <description>Disabled, no interrupts will be detected</description>
14958 <description>Rising edge</description>
14963 <description>Falling edge</description>
14968 <description>Both rising and falling edges</description>
14975 …<description>Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize …
14976 …epSleep mode this bit needs to be set to observe the DSI output on the dedicated pin.</description>
14982 … <description>Synchronous comparator DSI (trigger) output : 0=pulse, 1=level</description>
14990 <description>Comparator 0 switch control</description>
14999 <description>Comparator 0 positive terminal isolation switch to GPIO</description>
15005 <description>Comparator 0 positive terminal switch to amuxbusA</description>
15011 <description>Comparator 0 positive terminal switch to amuxbusB</description>
15017 <description>Comparator 0 negative terminal isolation switch to GPIO</description>
15023 <description>Comparator 0 negative terminal switch to amuxbusA</description>
15029 <description>Comparator 0 negative terminal switch to amuxbusB</description>
15035 …<description>Comparator 0 negative terminal switch to local Vref (LPREF_EN must be set)</descrip…
15043 <description>Comparator 0 switch control clear</description>
15052 <description>see corresponding bit in CMP0_SW</description>
15058 <description>see corresponding bit in CMP0_SW</description>
15064 <description>see corresponding bit in CMP0_SW</description>
15070 <description>see corresponding bit in CMP0_SW</description>
15076 <description>see corresponding bit in CMP0_SW</description>
15082 <description>see corresponding bit in CMP0_SW</description>
15088 <description>see corresponding bit in CMP0_SW</description>
15096 <description>Comparator 1 control Register</description>
15105 <description>Operating mode for the comparator</description>
15111 <description>Off</description>
15116 …description>Ultra lowpower operating mode (uses less power, < 300nA), must be used for DeepSlee…
15121 …<description>Low Power operating mode (uses more power, <10uA @@@ TBD). In this mode the iref f…
15126 …<description>Normal, full speed power operating mode (uses <150uA). In this mode the iref from …
15133 <description>Add 30mV hysteresis to the comparator
15135 1= Enable Hysteresis</description>
15141 <description>Sets which edge will trigger an IRQ</description>
15147 <description>Disabled, no interrupts will be detected</description>
15152 <description>Rising edge</description>
15157 <description>Falling edge</description>
15162 <description>Both rising and falling edges</description>
15169 …<description>Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize …
15170 …epSleep mode this bit needs to be set to observe the DSI output on the dedicated pin.</description>
15176 … <description>Synchronous comparator DSI (trigger) output : 0=pulse, 1=level</description>
15184 <description>Comparator 1 switch control</description>
15193 <description>Comparator 1 positive terminal isolation switch to GPIO</description>
15199 <description>Comparator 1 positive terminal switch to amuxbusA</description>
15205 <description>Comparator 1 positive terminal switch to amuxbusB</description>
15211 <description>Comparator 1 negative terminal isolation switch to GPIO</description>
15217 <description>Comparator 1 negative terminal switch to amuxbusA</description>
15223 <description>Comparator 1 negative terminal switch to amuxbusB</description>
15229 …<description>Comparator 1 negative terminal switch to local Vref (LPREF_EN must be set)</descrip…
15237 <description>Comparator 1 switch control clear</description>
15246 <description>see corresponding bit in CMP1_SW</description>
15252 <description>see corresponding bit in CMP1_SW</description>
15258 <description>see corresponding bit in CMP1_SW</description>
15264 <description>see corresponding bit in CMP1_SW</description>
15270 <description>see corresponding bit in CMP1_SW</description>
15276 <description>see corresponding bit in CMP1_SW</description>
15282 <description>see corresponding bit in CMP1_SW</description>
15292 <description>Capsense Controller</description>
15303 <description>Configuration and Control</description>
15312 <description>Select Iref supply.</description>
15318 <description>select SRSS Iref (default)</description>
15323 … <description>select PASS.AREF Iref, only available if PASS IP is on the chip.</description>
15330 …<description>This value determines the number of cycles that the digital filter makes the CSDCMP o…
15331 …f each measurement and from the first comparator trip to the end of each measurement.</description>
15337 … <description>Selects the delay by which csd_shield is delayed relative to csd_sense.</description>
15343 <description>Delay line is off, csd_shield=csd_sense</description>
15348 <description>Introduces a 5ns delay (typ)</description>
15353 <description>Introduces a 10ns delay (typ)</description>
15358 <description>Introduces a 20ns delay (typ)</description>
15365 <description>Enables the sense modulator output.
15367 1: switches and IDAC can be closed/on as per MMIO setting and CSD sequencer.</description>
15373 <description>Enables full wave cap sensing mode</description>
15379 <description>Half Wave mode (normal).
15380 …ame direction (positive or negative edge) and the same Vref, i.e. no polarity change.</description>
15385 <description>Full Wave mode.
15386 …in opposite direction and with different Vref in each phase, i.e. the polarity flips.</description>
15393 <description>Enables mutual cap sensing mode</description>
15399 <description>Self-cap mode (configure sense line as CSD_SENSE)</description>
15404 …description>Mutual-cap mode (configure Tx line as CSD_SENSE, inverted Tx line as CSD_SHIELD and Rx…
15411 …<description>Enable the use of two counters for MUTUAL cap sensing mode (CSX), do not use when MUT…
15417 <description>Use one counter for both phases (source and sink).</description>
15422 …<description>Use two counters, separate count for when csd_sense is high and when csd_sense is low…
15429 <description>Select what to output on the dsi_count bus.</description>
15435 …description>depending on the dsi_count_val_sel input either output RESULT_VAL1.VALUE (0) or RESUL…
15440 <description>output ADC_RES.VIN_CNT on the dsi_count bus</description>
15447 …<description>Enables the use of the dsi_sample_in input instead of the comparator output to strobe…
15453 …<description>Enables double synchronizing of sample input from DSI (only relevant when DSI_SAMPLE_…
15459 …description>Enables the use of the dsi_sense_in input instead of the internally generated modulati…
15465 … <description>Select the power mode for the CSD components (REFGEN, AMBUF, CSDCMP, HSCMP):
15467 1: Low Power mode</description>
15473 …<description>Master enable of the CSDv2 IP. Must be set to 1 for any CSDv2, ADC or IDAC operation…
15474 When 0 all analog components will be off and all switches will be open.</description>
15482 <description>Spare MMIO</description>
15491 <description>Spare MMIO</description>
15499 <description>Status Register</description>
15508 <description>Signal used to drive the Cs switches.</description>
15514 …<description>Output of reference buffer comparator used to charge up Cmod and/or Csh_tank (synchro…
15520 <description>Vin < Vref</description>
15525 <description>Vin > Vref</description>
15532 <description>Output of main sensing comparator (synchronized)</description>
15540 <description>Current Sequencer status</description>
15549 <description>CSD sequencer state</description>
15555 …<description>ADC sequencer state (only relevant after SEQ_STATE has reached SAMPLE_NORM and ADC se…
15563 <description>Current status counts</description>
15572 …description>Current number of conversions remaining when in Sample_* states (note that in AutoZero…
15580 <description>Current count of the HSCMP counter</description>
15589 <description>Current value of HSCMP counter</description>
15597 <description>Result CSD/CSX accumulation counter value 1</description>
15606 …description>Accumulated counter value for this result. In case of Mutual cap with two counters (CS…
15612 …description>Number of 'bad' conversion for which the CSD comparator did not trigger within the nor…
15620 <description>Result CSX accumulation counter value 2</description>
15629 …description>Only used in case of Mutual cap with two counters (CSX = config.mutual_cap & confi…
15637 <description>ADC measurement</description>
15646 <description>Count to source/sink Cref1 + Cref2 from Vin to Vrefhi.</description>
15652 … <description>Polarity used for IDACB for this last ADC result, 0= source, 1= sink</description>
15658 …description>This flag is set when the ADC counter overflows. This is an indication to the firmware…
15664 …<description>This flag is set when the ADC sequencer was aborted before tripping HSCMP.</descripti…
15672 <description>CSD Interrupt Request Register</description>
15681 <description>A normal sample is complete</description>
15687 …<description>Coarse initialization complete or Sample initialization complete (the latter is typic…
15693 <description>ADC Result ready</description>
15701 <description>CSD Interrupt set register</description>
15710 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
15716 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
15722 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
15730 <description>CSD Interrupt mask register</description>
15739 … <description>Mask bit for corresponding bit in interrupt request register.</description>
15745 … <description>Mask bit for corresponding bit in interrupt request register.</description>
15751 … <description>Mask bit for corresponding bit in interrupt request register.</description>
15759 <description>CSD Interrupt masked register</description>
15768 <description>Logical and of corresponding request and mask bits.</description>
15774 <description>Logical and of corresponding request and mask bits.</description>
15780 <description>Logical and of corresponding request and mask bits.</description>
15788 <description>High Speed Comparator configuration</description>
15797 <description>High Speed Comparator enable</description>
15803 <description>Disable comparator, output is zero</description>
15808 …<description>On, regular operation. Note that CONFIG.LP_MODE determines the power mode level</desc…
15815 …description>Invert the HSCMP output before it is used to control switches and the CSD sequencer. T…
15821 … <description>Auto-Zero enable, allow the Sequencer to Auto-Zero this component</description>
15829 <description>Reference Generator configuration</description>
15838 <description>Amux buffer power level</description>
15844 <description>Disable buffer</description>
15849 … <description>On, normal or low power level depending on CONFIG.LP_MODE.</description>
15854 … <description>On, high or low power level depending on CONFIG.LP_MODE.</description>
15863 <description>Reference Generator configuration</description>
15872 <description>Reference Generator Enable</description>
15878 <description>Disable Reference Generator</description>
15883 …<description>On, regular operation. Note that CONFIG.LP_MODE determines the power mode level</desc…
15890 <description>Bypass selected input reference unbuffered to Vrefhi</description>
15896 <description>Close Vdda switch to top of resistor string (or Vrefhi?)</description>
15902 …<description>Resistor string enable; 0= open switch on top of the resistor string (Vreflo=Vssa)</d…
15908 …description>Select resistor string tap for feedback, 0= minimum vout, 31= maximum vout = vrefhi -&…
15914 …description>Select resistor string tap for Vreflo/Vreflo_int, 0= minimum vout, 31= maximum vout = …
15920 … <description>Ouput the resistor string tap either to Vreflo (0) or Vreflo_int (1).</description>
15928 <description>CSD Comparator configuration</description>
15937 <description>CSD Comparator Enable</description>
15943 <description>Disable comparator, output is zero</description>
15948 …<description>On, regular operation. Note that CONFIG.LP_MODE determines the power mode level</desc…
15955 … <description>Select which IDAC polarity to use to detect CSDCMP triggering</description>
15961 …description>Use idaca_pol (firmware setting with CSX and optionally DSI mixed in) to determine the…
15966 …description>Use idacb_pol (firmware setting with optional DSI mixed in) to determine the direction…
15971 …description>Use the expression (csd_sense ? idaca_pol : idacb_pol) to determine the direction, th…
15978 …description>Select in what phase(s) the comparator is active, typically set to match the BAL_MODE …
15984 …description>Comparator is active from start of Phi2 and kept active into Phi1. Intended usage: leg…
15989 … <description>Comparator is active during Phi1 only. Currently no known use-case.</description>
15994 … <description>Comparator is active during Phi2 only. Intended usage: CSD Low EMI.</description>
15999 …<description>Comparator is activated at the start of both Phi1 and Phi2 (non-overlap should be ena…
16006 <description>Select which signal to output on dsi_sample_out.</description>
16012 … <description>CSD mode: output the filtered sample signal on dsi_sample_out</description>
16017 …<description>General Purpose mode: output the unfiltered sample unfiltered comparator output, eith…
16024 …description>This bit controls whether the output directly from the comparator (csdcmp_out) or the …
16030 … <description>Use feedback from sampling flip-flop (used in most modes).</description>
16035 …<description>Use feedback from comparator directly (used in single Cmod mutual cap sensing only)</…
16042 … <description>Auto-Zero enable, allow the Sequencer to Auto-Zero this component</description>
16050 <description>Switch Resistance configuration</description>
16059 … <description>Select resistance or low EMI (slow ramp) for the HCAV switch</description>
16065 <description>Low</description>
16070 <description>Medium</description>
16075 <description>High</description>
16080 … <description>Low EMI (slow ramp: 3 switches closed by fixed delay line)</description>
16087 <description>Select resistance or low EMI for the corresponding switch</description>
16093 <description>Select resistance or low EMI for the corresponding switch</description>
16099 <description>Select resistance or low EMI for the corresponding switch</description>
16105 <description>Select resistance for the corresponding switch</description>
16111 <description>Low</description>
16116 <description>Medium</description>
16121 <description>High</description>
16126 <description>N/A</description>
16133 <description>Select resistance for the corresponding switch</description>
16141 <description>Sense clock period</description>
16150 …<description>The length-1 of the Sense modulation 'clock' period in clk_csd cycles. For regular CS…
16153 In addition the FILTER_DELAY needs to be added to the minimum allowed SENSE_DIV value.</description>
16159 …description>Selects the length of the LFSR which determines the LFSR repeat period. LFSR_BITS LSB …
16165 … <description>Don't use clock dithering (=spreadspectrum) (LFSR output value is zero)</description>
16170 <description>6-bit LFSR (G(x)=X^6 +X^4+X^3+ X+1, period= 63)</description>
16175 <description>7-bit LFSR (G(x)=X^7 +X^4+X^3+X^2+1, period= 127)</description>
16180 <description>9-bit LFSR (G(x)=X^9 +X^4+X^3+ X+1, period= 511)</description>
16185 <description>10-bit LFSR (G(x)=X^10+X^4+X^3+ X+1, period= 1023)</description>
16190 <description>8-bit LFSR (G(x)=X^8+X^4+X^3+X^2+1, period= 255)</description>
16195 <description>12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1, period= 4095)</description>
16202 …<description>Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This dither…
16204 … including the dithering term must fit in 12 bits, otherwise the result is undefined.</description>
16210 …<description>When set, forces the LFSR to it's initial state (all ones). This bit is automaticall…
16211 Note that the LFSR will also get reset to all ones during the AutoZero_1/2 states.</description>
16217 …description>Use the MSB of configured LSFR size as csd_sense signal. Intended to be used only with…
16223 …<description>Selects the number of LSB bits to use from the LSFR to provide the clock dithering va…
16224 …imum absolute range (e.g. for 4B SENSE_DIV > 8), otherwise results are undefined.</description>
16230 <description>use 2 bits: range = [-2,1]</description>
16235 <description>use 3 bits: range = [-4,3]</description>
16240 <description>use 4 bits: range = [-8,7]</description>
16245 <description>use 5 bits: range = [-16,15] (default)</description>
16254 <description>Sense clock duty cycle</description>
16263 … <description>Defines the length of the first phase of the sense clock in clk_csd cycles.
16265 Note that this feature is not available when SEL_LFSR_MSB (PRS) is selected.</description>
16271 <description>Polarity of the sense clock
16273 1 = start with high phase</description>
16279 <description>NonOverlap or not for Phi1 (csd_sense=0).
16281 …O switching, the GPIO internal circuit ensures that the switches are non-overlapping.</description>
16287 <description>Same as OVERLAP_PHI1 but for Phi2 (csd_sense=1).</description>
16295 <description>HSCMP Pos input switch Waveform selection</description>
16304 <description>Set HMPM switch
16306 1: static closed</description>
16312 <description>Set corresponding switch</description>
16318 <description>Set corresponding switch</description>
16324 <description>Set corresponding switch</description>
16330 <description>Set corresponding switch</description>
16336 <description>Set corresponding switch</description>
16342 <description>Set corresponding switch</description>
16348 <description>Set corresponding switch</description>
16356 <description>HSCMP Neg input switch Waveform selection</description>
16365 <description>Set corresponding switch</description>
16371 <description>Set corresponding switch</description>
16377 <description>Select waveform for corresponding switch</description>
16383 <description>Select waveform for corresponding switch</description>
16391 <description>Shielding switches Waveform selection</description>
16400 <description>N/A</description>
16406 <description>Select waveform for corresponding switch</description>
16412 <description>N/A</description>
16418 … <description>Select waveform for corresponding switch, using csd_shield as base</description>
16424 <description>Set corresponding switch</description>
16430 <description>Set corresponding switch
16431 If the ADC is enabled then this switch is directly controlled by the ADC sequencer.</description>
16439 <description>Amuxbuffer switches Waveform selection</description>
16448 <description>Set corresponding switch</description>
16454 <description>Set corresponding switch</description>
16460 <description>Set corresponding switch</description>
16466 <description>Select waveform for corresponding switch</description>
16472 <description>Set corresponding switch</description>
16478 <description>Set corresponding switch</description>
16484 <description>Set corresponding switch</description>
16492 <description>AMUXBUS bypass switches Waveform selection</description>
16501 <description>Set corresponding switch</description>
16507 <description>Set corresponding switch</description>
16513 <description>Set corresponding switch
16514 If the ADC is enabled then this switch is directly controlled by the ADC sequencer.</description>
16522 <description>CSDCMP Pos Switch Waveform selection</description>
16531 <description>Select waveform for corresponding switch</description>
16537 <description>Select waveform for corresponding switch</description>
16543 <description>Select waveform for corresponding switch</description>
16549 <description>Set corresponding switch</description>
16555 <description>Set corresponding switch</description>
16561 <description>Set corresponding switch</description>
16567 <description>Set corresponding switch</description>
16575 <description>CSDCMP Neg Switch Waveform selection</description>
16584 <description>Select waveform for corresponding switch</description>
16590 <description>Select waveform for corresponding switch</description>
16598 <description>Reference Generator Switch Waveform selection</description>
16607 <description>Set corresponding switch</description>
16613 <description>Set corresponding switch</description>
16619 <description>Set corresponding switch</description>
16625 <description>Set corresponding switch</description>
16631 <description>Set corresponding switch</description>
16637 <description>Set corresponding switch</description>
16645 <description>Full Wave Cmod Switch Waveform selection</description>
16654 <description>Set corresponding switch</description>
16660 <description>Select waveform for corresponding switch</description>
16666 <description>Select waveform for corresponding switch</description>
16672 <description>Set corresponding switch</description>
16678 <description>Set corresponding switch</description>
16684 <description>Set corresponding switch</description>
16692 <description>Full Wave Csh_tank Switch Waveform selection</description>
16701 <description>Set corresponding switch</description>
16707 <description>Select waveform for corresponding switch</description>
16713 <description>Select waveform for corresponding switch</description>
16719 <description>Select waveform for corresponding switch</description>
16725 <description>Set corresponding switch</description>
16731 <description>Set corresponding switch</description>
16737 <description>Set corresponding switch</description>
16745 <description>DSI output switch control Waveform selection</description>
16754 <description>Select waveform for dsi_csh_tank output signal
16772 15: sense // = phi2 but ignores OVERLAP_PHI2</description>
16778 <description>Select waveform for dsi_cmod output signal</description>
16786 <description>IO output control Waveform selection</description>
16795 <description>Select waveform for csd_tx_out output signal</description>
16801 <description>Select waveform for csd_tx_out_en output signal</description>
16807 <description>Select waveform for csd_tx_amuxb_en output signal</description>
16813 <description>Select waveform for csd_tx_n_out output signal</description>
16819 <description>Select waveform for csd_tx_n_out_en output signal</description>
16825 <description>Select waveform for csd_tx_n_amuxa_en output signal</description>
16833 <description>Sequencer Timing</description>
16842 <description>Define Auto-Zero time in csd_sense cycles -1.</description>
16850 <description>Sequencer Initial conversion and sample counts</description>
16859 …<description>Number of conversion per Initialization sample, if set to 0 the Sample_init state wil…
16867 <description>Sequencer Normal conversion and sample counts</description>
16876 … <description>Number of conversion per sample, if set to 0 the Sample_norm state will be skipped.
16878 Note for CSDv1 Sample window size = PERIOD</description>
16886 <description>ADC Control</description>
16895 …description>ADC timing -1 in csd_sense clock cycles (actual time is ADC_TIME+1 cycles), either use…
16901 …<description>Enable ADC measurement. When enabled the ADC sequencer will be started when the main …
16907 <description>No ADC measurement</description>
16912 … <description>Count time A to bring Cref1 + Cref2 up from Vssa to Vrefhi with IDACB</description>
16917 …description>Count time B to bring Cref1 + Cref2 back up to Vrefhi with IDACB (after bringing them …
16922 …<description>Determine HSCMP polarity and count time C to source/sink Cref1 + Cref2 from Vin to Vr…
16931 <description>Sequencer start</description>
16940 …description>Start the CSD sequencer. The sequencer will clear this bit when it is done. Depending …
16946 <description>0 = regular CSD scan + optional ADC
16947 1 = coarse initialization, the Sequencer will go to the INIT_COARSE state.</description>
16953 …description>When a 1 is written the CSD and ADC sequencers will be aborted (if they are running) a…
16959 …<description>When this bit is set a positive edge on dsi_start will start the CSD sequencer and if…
16965 <description>When set the AutoZero_0 state will be skipped</description>
16971 <description>When set the AutoZero_1 state will be skipped</description>
16979 <description>IDACA Configuration</description>
16988 <description>Current value setting for this IDAC (7 bits).</description>
16994 …<description>Polarity is dynamic, this bit does not influence the logic in the SoftIP, it only goe…
17000 …description>Static polarity. Polarity is expected to be stable, so to save power this avoids the s…
17005 …description>Dynamic polarity. Polarity is expected to change frequently (e.g. invert after every c…
17012 …description>Selects the polarity of the IDAC (sensing operation). Normally the actual polarity dep…
17018 …<description>Normal: switch between Vssa and Cmod. For non-CSD application, IDAC will source curr…
17023 …<description>Inverted: switch between Vdda and Cmod. For non-CSD application, IDAC will sink curre…
17028 …description>The polarity of the IDAC will follow the csd_sense signal (POL_DYN bit should be set t…
17033 …description>The polarity of the IDAC will follow the inverted csd_sense signal (POL_DYN bit should…
17040 <description>Balancing mode: only applies to legs configured as CSD.</description>
17046 …description>enabled from start of Phi2 until disabled by CSDCMP. Intended usage: legacy CSD for ba…
17051 …description>enabled from start of Phi1 and disabled by CSDCMP or at end of Phi1. Enables dual IDAC…
17056 …description>enabled from start of Phi2 and disabled by CSDCMP or at end of Phi2. Intended usage: C…
17061 …description>enabled from start of both Phi1 and Phi2 and disabled by CSDCMP or at end of Phi1 or P…
17068 <description>Controls the usage mode of LEG1 and the Polarity bit</description>
17074 …description>General Purpose static mode: LEG1 and POLARITY are controlled by MMIO and optionally m…
17079 …description>General Purpose dynamic mode: LEG1 and POLARITY are controlled by MMIO and optionally …
17084 …description>CSD static mode: LEG1 can only be on when the CSD Sequencer is in the Sample_init or S…
17089 …description>CSD dynamic mode: LEG1 can only be on when the CSD Sequencer is in the Sample_init or …
17096 <description>Controls the usage mode of LEG2</description>
17102 …description>General Purpose static mode: LEG2 is controlled by MMIO and optionally mixed with DSI …
17107 …description>General Purpose dynamic mode: LEG2 is controlled by MMIO and optionally mixed with DSI…
17112 …description>CSD static mode: LEG2 can only be on when the CSD Sequencer is in the Sample_init or S…
17117 …description>CSD dynamic mode: LEG2 can only be on when the CSD Sequencer is in the Sample_init or …
17124 …<description>Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if e…
17132 IDACA_LEG2_EN = IDACA.LEG2_EN AND dsi_idaca_leg2_en</description>
17138 <description>IDAC multiplier</description>
17144 <description>1 LSB = 37.5 nA</description>
17149 <description>1 LSB = 300 nA</description>
17154 <description>1 LSB = 2400 nA</description>
17161 <description>output enable for leg 1 to CSDBUSA</description>
17167 <description>output enable for leg 2 to CSDBUSA</description>
17175 <description>IDACB Configuration</description>
17184 <description>Current value setting for this IDAC (7 bits).</description>
17190 …<description>Polarity is dynamic, this bit does not influence the logic in the SoftIP, it only goe…
17196 …description>Static polarity. Polarity is expected to be stable, so to save power this avoids the s…
17201 …description>Dynamic polarity. Polarity is expected to change frequently (e.g. invert after every c…
17208 …description>Selects the polarity of the IDAC (sensing operation). Normally the actual polarity dep…
17214 …<description>Normal: switch between Vssa and Cmod. For non-CSD application, IDAC will source curr…
17219 …<description>Inverted: switch between Vdda and Cmod. For non-CSD application, IDAC will sink curre…
17224 …description>The polarity of the IDAC will follow the csd_sense signal (POL_DYN bit should be set t…
17229 …description>The polarity of the IDAC will follow the inverted csd_sense signal (POL_DYN bit should…
17236 <description>same as corresponding IDACA Balancing mode</description>
17242 <description>same as corresponding IDACA Balancing mode</description>
17247 <description>same as corresponding IDACA Balancing mode</description>
17252 <description>same as corresponding IDACA Balancing mode</description>
17257 <description>same as corresponding IDACA Balancing mode</description>
17264 <description>Controls the usage mode of LEG1 and the Polarity bit</description>
17270 <description>same as corresponding IDACA.LEG1_MODE</description>
17275 <description>same as corresponding IDACA.LEG1_MODE</description>
17280 <description>same as corresponding IDACA.LEG1_MODE</description>
17285 <description>same as corresponding IDACA.LEG1_MODE</description>
17292 <description>Controls the usage mode of LEG2</description>
17298 <description>same as corresponding IDACA.LEG2_MODE</description>
17303 <description>same as corresponding IDACA.LEG2_MODE</description>
17308 <description>same as corresponding IDACA.LEG2_MODE</description>
17313 <description>same as corresponding IDACA.LEG2_MODE</description>
17320 …<description>Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if e…
17330 IDACB_LEG3_EN = IDACB.LEG3_EN AND dsi_idacb_leg3_en</description>
17336 <description>IDAC multiplier</description>
17342 <description>1 LSB = 37.5 nA</description>
17347 <description>1 LSB = 300 nA</description>
17352 <description>1 LSB = 2400 nA</description>
17359 <description>output enable for leg 1 to CSDBUSB or CSDBUSA</description>
17365 <description>output enable for leg 2 to CSDBUSB or CSDBUSA</description>
17371 …<description>output enable for leg3 to CSDBUSC, only allowed when RANGE = IDAC_LO. When this bit i…
17373 When LEG3_EN=1 also the IDACB polarity is controlled by the ADC sequencer.</description>
17383 <description>Timer/Counter/PWM</description>
17394 <description>TCPWM control register</description>
17403 <description>Counter enables for counters 0 up to CNT_NR-1.
17412 …LR registers to avoid race-conditions on read-modify-write attempts to this register.</description>
17420 <description>TCPWM control clear register</description>
17429 <description>Alias of CTRL that only allows disabling of counters. A write access:
17433 A read access returns CTRL.COUNTER_ENABLED.</description>
17441 <description>TCPWM control set register</description>
17450 <description>Alias of CTRL that only allows enabling of counters. A write access:
17454 A read access returns CTRL.COUNTER_ENABLED.</description>
17462 <description>TCPWM capture command register</description>
17471 …description>Counters SW capture trigger. When written with '1', a capture trigger is generated and…
17479 <description>TCPWM reload command register</description>
17488 … <description>Counters SW reload trigger. For HW behavior, see COUNTER_CAPTURE field.</description>
17496 <description>TCPWM stop command register</description>
17505 … <description>Counters SW stop trigger. For HW behavior, see COUNTER_CAPTURE field.</description>
17513 <description>TCPWM start command register</description>
17522 … <description>Counters SW start trigger. For HW behavior, see COUNTER_CAPTURE field.</description>
17530 <description>TCPWM Counter interrupt cause register</description>
17539 …description>Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENAB…
17549 <description>Timer/Counter/PWM Counter Module</description>
17553 <description>Counter control register</description>
17562 …<description>Specifies switching of the CC and buffered CC values. This field has a function in TI…
17568 '1': switch on a terminal count event with an actively pending switch event.</description>
17574 …<description>Specifies switching of the PERIOD and buffered PERIOD values. This field has a functi…
17576 '1': switch on a terminal count event with and actively pending switch event.</description>
17582 <description>Specifies asynchronous/synchronous kill behavior:
17586 …n in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.</description>
17592 <description>Specifies whether the counter stops on a kill events:
17596 This field has a function in PWM, PWM_DT and PWM_PR modes only.</description>
17602 …description>Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead …
17608 <description>Determines counter direction.</description>
17614 …description>Count up (to PERIOD). An overflow event is generated when the counter changes from a s…
17619 …description>Count down (to '0'). An underflow event is generated when the counter changes from a …
17624 …description>Count up (to PERIOD), then count down (to '0'). An overflow event is generated when th…
17629 …description>Count up (to PERIOD), then count down (to '0'). An overflow event is generated when th…
17636 …<description>When '0', counter runs continuous. When '1', counter is turned off by hardware when a…
17642 <description>In QUAD mode selects quadrature encoding mode (X1/X2/X4).
17643 …E[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].</description>
17649 <description>X1 encoding (QUAD mode)</description>
17654 <description>X2 encoding (QUAD mode)</description>
17659 <description>X4 encoding (QUAD mode)</description>
17666 <description>Counter mode.</description>
17672 <description>Timer mode</description>
17677 <description>Capture mode</description>
17682 <description>Quadrature encoding mode</description>
17687 <description>Pulse width modulation (PWM) mode</description>
17692 <description>PWM with deadtime insertion mode</description>
17697 <description>Pseudo random pulse width modulation</description>
17706 <description>Counter status register</description>
17715 …description>When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, th…
17721 …description>Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insert…
17727 … <description>When '0', the counter is NOT running. When '1', the counter is running.</description>
17735 <description>Counter count register</description>
17744 …<description>16-bit / 32-bit counter value. It is advised to not write to this field when the coun…
17752 <description>Counter compare/capture register</description>
17761 …<description>In CAPTURE mode, captures the counter value. In other modes, compared to counter valu…
17769 <description>Counter buffered compare/capture register</description>
17778 <description>Additional buffer for counter CC register.</description>
17786 <description>Counter period register</description>
17795 …<description>Period value: upper value of the counter. When the counter should count for n cycles,…
17803 <description>Counter buffered period register</description>
17812 <description>Additional buffer for counter PERIOD register.</description>
17820 <description>Counter trigger control register 0</description>
17829 …description>Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '…
17835 …description>Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the fir…
17841 …description>Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the in…
17847 …description>Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR mode…
17853 …<description>Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the se…
17861 <description>Counter trigger control register 1</description>
17870 … <description>A capture event will copy the counter value into the CC register.</description>
17876 <description>Rising edge. Any rising edge generates an event.</description>
17881 <description>Falling edge. Any falling edge generates an event.</description>
17886 … <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
17891 <description>No edge detection, use trigger as is.</description>
17898 … <description>A counter event will increase or decrease the counter by '1'.</description>
17904 <description>Rising edge. Any rising edge generates an event.</description>
17909 <description>Falling edge. Any falling edge generates an event.</description>
17914 … <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
17919 <description>No edge detection, use trigger as is.</description>
17926 …description>A reload event will initialize the counter. When counting up, the counter is initializ…
17932 <description>Rising edge. Any rising edge generates an event.</description>
17937 <description>Falling edge. Any falling edge generates an event.</description>
17942 … <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
17947 <description>No edge detection, use trigger as is.</description>
17954 …<description>A stop event, will stop the counter; i.e. it will no longer be running. Stopping will…
17960 <description>Rising edge. Any rising edge generates an event.</description>
17965 <description>Falling edge. Any falling edge generates an event.</description>
17970 … <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
17975 <description>No edge detection, use trigger as is.</description>
17982 …description>A start event will start the counter; i.e. the counter will become running. Starting d…
17988 <description>Rising edge. Any rising edge generates an event.</description>
17993 <description>Falling edge. Any falling edge generates an event.</description>
17998 … <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
18003 <description>No edge detection, use trigger as is.</description>
18012 <description>Counter trigger control register 2</description>
18021 …<description>Determines the effect of a compare match event (COUNTER equals CC register) on the 'l…
18022 …le, the counter CC register should be set to larger than the counter PERIOD register.</description>
18028 <description>Set to '1'</description>
18033 <description>Set to '0'</description>
18038 <description>Invert</description>
18043 <description>No Change</description>
18050 …<description>Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'li…
18056 <description>Set to '1'</description>
18061 <description>Set to '0'</description>
18066 <description>Invert</description>
18071 <description>No Change</description>
18078 …<description>Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line…
18084 <description>Set to '1'</description>
18089 <description>Set to '0'</description>
18094 <description>Invert</description>
18099 <description>No Change</description>
18108 <description>Interrupt request register</description>
18117 …<description>Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit…
18123 …<description>Counter matches CC register event. Set to '1', when event is detected. Write with '1'…
18131 <description>Interrupt set request register</description>
18140 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
18146 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
18154 <description>Interrupt mask register</description>
18163 … <description>Mask bit for corresponding bit in interrupt request register.</description>
18169 … <description>Mask bit for corresponding bit in interrupt request register.</description>
18177 <description>Interrupt masked request register</description>
18186 <description>Logical and of corresponding request and mask bits.</description>
18192 <description>Logical and of corresponding request and mask bits.</description>
18207 <description>LCD Controller Block</description>
18218 <description>ID & Revision</description>
18227 <description>the ID of LCD controller peripheral is 0xF0F0</description>
18233 <description>the version number is 0x0001</description>
18241 <description>LCD Divider Register</description>
18250 …description>Input clock frequency divide value, to generate the 1/4 sub-frame period. The sub-fram…
18256 …<description>Length of the dead time period in cycles. When set to zero, no dead time period exi…
18264 <description>LCD Configuration Register</description>
18273 <description>Low speed (LS) generator enable
18275 0: disable</description>
18281 <description>High speed (HS) generator enable
18283 0: disable</description>
18289 <description>HS/LS Mode selection</description>
18295 …<description>Select Low Speed (32kHz) Generator (Works in Active, Sleep and DeepSleep power modes)…
18300 …<description>Select High Speed (system clock) Generator (Works in Active and Sleep power modes onl…
18307 <description>LCD driving waveform type configuration.</description>
18313 …<description>Type A - Each frame addresses each COM pin only once with a balanced (DC=0) waveform.…
18318 …description>Type B - Each frame addresses each COM pin twice in sequence with a positive and negat…
18325 <description>Driving mode configuration</description>
18331 <description>PWM Mode</description>
18336 <description>Digital Correlation Mode</description>
18343 <description>PWM bias selection</description>
18349 <description>1/2 Bias</description>
18354 <description>1/3 Bias</description>
18359 <description>1/4 Bias (not supported by LS generator)</description>
18364 <description>1/5 Bias (not supported by LS generator)</description>
18371 <description>The number of COM connections minus 2. So:
18377 15: undefined</description>
18383 …<description>LS enable status bit. This bit is a copy of LS_EN that is synchronized to the low sp…
18388 4. Wait until LS_EN_STAT=0.</description>
18398 <description>LCD Pin Data Registers</description>
18407 …<description>Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb).</descri…
18417 <description>LCD Pin Data Registers</description>
18426 …<description>Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb).</descri…
18436 <description>LCD Pin Data Registers</description>
18445 …<description>Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb).</descr…
18455 <description>LCD Pin Data Registers</description>
18464 …<description>Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb).</des…
18474 <description>Bluetooth Low Energy Subsystem</description>
18484 <description>Radio Control Bus (RCB) controller</description>
18488 <description>RCB control register.</description>
18497 <description>Clock edge used for transmitting (Transmision uses internal core clock)
18499 1: Positive Edge</description>
18505 …<description>Clock edge used for sampling the received data (Sampling uses clock selected by RX_CL…
18508 …e: For RX_CLK_SRC =1, when pad clock is used as sampling clock, this field is ignored</description>
18514 <description>Clock to be used for sampling the received data
18518 When Clock from the SCK pad is used, sampling is always on negedge only</description>
18524 <description>Controls the behaviour of the RCB clock
18526 '1': SCLK is generated, when the RCB controller is enabled.</description>
18532 … <description>Slave select polarity. SSEL_POLARITY applies to the outgoing slave select signal
18534 '1': slave select is high/'1' active.</description>
18540 <description>N/A</description>
18546 <description>N/A</description>
18552 <description>Enable for RCB Clock Divider.
18553 The internal core clock divider is bypassed when DIV_ENABLED=0</description>
18559 <description>The internal core clock divider factor when DIV_ENABLED=1
18561 DIV value of zero is not supported. Make DIV_ENABLED=0 for undivided clock</description>
18567 …description>Width of Address phase (includes read/write mode bit) of the Dataframe width. ADDR_WID…
18573 <description>Width of Data phase of the transmit Dataframe width.
18575 1 - 16 bits</description>
18581 …<description>IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as f…
18586 …use re-initialization of the design and associated state is lost (e.g. FIFO content).</description>
18594 <description>RCB status register.</description>
18603 …<description>RCB bus is busy. The bus is considered busy ('1') during an ongoing transaction.</des…
18611 <description>Transmitter control register.</description>
18620 <description>Least significant bit first ('0') or most significant bit first ('1').
18623 When MSB_FIRST = 0, then [15:0] is for data. No address field</description>
18629 <description>Setting this bit, clears the FIFO and resets the pointer</description>
18635 …<description>This field determines the depth of the TX_FIFO. Allowed legal values are 8 and 16 onl…
18643 <description>Transmitter FIFO control register.</description>
18652 …description>Trigger level. When the transmitter FIFO has less entries than the number of this fiel…
18658 …description>When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated.…
18666 <description>Transmitter FIFO status register.</description>
18675 …<description>Amount of enties in the transmitter FIFO. The value of this field ranges from 0 to 16…
18681 …description>Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). …
18687 …<description>FIFO read pointer: FIFO location from which a data frame is read by the hardware.</de…
18693 … <description>FIFO write pointer: FIFO location at which a new data frame is written.</description>
18701 <description>Transmitter FIFO write register.</description>
18710 …<description>Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH o…
18711 A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'.</description>
18719 <description>Receiver control register.</description>
18728 <description>Least significant bit first ('0') or most significant bit first ('1').
18731 When MSB_FIRST = 0, then [15:0] is for data. No address field</description>
18739 <description>Receiver FIFO control register.</description>
18748 …<description>Trigger level. When the receiver FIFO has more entries than the number of this field,…
18754 …description>When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Inval…
18762 <description>Receiver FIFO status register.</description>
18771 …<description>Amount of enties in the receiver FIFO. The value of this field ranges from 0 to FF_DA…
18777 …description>Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or n…
18783 … <description>FIFO read pointer: FIFO location from which a data frame is read.</description>
18789 …<description>FIFO write pointer: FIFO location at which a new data frame is written by the hardwar…
18797 <description>Receiver FIFO read register.</description>
18806 …<description>Data read from the receiver FIFO. Reading a data frame will remove the data frame fro…
18809 A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'.</description>
18817 <description>Receiver FIFO read register.</description>
18826 …<description>Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame…
18827 A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'.</description>
18835 <description>Master interrupt request register.</description>
18844 …<description>RCB Controller transfer done event. On completion of every RCB transaction, this bit …
18850 … <description>Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.</description>
18856 <description>TX FIFO is not full. entries != TX_ENTRIES</description>
18862 <description>TX FIFO is empty; i.e. it has 0 entries.</description>
18868 <description>Attempt to write to a full TX FIFO.</description>
18874 …<description>Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer …
18880 …<description>More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTL.…
18886 <description>RX FIFO is not empty.</description>
18892 …<description>RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. e…
18898 <description>Attempt to write to a full RX FIFO.</description>
18904 <description>Attempt to read from an empty RX FIFO.</description>
18912 <description>Master interrupt set request register</description>
18921 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
18927 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
18933 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
18939 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
18945 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
18951 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
18957 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
18963 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
18969 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
18975 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
18981 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
18989 <description>Master interrupt mask register.</description>
18998 … <description>Mask bit for corresponding bit in interrupt request register.</description>
19004 … <description>Mask bit for corresponding bit in interrupt request register.</description>
19010 … <description>Mask bit for corresponding bit in interrupt request register.</description>
19016 … <description>Mask bit for corresponding bit in interrupt request register.</description>
19022 … <description>Mask bit for corresponding bit in interrupt request register.</description>
19028 … <description>Mask bit for corresponding bit in interrupt request register.</description>
19034 … <description>Mask bit for corresponding bit in interrupt request register.</description>
19040 … <description>Mask bit for corresponding bit in interrupt request register.</description>
19046 … <description>Mask bit for corresponding bit in interrupt request register.</description>
19052 … <description>Mask bit for corresponding bit in interrupt request register.</description>
19058 … <description>Mask bit for corresponding bit in interrupt request register.</description>
19066 <description>Master interrupt masked request register</description>
19075 <description>Logical and of corresponding request and mask bits.</description>
19081 <description>Logical and of corresponding request and mask bits.</description>
19087 <description>Logical and of corresponding request and mask bits.</description>
19093 <description>Logical and of corresponding request and mask bits.</description>
19099 <description>Logical and of corresponding request and mask bits.</description>
19105 <description>Logical and of corresponding request and mask bits.</description>
19111 <description>Logical and of corresponding request and mask bits.</description>
19117 <description>Logical and of corresponding request and mask bits.</description>
19123 <description>Logical and of corresponding request and mask bits.</description>
19129 <description>Logical and of corresponding request and mask bits.</description>
19135 <description>Logical and of corresponding request and mask bits.</description>
19143 <description>Radio Control Bus (RCB) & Link Layer controller</description>
19147 <description>RCB LL control register.</description>
19156 <description>RCB register access control
19161 …PU (HW clears this when the RCB controller is free abd RCB?_LL_CPU_REQ is set to 1)</description>
19167 <description>RCB register access control request by CPU
19170 And also indicates this by giving RCB_LL_DONE interrupt</description>
19176 <description>N/A</description>
19182 <description>N/A</description>
19188 …description>This bit indicates if CPU Single Read/Single Write are allowed when Radio RX/TX is ong…
19194 …<description>This bit indicates if the active logic in CYBLERD55 is reset on every TX/RX transacti…
19202 <description>Master interrupt request register.</description>
19211 <description>RCB_LL is done and the access is given back to CPU</description>
19217 <description>N/A</description>
19223 <description>N/A</description>
19231 <description>Master interrupt set request register</description>
19240 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
19246 <description>N/A</description>
19252 <description>N/A</description>
19260 <description>Master interrupt mask register.</description>
19269 … <description>Mask bit for corresponding bit in interrupt request register.</description>
19275 <description>N/A</description>
19281 <description>N/A</description>
19289 <description>Master interrupt masked request register</description>
19298 <description>Logical and of corresponding request and mask bits.</description>
19304 <description>N/A</description>
19310 <description>N/A</description>
19318 <description>Address of Register#1 in Radio (MDON)</description>
19327 <description>N/A</description>
19335 <description>Address of Register#2 in Radio (RSSI)</description>
19344 <description>N/A</description>
19352 <description>Address of Register#3 in Radio (ACCL)</description>
19361 <description>N/A</description>
19369 <description>Address of Register#4 in Radio (ACCH)</description>
19378 <description>N/A</description>
19386 <description>Address of Register#5 in Radio (RSSI ENERGY)</description>
19395 <description>N/A</description>
19403 <description>N/A</description>
19412 <description>N/A</description>
19418 <description>N/A</description>
19426 <description>N/A</description>
19435 <description>N/A</description>
19441 <description>N/A</description>
19451 <description>Bluetooth Low Energy Link Layer</description>
19455 <description>Instruction Register</description>
19464 <description>N/A</description>
19472 <description>Event(Interrupt) status and Clear register</description>
19481 …<description>Advertiser interrupt. If bit is set to 1, it indicates an event occurred in the adver…
19482 … is cleared, when firmware clears ALL interrupts by writing to the ADV_INTR register.</description>
19488 …<description>Scanner interrupt. If bit is set to 1, it indicates an event occurred in the scannin…
19489 …is cleared, when firmware clears ALL interrupts by writing to the SCAN_INTR register.</description>
19495 …<description>Initiator interrupt. If bit is set to 1, it indicates an event occurred in the initi…
19496 …is cleared, when firmware clears ALL interrupts by writing to the INIT_INTR register.</description>
19502 …description>Connection interrupt. If bit is set to 1, it indicates an event occurred in the conne…
19508 …<description>Read: Sleep-mode-exit interrupt. This bit is set, when link layer hardware exits from…
19510 This interrupt is deprecated and should not be used.</description>
19516 …<description>Read: Deep sleep mode exit interrupt. This bit is set, when link layer hardware exits…
19517 …interrupt. Write to the register with this bit set to 1, clears the interrupt source.</description>
19523 <description>Encryption module interrupt.
19524 This interrupt id deprecated and should not be used</description>
19530 <description>RSSI RX done interrupt.</description>
19538 <description>Event indications enable.</description>
19547 <description>Advertiser interrupt enable.
19549 0 - disable advertiser procedure interrupt to firmware.</description>
19555 <description>Scanner interrupt enable.
19557 0 - disable scan procedure interrupt to firmware.</description>
19563 <description>Initiator interrupt enable.
19565 0 - disable initiator procedure interrupt to firmware.</description>
19571 <description>Connection interrupt enable.
19573 0 - disable connection procedure interrupt to firmware.</description>
19579 <description>Sleep-mode-exit interrupt enable.
19582 This interrupt is deprecated and should not be used.</description>
19588 <description>Deep Sleep-mode-exit interrupt enable.
19590 0 - disable deep sleep mode exit interrupt to firmware.</description>
19596 <description>Encryption module interrupt enable.
19599 This interrupt is deprecated and should not be used</description>
19605 <description>RSSI Rx interrupt enable.
19607 0 - Disable RSSI Rx done interrupt to firmware.</description>
19615 <description>Advertising parameters register.</description>
19624 <description>Device own address type.
19626 0 - Address type is public.</description>
19632 …<description>The Advertising type is used to determine the packet type that is used for advertisin…
19636 0x3 - Non connectable undirected advertising (adv_nonconn_ind).</description>
19642 …<description>Advertising filter policy. The set of devices that the advertising procedure uses for…
19646 …om devices in white list only, allow connect request from devices in white list only.</description>
19652 …<description>Advertising channel map indicates the advertising channels used for advertising. By s…
19655 5 - enable channel 37.</description>
19661 …<description>Peer addresses type. This is the Direct_Address_type field programmed, only if ADV_DI…
19663 0 - Rx addr type is public</description>
19669 …<description>Peer secondary addresses type. This is the Direct_Address_type field programmed, only…
19671 0 - Rx secondary addr type is public</description>
19677 …<description>This bit field is used to specify to the Controller the Low Duty Cycle connectable di…
19679 0 - High Duty Cycle Connectable Directed Advertising.</description>
19685 …<description>This bit field is used to specify the Advertiser behavior on receiving the same INITA…
19687 1 - Reject the connect_req packet</description>
19693 …<description>Device own address type subtype when Address type is random. This bit is valid only i…
19695 0 - Random Address type is static.</description>
19701 …<description>Advertiser behavior when a peer Identity address is received in privacy mode. This bi…
19703 …- Reject packets with peer identity address not in the Resolving list in privacy mode</description>
19709 …<description>Advertiser behavior when a peer Non Resolvable Private Address is received in privacy…
19711 0 - Respond to packets with peer NRPA address in privacy mode</description>
19717 …description>Transmit address field of the received packet extracted from the receive packet. This …
19725 <description>Advertising interval register.</description>
19734 <description>Range: 0x0020 to 0x4000 (For ADV_IND)
19741 … mode, this register is used as ADV_NI_TIMER when the ADV_NI_VALID is set by firmware</description>
19749 <description>Advertising interrupt status and Clear register</description>
19758 …<description>If this bit is set it indicates a new advertising event started after interval expiry.
19759 Write to the register with this bit set to 1, clears the interrupt source.</description>
19765 <description>If this bit is set it indicates current advertising event is closed.
19766 Write to the register with this bit set to 1, clears the interrupt source.</description>
19772 <description>If this bit is set it indicates ADV packet is transmitted.
19773 Write to the register with this bit set to 1, clears the interrupt source.</description>
19779 …<description>If this bit is set it indicates scan response packet transmitted in response to previ…
19780 Write to the register with this bit set to 1, clears the interrupt source.</description>
19786 <description>If this bit is set it indicates scan request packet received.
19787 Write to the register with this bit set to 1, clears the interrupt source.</description>
19793 <description>If this bit is set it indicates connect request packet is received.
19794 Write to the register with this bit set to 1, clears the interrupt source.</description>
19800 <description>If this bit is set it indicates that connection is created as slave.
19802 …eep mode in the same slot . It can enter deepsleep mode only in the subsequent slots.</description>
19808 …<description>If this bit is set it indicates that the directed advertising event has timed out aft…
19809 Write to the register with this bit set to 1, clears the interrupt source.</description>
19815 …<description>Advertiser procedure is ON in hardware. Indicates that advertiser procedure is ON in …
19817 0 - OFF</description>
19823 …<description>If this bit is set it indicates that connection is created as slave, but the peer dev…
19825 This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set.</description>
19831 …<description>If this bit is set it indicates scan request packet received, but the peer device Res…
19833 This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set.</description>
19839 …<description>If this bit is set it indicates that an Identity address is received from a Scanner a…
19841 This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set.</description>
19847 …<description>If this bit is set it indicates that an Identity address is received from an initiato…
19849 This bit is valid only if PRIV_1_2 and PRIV_1_2_ADV are set.</description>
19857 <description>Advertising next instant.</description>
19866 …<description>Shows the next start of advertising event with reference to the internal reference cl…
19874 <description>Scan Interval Register</description>
19883 …<description>Scan interval register. Interval between two consecutive scanning events. Firmware se…
19889 …ode, this register is used as SCAN_NI_TIMER when the SCAN_NI_VALID is set by firmware</description>
19897 <description>Scan window Register</description>
19906 …<description>Duration of scan in a scanning event, which should be less than or equal to scan inte…
19911 … not in continuous scan, the scan window must be 2 slots less that the scan interval.</description>
19919 <description>Scanning parameters register</description>
19928 <description>Device's own address type.
19930 0 - addr type is public.</description>
19936 <description>0x00 - passive scanning.(default)
19939 0x11 - RFU</description>
19945 … <description>The scanner filter policy determines how the scanner processes advertising packets.
19951 …vate address are accepted. The above 2 policies are extended scanner filter policies.</description>
19957 <description>Filter duplicate packets.
19960 This field is derived from the LE_set_scan_enable command.</description>
19966 …<description>This bit field is used to specify the Scanner duplicate filter behavior for ADV_DIREC…
19968 1 - Filter ADV_DIRECT_IND duplicate packets</description>
19974 …<description>This bit field is used to specify the Scanner behavior with respect to ADVA while rec…
19976 …re verified against ADVA received in ADV packet . If it fails, then abort the packet.</description>
19982 …<description>Scanner behavior when a peer Identity address is received in privacy mode. This bit i…
19984 …- Reject packets with peer identity address not in the Resolving list in privacy mode</description>
19990 …<description>Scanner behavior when a peer Non Resolvable Private Address is received in privacy mo…
19992 0 - Respond packets with peer NRPA address in privacy mode</description>
20000 <description>Scan interrupt status and Clear register</description>
20009 <description>If this bit is set it indicates scan window is opened.
20010 Write to the register with this bit set to 1, clears the interrupt source.</description>
20016 <description>If this bit is set it indicates scan window is closed.
20017 Write to the register with this bit set to 1, clears the interrupt source.</description>
20023 <description>If this bit is set it indicates scan request packet is transmitted.
20024 Write to the register with this bit set to 1, clears the interrupt source.</description>
20030 …<description>If this bit is set it indicates ADV packet received. Firmware can read the content of…
20033 … received after issuing SCAN_STOP command must be ignored and the ADVCH FIFO flushed.</description>
20039 …<description>If this bit is set it indicates SCAN_RSP packet is received. Firmware can read the co…
20041 …his interrupt is generated while active scanning upon receiving scan response packet.</description>
20047 …<description>If this bit is set it indicates ADV packet received but the peer device Address is no…
20049 This interrupt is generated while active/passive scanning upon receiving adv packets.</description>
20055 …<description>If this bit is set it indicates ADV_DIRECT packet received but the self device Resolv…
20057 …terrupt is generated while active/passive scanning upon receiving adv_direct packets.</description>
20063 …<description>If this bit is set it indicates that a valid ScanA RPA to be transmitted in SCAN_REQ …
20065 This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.</description>
20071 <description>Scan procedure status.
20073 0 - scan procedure is not active.</description>
20079 …<description>If this bit is set it indicates that an Identity address is received from an initiato…
20081 This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.</description>
20087 …<description>If this bit is set it indicates that the self Identity address is received from an in…
20089 This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.</description>
20097 <description>Advertising next instant.</description>
20106 …<description>Shows the instant with respect to internal reference clock of resolution 625 us at wh…
20114 <description>Initiator Interval Register</description>
20123 …<description>Initiator interval register. Firmware sets the initiator's scanning interval value to…
20128 …ode, this register is used as INIT_NI_TIMER when the INIT_NI_VALID is set by firmware</description>
20136 <description>Initiator window Register</description>
20145 …<description>Duration of scan in a scanning event, which should be less than or equal to scan inte…
20150 …ode, this register is used as INIT_NI_TIMER when the INIT_NI_VALID is set by firmware</description>
20158 <description>Initiator parameters register</description>
20167 <description>Device' own address type.
20169 0 - addr type is public.</description>
20175 <description>Peer address type.
20178 0 - addr type is public.</description>
20184 …<description>The Initiator_Filter_Policy is used to determine whether the White List is used or no…
20187 Peer_Address_Type and Peer_Address fields are ignored when whitelist is used.</description>
20193 …<description>Init behavior when a peer Identity address is received in privacy mode. This bit is v…
20195 … address not in the Resolving list in privacy mode & HW_RSLV_LIST_FULL is not set</description>
20203 <description>Scan interrupt status and Clear register</description>
20212 <description>If this bit is set it indicates initiator scan window has started.
20213 Write to the register with this bit set to 1, clears the interrupt source.</description>
20219 <description>If this bit is set it indicates initiator scan window has finished.
20220 Write to the register with this bit set to 1, clears the interrupt source.</description>
20226 … <description>If this bit is set it indicates initiator packet (CONREQ) transmission has started.
20227 Write to the register with this bit set to 1, clears the interrupt source.</description>
20233 <description>If this bit is set it indicates connection is created as master.
20234 Write to the register with this bit set to 1, clears the interrupt source.</description>
20240 …<description>If this bit is set it indicates ADV_DIRECT packet received but the self device Resolv…
20242 This interrupt is generated while active/passive scanning upon receiving adv packets.</description>
20248 …<description>If this bit is set it indicates ADV packet received but the peer device Address is no…
20250 This interrupt is generated while active/passive scanning upon receiving adv packets.</description>
20256 …<description>If this bit is set it indicates that a valid INITA RPA to be transmitted in CONN_REQ …
20258 This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set.</description>
20264 …<description>If this bit is set it indicates that an Identity address is received from an initiato…
20266 This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set.</description>
20272 <description>If this bit is set it indicates that
20276 This bit is valid only if PRIV_1_2 and PRIV_1_2_INIT are set.</description>
20284 <description>Initiator next instant.</description>
20293 …<description>Shows the instant with respect to internal reference clock of resolution 625 us at wh…
20301 <description>Lower 16 bit random address of the device.</description>
20310 <description>Lower 16 bit of 48-bit random address of the device.</description>
20318 <description>Middle 16 bit random address of the device.</description>
20327 <description>Middle 16 bit of 48-bit random address of the device.</description>
20335 <description>Higher 16 bit random address of the device.</description>
20344 <description>Higher 16 bit of 48-bit random address of the device.</description>
20352 <description>Lower 16 bit address of the peer device.</description>
20361 <description>Lower 16 bit of 48-bit address of the peer device.</description>
20369 <description>Middle 16 bit address of the peer device.</description>
20378 <description>Middle 16 bit of 48-bit address of the peer device.</description>
20386 <description>Higher 16 bit address of the peer device.</description>
20395 <description>Higher 16 bit of 48-bit address of the peer device.
20404 … this register to get the address of the peer de-vice to which connection is created.</description>
20412 <description>whitelist address type</description>
20421 <description>8 address type bits corresponding to the device address stored.
20423 0 - Address type is public.</description>
20431 <description>whitelist valid entry bit</description>
20440 …<description>Stores the valid entry bit corresponding to each of the eight device address stored i…
20442 0 - White list entry is Invalid</description>
20450 <description>Transmit window offset</description>
20459 …<description>This is used to determine the first anchor point for the master transmission, from th…
20460 Range: This shall be a multiple of 1.25 ms in the range of 0 ms to connInterval value.</description>
20468 <description>Transmit window size</description>
20477 …<description>window_size along with the window_offset is used to calculate the first connection po…
20479 Values range from 0 to 10 ms.</description>
20487 <description>Data channel map 0 (lower word)</description>
20496 …<description>This register field indicates which of the data channels are in use. This stores the …
20497 …cates the corresponding data channel is used and '0' indicates the channel is unused.</description>
20505 <description>Data channel map 0 (middle word)</description>
20514 …<description>This register field indicates which of the data channels are in use. This stores the …
20515 …cates the corresponding data channel is used and '0' indicates the channel is unused.</description>
20523 <description>Data channel map 0 (upper word)</description>
20532 …<description>This register field indicates which of the data channels are in use. This stores the …
20534 …cific to the link. Firmware must also manage to update this field along with the map.</description>
20542 <description>Data channel map 1 (lower word)</description>
20551 …<description>This register field indicates which of the data channels are in use. This stores the …
20552 …cates the corresponding data channel is used and '0' indicates the channel is unused.</description>
20560 <description>Data channel map 1 (middle word)</description>
20569 …<description>This register field indicates which of the data channels are in use. This stores the …
20570 …cates the corresponding data channel is used and '0' indicates the channel is unused.</description>
20578 <description>Data channel map 1 (upper word)</description>
20587 …<description>This register field indicates which of the data channels are in use. This stores the …
20589 …cific to the link. Firmware must also manage to update this field along with the map.</description>
20597 <description>Connection interrupt status and Clear register</description>
20606 <description>If this bit is set it indicates that the link is disconnected.
20607 If this bit is written with 1, it clears the connection updated interrupt.</description>
20613 …<description>If this bit is set it indicates that the connection has been established. The bit is …
20614 If this bit is written with 1, it clears the connection established interrupt.</description>
20620 …<description>If this bit is set it indicates that the channel map update is completed at the insta…
20621 If this bit is written with 1, it clears the map update done interrupt.</description>
20627 …<description>If this bit is set it indicates that the connection event started interrupt has happe…
20628 If this bit is written with 1, it clears the connection event started interrupt.</description>
20634 …<description>If this bit is set it indicates that the connection event closed interrupt has happen…
20635 If this bit is written with 1, it clears the connection event closed interrupt.</description>
20641 …<description>If this bit is set it indicates that the connection event transmission acknowledgemen…
20642 …bit is written with 1, it clears the ce transmission acknowledgement interrupt.</description>
20648 … <description>If this bit is set it indicates that a packet is received in the connection event.
20649 If this bit is written with 1, it clears the connection event received interrupt.</description>
20655 …<description>This bit is set when the last connection event with previous connec-tion parameters i…
20656 If this bit is written with 1, it clears the connection updated interrupt.</description>
20662 … <description>Reason for disconnect - indicates the reason the link is disconnected by hardware.
20667 101 - PDU response timer expired</description>
20673 … <description>Status of PDU received. This information is valid along with receive interrupt.
20677 110 - Duplicate Packet</description>
20683 <description>If this is set, it indicates that ping timer has expired.
20684 If this bit is written with 1, it clears the interrupt.</description>
20690 <description>If this is set, it indicates that ping timer has nearly expired.
20691 If this bit is written with 1, it clears the interrupt.</description>
20699 <description>Connection channel status</description>
20708 …<description>This field stores the count for the number of receive packets in the receive FIFO tha…
20710 … it decrements the counter by issuing the PACKET_RECEIVED command from the commander.</description>
20718 <description>Connection Index register</description>
20727 …<description>This field is used to index the multiple connections existing. Range is 0 to maximum …
20728 For a single connection device, conn_index is 0.</description>
20736 <description>Wakeup configuration</description>
20745 …<description>Oscillator stabilization/startup delay. This is in X.Y for-mat where X is in terms of…
20748 …y [4:0] sup-ported is 1 and Max. value is 9. Therefore programma-ble range is 1 to 9)</description>
20754 …description>Number of 'slots' before the wake up instant before which the hardware needs to exit f…
20762 <description>Wakeup control</description>
20771 …<description>Instant, with reference to the internal 16-bit clock reference, at which the hardware…
20772 …akeup_instant - osc_startup_delay, and it shall be greater than 'reference clock + 2'</description>
20780 <description>Clock control</description>
20789 <description>Advertiser block clock gate enable. 1 - enable, 0 - disable.
20790 …e module. If 0, the logic has no control and clock to the module is always turned ON.</description>
20796 <description>Scan block clock gate enable. 1 - enable, 0 - disable.
20797 …e module. If 0, the logic has no control and clock to the module is always turned ON.</description>
20803 <description>Initiator block clock gate enable. 1 - enable, 0 - disable.
20804 …e module. If 0, the logic has no control and clock to the module is always turned ON.</description>
20810 <description>Connection block clock gate enable. 1 - enable, 0 - disable.
20811 …e engine. If 0, the logic has no control and clock to the module is always turned ON.</description>
20817 <description>Core clock gate enable. 1 - enable, 0 - disable.
20818 …he clock to the module. If 0, the logic has no control and clock is always turned ON.</description>
20824 <description>Sysclk gate enable. 1- enable, 0 - disable.
20825 …nput from pin. If 0, the DSM logic has no control and the system clock is always ON.</description>
20831 <description>Digital PHY clock enable. 1- enable, 0-disable.
20832 …ty so PHY clock must be turned ON. When 0, it indicates inactivity in the controller.</description>
20838 …<description>Indicates if hardware is doing any transmit/receive operation. This information is us…
20840 …e generates dsm exit interrupt to inform firmware that DSM entry was not successful).</description>
20846 <description>Clock frequency select. 0 - 32KHz, 1 - 32.768KHz.
20847 …put used for generat-ing the internal reference clock of approximate 16Khz frequency.</description>
20853 … <description>Select external sleep clock. 1 - External clock, 0 - inter-nal generated clock.
20854 …e DSM logic or to use the internal gener-ated reference clock(of 16KHz) for the same.</description>
20860 <description>Enable sleep mode auto wakeup enable. 1- enable, 0 - disable.
20861 …_to_wakeup_instant value is the field described in the wakeup configuration register.</description>
20867 <description>Enable SM exit interrupt. 1 - enable, 0 - disable.
20869 This feature is not available. FW should never set this bit</description>
20875 <description>Disable Auto Wakeup in DEEP_SLEEP mode.
20877 0 - Auto Wakeup enabled</description>
20883 <description>Enable sleep mode. 1 - enable, 0 - disable.
20885 This feature is not available. FW should never set this bit</description>
20891 <description>Enable deep sleep mode. 1 - enable, 0 - disable.
20892 …isabled, the related logic is not executed and hardware cannot enter deep sleep mode.</description>
20900 <description>Reference Clock</description>
20909 …description>16-bit internal reference clock. The clock is a free run-ning clock, incremented by a …
20917 <description>Wakeup configuration extended</description>
20926 …description>Number of 'LF slots' before the wake up instant before which the hardware needs to exi…
20934 <description>BLE Time Control</description>
20943 …description>LLH clock configuration. The clock frequency of the clock input to this design is conf…
20949 …description>LLH clock configuration. The start of slot signal is offset by this value. If value is…
20957 <description>Advertising data transmit FIFO. Access ADVCH_TX_FIFO.</description>
20966 …<description>IO mapped FIFO of depth 16 (2 byte wide), to store ADV data of maximum length 31 byte…
20968 Reading this location resets the FIFO pointer.</description>
20976 … <description>Advertising scan response data transmit FIFO. Access ADVCH_TX_FIFO.</description>
20985 …<description>IO mapped FIFO of depth 16 (2 byte wide), to store scan response data of maximum leng…
20987 Reading this location resets the FIFO pointer.</description>
20995 … <description>advertising scan response data receive data FIFO. Access ADVRX_FIFO.</description>
21004 …<description>IO mapped FIFO of depth 64, to store ADV and SCAN_RSP header and payload received by …
21005 …dvertise channel data receive FIFO followed by the payload data and then 16 bit RSSI.</description>
21013 <description>Connection Interval</description>
21022 …<description>The value configured in this register determines the spacing be-tween the connection …
21023 This shall be a multiple of 1.25 ms in the range of 7.5 ms to 4.0 s.</description>
21031 <description>Supervision timeout</description>
21040 …<description>This field defines the maximum time between two received Data packet PDUs before the …
21041 …ge of 100 ms to 32.0 s and it shall be larger than (1+connSlaveLatency)*connInterval.</description>
21049 <description>Slave Latency</description>
21058 …<description>The value configured in this field defines the number of consecutive connection event…
21060 …nnSupervision Timeout/connInterval)-1). connSlaveLatency shall also be less than 500.</description>
21068 <description>Connection event length</description>
21077 <description>N/A</description>
21085 <description>Access address (lower)</description>
21094 …<description>This field defines the lower 16 bits of the access address for each Link layer connec…
21102 <description>Access address (upper)</description>
21111 …<description>This field defines the higher 16 bits of the access address for each Link layer conne…
21119 <description>Connection event instant</description>
21128 …<description>This is the value of the free running Connection Event counter when the new parameter…
21129 Range : 0x0000 to 0xFFFF</description>
21137 <description>connection configuration & status register</description>
21146 …<description>Data list index for start/resume. This field must be valid along with data_list_head_…
21148 Hardware will start the next data transmission from the index indicated by this field.</description>
21154 …<description>Update the first packet buffer index ready for transmis-sion to start/resume data tra…
21155 …ware needs to indicate the start/resume. This requires a read modify write operation.</description>
21161 <description>This bit is unused</description>
21167 … <description>MD bit set to '1' indicates device has more data to be sent.</description>
21173 …<description>Written by firmware to select the map index to be used by hardware for this connectio…
21176 …n firmware reads this field, it returns the current map index being used in hardware.</description>
21182 <description>Pause data.
21186 …ENT bit is set for the current_pdu_index as which pause is set, data will be sent out</description>
21192 <description>This bit is '1' whenever the connection is active.</description>
21198 …<description>The index of the transmit packet buffer that is currently in transmission/waiting for…
21206 <description>Next connection event instant</description>
21215 …<description>16-bit internal reference clock value at which the next connection event will occur o…
21216 …deassertion, then the very next clock, the value assigned to the registers is 0xFFFF.</description>
21224 <description>connection event counter</description>
21233 … <description>This is the free running counter, connEventCounter as defined by Bluetooth spec.
21234 … the new parameters (for connection update and channel map update) will be effective.</description>
21242 <description>data list sent update and status</description>
21251 … <description>Write:Indicates the buffer index for which the SENT bit is being updated by firmware.
21261 SENT ACK Description
21266 0 0 Firmware has processed the ack. The buffer is again empty.</description>
21272 … <description>Write: Used to set the SENT bit in hardware for the selected packet buffer.
21276 …ent from the remote device, firmware clears BIT7 along with the list_index specified.</description>
21284 <description>data list ack update and status</description>
21293 … <description>Write: Indicates the buffer index for which the ACK bit is being updated by firmware.
21302 SENT ACK Description
21307 0 0 Firmware has processed the ack. The buffer is again empty.</description>
21313 …<description>Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that …
21317 …CK bit in hardware is set by hardware when it has success-fully transmitted a packet.</description>
21325 <description>connection configuration & status register</description>
21334 <description>transmittion on 2M</description>
21340 <description>receiving on 2M</description>
21346 <description>Sequence number for next scheduled connection index</description>
21352 <description>Next Sequence number for next scheduled connection index</description>
21358 <description>Last unmapped channel for next scheduled connection index</description>
21366 <description>Connection extended interrupt status and Clear register</description>
21375 <description>If this bit is set it indicates that the data rate is updated
21376 If this bit is written with 1, it clears the interrupt status bit</description>
21382 <description>For master this bit is set on start_ce
21383 For Slave this bit is set on slave_timer_adj</description>
21389 …<description>If this bit is set it indicates that the generic timer (PDU response timer reconfigur…
21390 If this bit is written with 1, it clears the interrupt status bit</description>
21398 <description>Connection Extended Interrupt mask</description>
21407 … <description>If this bit is set connection data rate update interrupt is enabled.</description>
21413 <description>If this bit is set connection early interrupt is enabled.</description>
21419 …<description>Generic timer (PDU response timer reconfigured in MMMS mode) expiry interrupt</descri…
21429 <description>Data buffer descriptor 0 to 4</description>
21438 <description>N/A</description>
21444 …<description>This field indicates the length of the data packet. Bits [9:7] are valid only if DLE …
21445 Range 0x00 to 0xFF.</description>
21453 <description>Window widen for interval</description>
21462 <description>This value defines the increased listening time for the slave.
21464 …this value is accu-mulated till the next anchor point at which the slave will listen.</description>
21472 <description>Window widen for offset</description>
21481 …description>This field stores the additional number of microseconds the slave must extend its list…
21489 <description>Direct Test Mode control</description>
21498 <description>N = (F - 2402) / 2
21499 Range: 0x00 - 0x27. Frequency Range : 2402 MHz to 2480 MHz</description>
21505 <description>This bit is overloaded.
21511 1: DTM run at continuous RX DTM mode</description>
21517 <description>N/A</description>
21523 <description>0: DTM run at normal DTMTX burst mode
21524 1: DTM run at continuous TX DTM mode</description>
21530 <description>0: DTM run at 1M bps data rate
21531 1: DTM run at 2M bps data rate</description>
21539 <description>Direct Test Mode receive packet count</description>
21548 <description>Number of packets received in receive test mode.</description>
21556 <description>Direct Test Mode control</description>
21565 <description>DTM TX packet length.
21566 Bits [7:6] are accessible onle when DLE is enabled</description>
21574 <description>Channel Address register</description>
21583 …<description>Transmit channel index. Channel index on which previous packet is transmitted.</descr…
21589 …<description>Receive channel index. Channel index on which previous packet is received.</descripti…
21597 <description>Transmit/Receive data delay</description>
21606 …description>Receive delay - Delay from start of receive to expected first bit of receive packet at…
21612 …description>Transmit delay - Delay from start of transmit to transmission of first bit on air. It …
21620 <description>ADV packet access code low word</description>
21629 <description>Lower 16 bit of ADV packet access code</description>
21637 <description>ADV packet access code high word</description>
21646 <description>higher 16 bit of ADV packet access code</description>
21654 <description>Advertising channel transmit power setting</description>
21663 …<description>When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 1, this field represents the Advertising channel…
21664 …E is 0, the LS 4 bits represents the Advertising channel transmit power code 4 bits.</description>
21672 <description>Advertising channel transmit power setting extension</description>
21681 … <description>Advertising channel transmit power setting Most Significant 2 bits.</description>
21689 <description>Connection channel transmit power setting</description>
21698 …<description>When LL_CONFIG.TX_PA_PWR_LVL_TYPE is 1, this field represents the Connection channel …
21699 …PE is 0, the LS 4 bits represents the Connection channel transmit power code 4 bits.</description>
21707 <description>Connection channel transmit power setting extension</description>
21716 … <description>Connection channel transmit power setting Most Significant 2 bits.</description>
21724 <description>Device public address lower register</description>
21733 <description>Lower 16 bit of 48-bit public address of the device.</description>
21741 <description>Device public address middle register</description>
21750 <description>Middle 16 bit of 48-bit public address of the device.</description>
21758 <description>Device public address higher register</description>
21767 <description>Higher 16 bit of 48-bit public address of the device.</description>
21775 <description>Offset to first instant</description>
21784 …<description>The offset w.r.t the internal reference clock at which instant the first event occurs.
21785 …t is optional to be updated by firmware. This is not updated in the current firmware.</description>
21793 <description>Advertiser configuration register</description>
21802 <description>Enable advertising event start interrupt.</description>
21808 <description>Enable advertising event stop interrupt.</description>
21814 <description>Enable adv packet transmitted interrupt.</description>
21820 <description>Enable scan response packet transmitted interrupt.</description>
21826 <description>Enable scan request packet received interrupt.</description>
21832 <description>Enable connect request packet received interrupt.</description>
21838 <description>Enable slave connected interrupt.</description>
21844 … <description>Enable adv_timeout interrupt. Applicable in adv_direct_ind advertising.</description>
21850 …<description>Disable randomization of adv interval. When disabled, interval is same as programmed …
21856 …description>Enable scan request packet received with peer device address unmatched interrupt. This…
21862 …description>Enable connect request packet received with peer device address unmatched interrupt. T…
21868 <description>Time between the beginning of two consecutive advertising PDU's.
21870 Time Range: <=10msec.</description>
21878 <description>Scan configuration register</description>
21887 <description>Enable scan event start interrupt.</description>
21893 <description>Enable scan event close interrupt.</description>
21899 <description>Enable scan request packet transmitted interrupt.</description>
21905 <description>Enable adv packet received interrupt .</description>
21911 <description>Enable scan_rsp packet received interrupt .</description>
21917 …<description>Enable ADV peer address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_…
21923 …<description>Enable ADV self address unmatched interrupt. This bit is valid only if PRIV_1_2 PRIV_…
21929 …<description>Enable SCANA RPA TX not set interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_…
21935 …<description>This bit controls the SCAN engine behavior when an self address match occurs but a pr…
21938 This bit is valid only if PRIV_1_2 and PRIV_1_2_SCAN are set.</description>
21944 <description>Enable random backoff feature in scanner.
21946 0 - disable</description>
21952 <description>Advertising channels that are enabled for scanning operation.
21955 Bit 13: setting 1 - enables channel 37 for use.</description>
21963 <description>Initiator configuration register</description>
21972 <description>Enable Initiator event start interrupt.</description>
21978 <description>Enable Initiator event close interrupt.</description>
21984 … <description>Enables connection request packet transmission start interrupt.</description>
21990 <description>Enable master connection created interrupt</description>
21996 …<description>Enable ADV self address RPA unresolved interrupt. This bit is valid only if PRIV_1_2 …
22002 …<description>Enable ADV peer address RPA unresolved interrupt. This bit is valid only if PRIV_1_2 …
22008 …<description>Enable INITA RPA TX not set interrupt. This bit is valid only if PRIV_1_2 and PRIV_1_…
22014 <description>Advertising channels that are enabled for initiator scanning operation.
22017 Bit 13: setting 1 - enables channel 37 for use.</description>
22025 <description>Connection configuration register</description>
22034 …description>Defines a limit for the number of Rx packets that can be re-ceived by the LLH. Default…
22040 …<description>This register field allows setting a threshold for the packet received interrupt to t…
22044 Min value possible is 1. Max value depends on the Rx FIFO capacity.</description>
22050 …<description>This register field indicates whether the MD (More Data) bit needs to be controlled b…
22054 … there is an acknowledgement awaited from the remote side for the packet transmitted.</description>
22060 <description>This bit configures the DSM slot counting mode.
22062 …count variance with respect to actual time is more than 1 slot &less that 2 slots</description>
22068 … <description>This bit is set to configure the MD bit control when IUT is in slave role.
22071 This bit has effect only when 'CONN_CONFIG.md_bit_ctr' bit is not set .</description>
22077 …<description>This bit is used to enable/disable extending the additional rx window on slave side d…
22079 0 - Disable</description>
22085 …<description>This bit is used to enable/disable masking of internal hardware supervision timeout t…
22087 0 - Disable</description>
22093 …<description>This bit is used to enable extension of the Conn Request to arbiter to 1 slot early. …
22095 0 - Disable</description>
22103 <description>Connection parameter 1</description>
22112 <description>Sleep Clock Accuracy</description>
22118 <description>Hop increment for connection channel.</description>
22124 …<description>This field defines the lower byte (7:0) of the CRC initialization vector.</descriptio…
22132 <description>Connection parameter 2</description>
22141 …<description>This field defines the upper two bytes (23:8) of the CRC initialization vector.</desc…
22149 <description>Connection Interrupt mask</description>
22158 … <description>If this bit is set connection closed interrupt is enabled.</description>
22164 … <description>If this bit is set connection establishment interrupt is enabled.</description>
22170 … <description>If this bit is set, channel map update interrupt is enabled.</description>
22176 … <description>If this bit is set connection event start interrupt is enabled</description>
22182 … <description>If this bit is set connection event closed interrupt is enabled.</description>
22188 <description>If this bit is set transmission acknowledgement interrupt is enabled:
22190 …tive acknowledgements from remote device, this interrupt indication is not generated.</description>
22196 …<description>If this bit is set interrupt is enabled for reception of packet in a connection event…
22202 … <description>If this bit is set connection update interrupt is enabled.</description>
22208 …<description>If this bit is set packet receive good pdu interrupt is enabled. Effective only when …
22214 …<description>If this bit is set packet receive bad pdu interrupt is enabled. Effective only when b…
22220 …<description>If this but us set, the RX interrupt is triggerred for an end of connection event wit…
22226 … <description>If this bit is set ping timer expired interrupt is enabled.</description>
22232 … <description>If this bit is set ping timer nearly expired interrupt is enabled</description>
22240 <description>slave timing control</description>
22249 … <description>Programmable adjust value to the clock counter when slave is connected</description>
22255 …description>Timing adjust value. The internal micro second counter is adjusted to this value whene…
22263 <description>Receive trigger control</description>
22272 …<description>Access address match threshold value. Number of bits of ac-cess address that should m…
22275 … ensure there are no 'false' matches due to reduced number of bits required to match.</description>
22281 …<description>If access address match does not occur then within this time from the start of receiv…
22282 Max value :0xFF</description>
22290 <description>LL debug register 1</description>
22299 <description>Connection receive FIFO write pointer</description>
22307 <description>LL debug register 2</description>
22316 <description>Connection receive FIFO read pointer</description>
22324 <description>LL debug register 3</description>
22333 … <description>Connection receive FIFO stored write pointer for pointer restore</description>
22341 <description>LL debug register 4</description>
22350 <description>Connection FSM state</description>
22356 <description>Slave Latency FSM state</description>
22362 <description>Advertiser FSM state</description>
22370 <description>LL debug register 5</description>
22379 <description>Initiator FSM state</description>
22385 <description>Scanner FSM state</description>
22393 <description>LL debug register 6</description>
22402 <description>Advertiser Transmit FIFO write pointer</description>
22408 <description>Scan Response Transmit FIFO write pointer</description>
22414 <description>Advertiser/ Scan Response FIFO read pointer</description>
22422 <description>LL debug register 7</description>
22431 <description>Advertiser Receive FIFO write pointer</description>
22437 <description>Advertiser Receive FIFO read pointer</description>
22445 <description>LL debug register 8</description>
22454 … <description>Advertiser Receive FIFO stored write pointer for pointer restore</description>
22460 <description>Whitelist FIFO pointer</description>
22468 <description>LL debug register 9</description>
22477 …description>Window Widening value in us. The reset value of this register is 0x0000. After reset d…
22485 <description>LL debug register 10</description>
22494 <description>Active channel number</description>
22502 <description>Lower 16 bit address of the peer device for INIT.</description>
22511 … <description>Lower 16 bit of 48-bit address of the peer device. This is used only in MMMS mode
22517 …rom which connectable ADV packet was received and to which the connection is created.</description>
22525 <description>Middle 16 bit address of the peer device for INIT.</description>
22534 … <description>Middle 16 bit of 48-bit address of the peer device. This is used only in MMMS mode
22540 …rom which connectable ADV packet was received and to which the connection is created.</description>
22548 <description>Higher 16 bit address of the peer device for INIT.</description>
22557 … <description>Higher 16 bit of 48-bit address of the peer device. This is used only in MMMS mode
22563 …rom which connectable ADV packet was received and to which the connection is created.</description>
22571 … <description>Lower 16 bits of the secondary address of the peer device for ADV_DIR.</description>
22580 …<description>Lower 16 bit of 48-bit secondary address of the peer device for ADV_DIR.</description>
22588 … <description>Middle 16 bits of the secondary address of the peer device for ADV_DIR.</description>
22597 …<description>Middle 16 bit of 48-bit secondary address of the peer device for ADV_DIR.</descriptio…
22605 … <description>Higher 16 bits of the secondary address of the peer device for ADV_DIR.</description>
22614 … <description>Higher 16 bit of 48-bit secondary address of the peer device for ADV_DIR.
22616 …ty address is written into the PEER_ADDR registers and this register must be cleared.</description>
22624 <description>Initiator Window NI timer control</description>
22633 <description>Controls the INIT Window offset source
22635 0 - Pick INIT Window Offset from FW loaded register</description>
22643 <description>Connection extended configuration register</description>
22652 …<description>This bit is used to enable extension of the Conn Request to arbiter to 2 slot early. …
22654 0 - Disable</description>
22660 …<description>This bit is used to enable extension of the Conn Request to arbiter to 3 slot early. …
22662 0 - Disable</description>
22668 …description>Connection Index for which the FW generates Packet Received Command. In MMMS mode, FW …
22674 …<description>Receive Packet Limit for MMMS mode. This is the RX_FIFO Limit and applies to all conn…
22680 <description>MMMS CE expire control bit</description>
22686 <description>MMMS empty PDU CE expire handling control bit</description>
22694 <description>DPLL & CY Correlator configuration register</description>
22703 <description>If MXD_IF_OPTION is 0:
22708 …rrel maximum number of allowed mismatched bits in access address. Ideal value is 0x0.</description>
22716 <description>Initiator Window NI instant</description>
22725 …<description>Initiator window Next Instant value used for spacing Master connections in time, to m…
22726 The read value corresponds to the hardware updated Interval value</description>
22734 <description>Initiator Window offset captured at conn request</description>
22743 …<description>Initiator Window offset captured at conn request. This value is in 1.25ms slots</desc…
22751 <description>Initiator Window NI anchor point captured at conn request</description>
22760 …description>Initiator interval offset captured at conn request. The value indicates the master con…
22768 <description>Connection update new interval</description>
22777 …description>This register will have the new connection interval that the hardware will use after t…
22785 <description>Connection update new latency</description>
22794 …description>This register will have the new slave latency parameter that the hardware will use aft…
22802 <description>Connection update new supervision timeout</description>
22811 …description>This register will have the new supervision timeout that the hardware will use after t…
22819 <description>Connection update new Slave Latency X Conn interval Value</description>
22828 …description>This register will have the new Slave Latency * Conn Interval value that the hardware …
22836 <description>Connection request address word 0</description>
22845 …<description>This field defines the lower 16 bits of the access address that is to be sent in the …
22853 <description>Connection request address word 1</description>
22862 …<description>This field defines the upper16 bits of the access address that is to be sent in the c…
22870 <description>Connection request address word 2</description>
22879 …<description>window_size along with the window_offset is used to calculate the first connection po…
22881 Values range from 0 to 10 ms.</description>
22887 …<description>This field defines the lower byte [7:0] of the CRC initialization value.</description>
22895 <description>Connection request address word 3</description>
22904 …description>This field defines the upper byte [23:8] of the CRC initialization value that is to be…
22912 <description>Connection request address word 4</description>
22921 <description>This is used to determine the anchor point for the master transmission.
22922 Range: This shall be a multiple of 1.25 ms in the range of 0 ms to connInterval value.</description>
22930 <description>Connection request address word 5</description>
22939 …<description>The value configured in this register determines the spacing between the connection e…
22940 This shall be a multiple of 1.25 ms in the range of 7.5 ms to 4.0 s.</description>
22948 <description>Connection request address word 6</description>
22957 …description>The value configured in this field defines the number of consecutive connection events…
22965 <description>Connection request address word 7</description>
22974 …<description>This field defines the maximum time between two received Data packet PDUs before the …
22975 …ge of 100 ms to 32.0 s and it shall be larger than (1+connSlaveLatency)*connInterval.</description>
22983 <description>Connection request address word 8</description>
22992 …<description>This register field indicates which of the data channels are in use. This stores the …
22993 …cates the corresponding data channel is used and '0' indicates the channel is unused.</description>
23001 <description>Connection request address word 9</description>
23010 …<description>This register field indicates which of the data channels are in use. This stores the …
23011 …cates the corresponding data channel is used and '0' indicates the channel is unused.</description>
23019 <description>Connection request address word 10</description>
23028 …<description>This register field indicates which of the data channels are in use. This stores the …
23029 …cates the corresponding data channel is used and '0' indicates the channel is unused.</description>
23037 <description>Connection request address word 11</description>
23046 … <description>This field is used for the data channel selection process.</description>
23052 … <description>This field defines the sleep clock accuracies given in ppm.</description>
23060 <description>PDU response timer/Generic Timer (MMMS mode)</description>
23069 …<description>Non MMMS mode: This register is loaded with the count value to monitor the time to ge…
23080 Resolution : 625 us</description>
23088 <description>Next response timeout instant</description>
23097 …<description>This field defines the clock instant at which the next PDU response timeout event wil…
23098 This is with reference to the 16-bit internal reference clock.</description>
23106 <description>Next supervision timeout instant</description>
23115 …<description>This field defines the clock instant at which the next connection supervision timeout…
23116 This is with reference to the 16-bit internal reference clock.</description>
23124 <description>Feature enable</description>
23133 <description>Quick transmit feature in slave latency is enabled by setting this bit.
23134 …nection interval, in case required, instead of waiting till the end of slave latency</description>
23140 <description>Enable/Disable Slave Latency Period DSM.</description>
23146 …<description>Enable/Disable the connection US counter offset adjust. For non-MMMS mode, this bit m…
23154 <description>Window minimum step size</description>
23163 …description>After receiving 2 consecutive good packets the reference window is gradually decrement…
23169 …description>If packets are missed, the reference window is gradually increased by step up size, un…
23175 …description>Minimum window interval value programmed by firmware. While the slave receive window i…
23183 <description>Slave window adjustment</description>
23192 …<description>Window Adjust value. This value is added to the calculated slave window widening valu…
23200 <description>Slave Latency X Conn Interval Value</description>
23209 …description>This field defines the (SL*CI) product for the ongoing connection. This value is used …
23217 <description>LE Ping connection timer address</description>
23226 …<description>The register used to configure the LE Au-thenticated payload Timeout (LE APTO) which …
23227 This value of ping timer is in the order of 10ms, valid range 0x1 ~ 0xFFFF</description>
23235 <description>LE Ping connection timer offset</description>
23244 …description>The value of ping timer nearly expired offset in the order of 10ms, valid range 0x0 ~ …
23252 <description>LE Ping timer next expiry instant</description>
23261 …<description>The value of ping timer next expiry instant in the terms of native clock value (least…
23262 …CONN_PING_TIMER_NEXT_EXP_WRAP will provide the correct status of ping timer duration.</description>
23270 <description>LE Ping Timer wrap count</description>
23279 … <description>This register holds the current position of the Ping timer.</description>
23287 <description>Transmit enable extension delay</description>
23296 …description>Transmit enable extension delay. This is to extend the active state (high) of rif_tx_e…
23302 …description>receiver enable extension delay. This is to extend the active state (high) of dbus_rx_…
23308 …<description>2Mbps demod delay delta compare to 1Mbps demod delay. This data is 2's comp data.</de…
23314 …<description>2Mbps modulation delay delta compare to 1Mbps demod delay. This data is 2's comp data…
23322 <description>Transmit/Receive enable delay</description>
23331 …<description>The delay used to assert rif_rx_en, Rx_tRamp micro-seconds, ahead of first bit of the…
23334 Rx_tRamp = Radio receiver rampup time</description>
23340 …<description>The delay used to assert rif_tx_en exactly Tx_tRamp micro-seconds ahead of the first …
23343 Tx_tRamp = Radio transmitter ramp_up</description>
23351 <description>External TX PA and RX LNA delay configuration</description>
23360 …<description>The delay used to assert LNA_CTL, LNA_tRamp micro-seconds, ahead of first bit of the …
23363 LNA_tRamp = External Low Noise Amplifier startup time</description>
23369 …<description>The delay used to assert PA_CTL exactly PA_tRamp micro-seconds ahead of the first bit…
23372 PA_tRamp = External Power Amplifier ramp time</description>
23380 <description>Link Layer additional configuration</description>
23389 … <description>Controls the RSSI reads. When this bit is 1, the bit RSSI_INTR_SEL is don't care.
23392 When RCB Interface is operating 4Mhz are lower this bit should be set to 1'b0.</description>
23398 <description>Controls the mode of issueing TX_EN & RX_EN to the Radio
23400 0 - TX_EN and RX_EN are issued through RCB writes</description>
23406 …description>Setting this bit enables the tx 1MHz pulse to match the received bpktctl from CYBLERD5…
23412 <description>Controls the wakeup timer configuration
23414 0 - Wakeup time is not compensated with the LF_OFFSET as in legacy mode</description>
23420 …<description>Controls the engine interrupt generation based on RSSI reads. This is valid only if R…
23422 1 - Receive interrupts are triggerred after the last bit of CRC</description>
23428 … <description>Controls the early RSSI reads. This is applicable only when RSSI_SEL is 1.
23430 0 - RSSI read is initiated during the third CRC byte reception.</description>
23436 …<description>Controls the delay from DBUS_TX, DBUS_RX assertion to the assertion on the pins. This…
23438 1 - The pin assertion is delayed by 8 cycles.</description>
23444 <description>Controls the TX power level format given to the CYBLERD55 chip.
23446 …WER_LVL_LS} for connection channel packets. This setting is directly given to the PA.</description>
23452 <description>Controls the RSSI reads.
23454 …nel Energy read is initiated at the end of the receive cycle if no packet is received</description>
23460 <description>Controls the RSSI reads.
23462 1 - RSSI read is initiated for zero length and aborted packets</description>
23468 …<description>Controls the RCB update to radio on TX/RX enable. Applicable only when TX_RX_CTRL_SEL…
23471 …TX_RX_CTRL_SEL is 1'b1 and ENABLE_RADIO_BOD is 1'b1, this bit needs to be set to 1'b1</description>
23477 <description>Controls the duplicate connection checkin ADV and INIT
23479 …nection before a new connection is created and aborts a duplicate connection creation</description>
23485 <description>Controls the LPM entry condition
23487 1 - MMMS mode LPM entry check</description>
23493 …<description>Controls the ADV behavior while advertising ADV_DIR and only device privacy is set. W…
23495 1 - Check the address against PEER_SEC_ADDR_ADV and create connection on a match.</description>
23503 <description>LL Backward compatibility</description>
23512 <description>Enables Privacy 1.2 Feature.</description>
23518 … <description>Enables Data Length extension feature in DTM, connection and encryption modules.
23519 This bit should always be set to 1'b1. 1'b0 is not supported.</description>
23525 <description>The Whilelist read logic is controlled using this bit.
23527 … whitelist address range is treated an memory reads. Any whilelist entry can be read.</description>
23533 <description>Controls the ADVCH FIFO flushing when PRIV_1_2 is enabled.
23535 1 - Does not flush any CRC good packets</description>
23541 …<description>This bit indicates that the resolving list in the hardware is full and the list is ex…
23543 …st should be followed by copying the matching entry into the hardware resolving list.</description>
23549 …<description>This bit controls the ADV engine behavior when an initiator address match occurs but …
23551 1 - The packet is received and reported to the Link Layer firmware</description>
23557 …<description>This bit controls the ADV engine behavior when a scanner address match occurs but a p…
23559 1 - The packet is received and reported to the Link Layer firmware</description>
23565 …<description>This bit controls the SCAN engine behavior when an peer address match occurs but a pr…
23567 1 - The packet is received and reported to the Link Layer firmware</description>
23573 …<description>This bit controls the INIT engine behavior when an peer address match occurs but a pr…
23575 1 - The packet is received and reported to the Link Layer firmware</description>
23581 …<description>This bit controls the INIT engine behavior when a self address match occurs but a pri…
23583 1 - The packet is received and reported to the Link Layer firmware</description>
23589 <description>Enables Privacy 1.2 for ADV engine</description>
23595 <description>Enables Privacy 1.2 for SCAN engine</description>
23601 <description>Enables Privacy 1.2 for INIT engine</description>
23607 …<description>This bit controls the Connection RX enable modification mode when SLV_CONN_PEER_RPA_N…
23609 …nable is during the Peer INIT RPA unresolved state is modified, until it is resolved.</description>
23615 …<description>This bit is asserted when SLV_CONN_PEER_RPA_UNMCH_INTR is set. The device does not en…
23616 This bit is valid only if PRIV_1_2 is set.</description>
23622 <description>When set, flushes the ADVCH FIFO. The bit is auto cleared.
23623 …started reading the FIFO, then the FIFO must be emptied exclusively by firmware reads</description>
23631 … <description>Device Resolvable/Non-Resolvable Private address lower register</description>
23640 … <description>Lower 16 bit of 48-bit Random Private address of the device.</description>
23648 … <description>Device Resolvable/Non-Resolvable Private address middle register</description>
23657 … <description>Middle 16 bit of 48-bit Random Private address of the device.</description>
23665 … <description>Device Resolvable/Non-Resolvable Private address higher register</description>
23674 … <description>Higher 16 bit of 48-bit Random Private address of the device.</description>
23684 <description>Resolving list entry control bit</description>
23693 <description>Indicates if the index is valid</description>
23699 <description>Indicates if the listed peer device has shared its IRK.
23701 …cepted. An Identity address in the received packet is reported as a privacy mismatch.</description>
23707 <description>Indicates if the local IRK has been shared with the listed peer device
23709 …ed. A Self Identity address in the received packet is reported as a privacy mismatch.</description>
23715 <description>Indicates if the listed peer device is in the whitelist</description>
23721 <description>Indicates the address type of the listed peer device</description>
23727 <description>Indicates that the peer device RPA in the list is valid</description>
23733 <description>Indicates that the received self RPA in the list is valid</description>
23739 … <description>Indicates that the self RPA in the list to be transmitted is valid</description>
23745 …<description>When Initiator whitelist is disabled, this bit indicates the specific device to from …
23751 <description>Indicates the TX addr type to be used for SCANA and INITA
23753 …bit in SELF_ADDR_TX_RPA_VAL above is used in SCANA/INITA in SCAN_REQ/CONN_REQ packets</description>
23759 … <description>Indicates if the entry is already in connection with our device</description>
23767 <description>whitelist valid entry bit</description>
23776 …<description>Stores the connection status of each of the sixteen device address stored in the whit…
23778 0 - White list entry is not in a connection</description>
23786 <description>DLE Connection RX memory base address</description>
23795 …<description>Data from Rx memory are read as 32-bit wide data. This memory is valid only if DLE is…
23803 <description>DLE Connection TX memory base address</description>
23812 …<description>Data to Tx memory are written as 32-bit wide data. This memory is valid only if DLE i…
23820 <description>Connection Parameter memory base address for connection 1</description>
23829 <description>N/A</description>
23837 <description>Connection Parameter memory base address for connection 2</description>
23846 <description>N/A</description>
23854 <description>Connection Parameter memory base address for connection 3</description>
23863 <description>N/A</description>
23871 <description>Connection Parameter memory base address for connection 4</description>
23880 <description>N/A</description>
23888 <description>Next Instant Timer</description>
23897 …description>BT Slot at which the next connection has to be serviced, granularity is 625us. The NI …
23905 <description>Micro-second Offset</description>
23914 …description>Micro Second Offset from the Slot Bounday at which the connection programmed in NEXT_C…
23922 <description>Next Connection</description>
23931 … <description>Connection Index to be serviced. Allowed values are 0,1,2,3.</description>
23937 <description>Connection type
23939 0 - Slave Connection</description>
23945 …description>Flag indication if programmed NI_TIMER is valid. FW sets this bit to indicate that the…
23953 <description>Abort next scheduled connection</description>
23962 <description>Setting this bit clears the schedule NI</description>
23968 <description>This bit will set if the scheduled NI is aborted</description>
23976 <description>Connection NI Status</description>
23985 …description>HW updates this register with the next Connection Instant for current serviced connect…
23993 <description>Next Supervision timeout Status</description>
24002 …<description>HW updates this register for the SuperVision timeout next instant, granularity is 625…
24010 <description>Connection Status</description>
24019 … <description>Connection Index that was serviced. Legal values are 0,1,2,3.</description>
24025 <description>Connection type
24027 0 - Slave Connection</description>
24033 <description>Sequence Number of Packets exchanged</description>
24039 <description>Next Sequence Number</description>
24045 <description>Last Unmapped Channel</description>
24051 <description>1 - Packet Missed
24052 0 - Connection exchanged packets</description>
24058 <description>Anchor Point State
24060 1 - Anchor point established</description>
24068 <description>BT Slot Captured Status</description>
24077 …<description>During slave connection event, HW updates this register with the captured BT_SLOT at …
24085 <description>Micro-second Capture Status</description>
24094 …<description>During slave connection event, HW updates this register with the captured microsecond…
24102 <description>Micro-second Offset Status</description>
24111 …description>During slave connection event, HW updates this register with the calculated us_offset …
24119 <description>Accumulated Window Widen Status</description>
24128 …<description>Accumulated Window Widen Value. HW updates this register at the close of slave connec…
24136 <description>Status when early interrupt is raised</description>
24145 <description>Connection Index for which early interrupt is raised</description>
24151 <description>Connection type for which early interrupt is raised.</description>
24157 <description>US offset when early interrupt is raised</description>
24165 <description>Multi-Master Multi-Slave Config</description>
24174 <description>Configuration bit to enable MMMS functionality</description>
24180 …<description>If set to 1'b1 and MMMS enabled, then the parameters received in connection request a…
24181 This bit is intended as a fail-safe. Should not be changed dynamically during runtime</description>
24187 …<description>By default on end_ce, the connection parameters memory is loaded with the updated con…
24188 This bit is intended as a fail-safe. Should not be changed dynamically during runtime</description>
24194 …<description>By default the parameters for the connection are picked up from the connection parame…
24197 This bit is intended as a fail-safe. Should not be changed dynamically during runtime</description>
24203 … <description>This field specifies the connection index for which ADV is enabled</description>
24209 <description>Enable for CE length immediate expiry</description>
24215 <description>Setting this bit resets the receive FIFO pointers</description>
24223 <description>Running US of the current BT Slot</description>
24232 <description>Current value of the US Counter</description>
24240 <description>Previous captured US of the BT Slot</description>
24249 …description>HW uses this register to load the us_offset from connection parameter memory. This can…
24257 <description>NI at early interrupt</description>
24266 … <description>Connection Next instant when the early interrupt is triggered</description>
24274 <description>BT slot capture for master connection creation</description>
24283 …<description>This register captures the BT_SLOT when master connection is created, granularity is …
24291 <description>BT slot capture for slave connection creation</description>
24300 …<description>This register captures the BT_SLOT when slave connection is created, granularity is 6…
24308 <description>Micro second capture for slave connection creation</description>
24317 …<description>This register captures the us when slave connection is created, granularity is 1us</d…
24327 <description>Data buffer descriptor 0 to 15</description>
24336 <description>N/A</description>
24342 …<description>This field indicates the length of the data packet. Bits [9:7] are valid only if DLE …
24343 Range 0x00 to 0xFF.</description>
24351 <description>data list sent update and status for connection 1</description>
24360 … <description>Write:Indicates the buffer index for which the SENT bit is being updated by firmware.
24367 …e other FIFOs are empty or hardware has cleared them after receiving acknowledgement.</description>
24373 … <description>Write: Used to set the SENT bit in hardware for the selected packet buffer.
24377 …ent from the remote device, firmware clears BIT7 along with the list_index specified.</description>
24383 …description>Write: Indicates the buffer number for which SENT bit is updated by firmware. This is …
24391 <description>data list ack update and status for connection 1</description>
24400 … <description>Write: Indicates the buffer index for which the ACK bit is being updated by firmware.
24406 …ed by the remote device. This acknowledgement is pending to be processed by firmware.</description>
24412 …<description>Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that …
24416 …CK bit in hardware is set by hardware when it has success-fully transmitted a packet.</description>
24424 <description>Connection specific pause resume for connection 1</description>
24433 …<description>Data list index for start/resume. This field must be valid along with data_list_head_…
24435 Hardware will start the next data transmission from the index indicated by this field.</description>
24441 …<description>Update the first packet buffer index ready for transmis-sion to start/resume data tra…
24442 The bit must be set every time the firmware needs to indicate the start/resume.</description>
24448 … <description>This bit is set to configure the MD bit control when the design is in slave mode.
24451 This bit has valid only when MD_BIT_CLEAR bit is not set</description>
24457 … <description>MD bit set to '1' indicates device has more data to be sent.</description>
24463 …<description>This register field indicates whether the MD (More Data) bit needs to be controlled b…
24469 … there is an acknowledgement awaited from the remote side for the packet transmitted.</description>
24475 <description>Pause data.
24479 …ENT bit is set for the current_pdu_index as which pause is set, data will be sent out</description>
24485 … <description>Kills the connection immediately when the connection event is active</description>
24491 …<description>Kills the connection when the connection event is active and a TX is completed</descr…
24497 …<description>This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cle…
24503 …<description>The index of the transmit packet buffer that is currently in transmission/waiting for…
24511 <description>data list sent update and status for connection 2</description>
24520 … <description>Write:Indicates the buffer index for which the SENT bit is being updated by firmware.
24527 …e other FIFOs are empty or hardware has cleared them after receiving acknowledgement.</description>
24533 … <description>Write: Used to set the SENT bit in hardware for the selected packet buffer.
24537 …ent from the remote device, firmware clears BIT7 along with the list_index specified.</description>
24543 …description>Write: Indicates the buffer number for which SENT bit is updated by firmware. This is …
24551 <description>data list ack update and status for connection 2</description>
24560 … <description>Write: Indicates the buffer index for which the ACK bit is being updated by firmware.
24566 …ed by the remote device. This acknowledgement is pending to be processed by firmware.</description>
24572 …<description>Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that …
24576 …CK bit in hardware is set by hardware when it has success-fully transmitted a packet.</description>
24584 <description>Connection specific pause resume for connection 2</description>
24593 …<description>Data list index for start/resume. This field must be valid along with data_list_head_…
24595 Hardware will start the next data transmission from the index indicated by this field.</description>
24601 …<description>Update the first packet buffer index ready for transmis-sion to start/resume data tra…
24602 The bit must be set every time the firmware needs to indicate the start/resume.</description>
24608 … <description>This bit is set to configure the MD bit control when the design is in slave mode.
24611 This bit has valid only when MD_BIT_CLEAR bit is not set</description>
24617 … <description>MD bit set to '1' indicates device has more data to be sent.</description>
24623 …<description>This register field indicates whether the MD (More Data) bit needs to be controlled b…
24629 … there is an acknowledgement awaited from the remote side for the packet transmitted.</description>
24635 <description>Pause data.
24639 …ENT bit is set for the current_pdu_index as which pause is set, data will be sent out</description>
24645 … <description>Kills the connection immediately when the connection event is active</description>
24651 …<description>Kills the connection when the connection event is active and a TX is completed</descr…
24657 …<description>This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cle…
24663 …<description>The index of the transmit packet buffer that is currently in transmission/waiting for…
24671 <description>data list sent update and status for connection 3</description>
24680 … <description>Write:Indicates the buffer index for which the SENT bit is being updated by firmware.
24687 …e other FIFOs are empty or hardware has cleared them after receiving acknowledgement.</description>
24693 … <description>Write: Used to set the SENT bit in hardware for the selected packet buffer.
24697 …ent from the remote device, firmware clears BIT7 along with the list_index specified.</description>
24703 …description>Write: Indicates the buffer number for which SENT bit is updated by firmware. This is …
24711 <description>data list ack update and status for connection 3</description>
24720 … <description>Write: Indicates the buffer index for which the ACK bit is being updated by firmware.
24726 …ed by the remote device. This acknowledgement is pending to be processed by firmware.</description>
24732 …<description>Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that …
24736 …CK bit in hardware is set by hardware when it has success-fully transmitted a packet.</description>
24744 <description>Connection specific pause resume for connection 3</description>
24753 …<description>Data list index for start/resume. This field must be valid along with data_list_head_…
24755 Hardware will start the next data transmission from the index indicated by this field.</description>
24761 …<description>Update the first packet buffer index ready for transmis-sion to start/resume data tra…
24762 The bit must be set every time the firmware needs to indicate the start/resume.</description>
24768 … <description>This bit is set to configure the MD bit control when the design is in slave mode.
24771 This bit has valid only when MD_BIT_CLEAR bit is not set</description>
24777 … <description>MD bit set to '1' indicates device has more data to be sent.</description>
24783 …<description>This register field indicates whether the MD (More Data) bit needs to be controlled b…
24789 … there is an acknowledgement awaited from the remote side for the packet transmitted.</description>
24795 <description>Pause data.
24799 …ENT bit is set for the current_pdu_index as which pause is set, data will be sent out</description>
24805 … <description>Kills the connection immediately when the connection event is active</description>
24811 …<description>Kills the connection when the connection event is active and a TX is completed</descr…
24817 …<description>This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cle…
24823 …<description>The index of the transmit packet buffer that is currently in transmission/waiting for…
24831 <description>data list sent update and status for connection 4</description>
24840 … <description>Write:Indicates the buffer index for which the SENT bit is being updated by firmware.
24847 …e other FIFOs are empty or hardware has cleared them after receiving acknowledgement.</description>
24853 … <description>Write: Used to set the SENT bit in hardware for the selected packet buffer.
24857 …ent from the remote device, firmware clears BIT7 along with the list_index specified.</description>
24863 …description>Write: Indicates the buffer number for which SENT bit is updated by firmware. This is …
24871 <description>data list ack update and status for connection 4</description>
24880 … <description>Write: Indicates the buffer index for which the ACK bit is being updated by firmware.
24886 …ed by the remote device. This acknowledgement is pending to be processed by firmware.</description>
24892 …<description>Write: Firmware uses the field to clear and ACK bit in the hardware to indicate that …
24896 …CK bit in hardware is set by hardware when it has success-fully transmitted a packet.</description>
24904 <description>Connection specific pause resume for connection 4</description>
24913 …<description>Data list index for start/resume. This field must be valid along with data_list_head_…
24915 Hardware will start the next data transmission from the index indicated by this field.</description>
24921 …<description>Update the first packet buffer index ready for transmis-sion to start/resume data tra…
24922 The bit must be set every time the firmware needs to indicate the start/resume.</description>
24928 … <description>This bit is set to configure the MD bit control when the design is in slave mode.
24931 This bit has valid only when MD_BIT_CLEAR bit is not set</description>
24937 … <description>MD bit set to '1' indicates device has more data to be sent.</description>
24943 …<description>This register field indicates whether the MD (More Data) bit needs to be controlled b…
24949 … there is an acknowledgement awaited from the remote side for the packet transmitted.</description>
24955 <description>Pause data.
24959 …ENT bit is set for the current_pdu_index as which pause is set, data will be sent out</description>
24965 … <description>Kills the connection immediately when the connection event is active</description>
24971 …<description>Kills the connection when the connection event is active and a TX is completed</descr…
24977 …<description>This bit indicates if EMPTYPDU has been sent. IF ACK is received this bit will be cle…
24983 …<description>The index of the transmit packet buffer that is currently in transmission/waiting for…
24991 <description>Enable bits for ADV_NI, SCAN_NI and INIT_NI</description>
25000 …<description>This bit is used to enable the Advertisement NI timer and is valid when MMMS_ENABLE=1.
25004 In this mode, the adv engine next instant is scheduled by firmware</description>
25010 … <description>This bit is used to enable the SCAN NI timer and is valid when MMMS_ENABLE=1.
25014 In this mode, the scan engine next instant is scheduled by firmware</description>
25020 … <description>This bit is used to enable the INIT NI timer and is valid when MMMS_ENABLE=1.
25024 In this mode, the init engine next instant is scheduled by firmware</description>
25032 <description>Next instant valid for ADV, SCAN, INIT</description>
25041 …<description>This bit indicates if the programmed advertisement NI_TIMER is valid. FW sets this bi…
25043 1 - ADV_NI timer is valid</description>
25049 …<description>This bit indicates if the programmed scan NI_TIMER is valid. FW sets this bit to indi…
25051 1 - SCAN_NI timer is valid</description>
25057 …<description>This bit indicates if the programmed initiator NI_TIMER is valid. FW sets this bit to…
25059 1 - INIT_NI timer is valid</description>
25067 <description>Abort the next instant of ADV, SCAN, INIT</description>
25076 …description>FW can use this bit to clear an unserviced NI_VALID for Advertisement or scanner or in…
25082 …description>The link layer hardware logic will set this bit when the NI_TIMER is aborted. Firmware…
25090 …<description>Register to configure the supervision timeout for next scheduled connection</descript…
25099 …description>HW uses this register to load the Supervision timeout Next instant from the connection…
25107 …<description>Register to configure Accumulated window widening for next scheduled connection</desc…
25116 …description>HW uses this register to load the accumulated window windeing value from the connectio…
25124 …<description>Register to configure offset from connection anchor point at which connection paramet…
25133 …<description>Load Offset in us before connection event at which the connection parameters are load…
25141 <description>Random number generated by Hardware for ADV NI calculation</description>
25150 …<description>Random ADV delay, to be used for ADV next instant calculation. The granularity is in …
25158 <description>Packet Counter of packets in RX FIFO in MMMS mode</description>
25167 <description>Count of all packets in the RX FIFO in MMMS mode</description>
25177 <description>Packet Counter for Individual connection index</description>
25186 …description>Number of packets received for the connection. Incremented when the packet is received…
25194 <description>Whitelist base address</description>
25203 …<description>Device address values written to white list memory are written as 16-bit wide address…
25211 <description>Resolving list base address for storing Peer Identity address</description>
25220 …<description>Device address values written to the list are written as 16-bit wide address.</descri…
25228 … <description>Resolving list base address for storing resolved Peer RPA address</description>
25237 …<description>Device address values written to the list are written as 16-bit wide address.</descri…
25245 … <description>Resolving list base address for storing Resolved received INITA RPA</description>
25254 …<description>Device address values written to the list are written as 16-bit wide address.</descri…
25262 … <description>Resolving list base address for storing generated TX INITA RPA</description>
25271 …<description>Device address values written to the list are written as 16-bit wide address.</descri…
25280 <description>Bluetooth Low Energy Subsystem Miscellaneous</description>
25284 <description>BLESS DDFT configuration register</description>
25293 <description>Enables the DDFT output from BLESS
25295 0: DDFT is disabled</description>
25301 <description>Enables the DDFT inputs from CYBLERD55 chip
25303 0: DDFT inputs are disabled</description>
25309 <description>dbg_mux_pin1 selection, combine with BLERD and BLESS
25341 5'h1F 1'b0</description>
25347 <description>dbg_mux_pin2 selection, combine with BLERD and BLESS
25379 5'h1F enable_ldo_dly</description>
25387 <description>Crystal clock divider configuration register</description>
25396 …<description>System clock pre-divider value. The 24 MHz crystal clock is divided to generate the s…
25400 3: DIV_BY_8: SYSCLK= XTALCLK/8</description>
25406 …<description>Link Layer clock pre-divider value. The 24 MHz crystal clock is divided to generate t…
25410 3: DIV_BY_8: LLCLK= XTALCLK/8</description>
25418 <description>Link Layer interrupt status register</description>
25427 …description>On a firmware request to LL to enter into state machine, working on LF clock, LL trans…
25433 …description>On a firmware request to LL to exit from Deep Sleep Mode, working on LF clock, LL tran…
25439 <description>RCB transaction Complete</description>
25445 <description>CYBLERD55 is in active mode. RF is active</description>
25451 … <description>RCB controller Interrupt - Refer to RCB_INTR_STAT register</description>
25457 <description>LL controller interrupt - Refer to EVENT_INTR register</description>
25463 <description>GPIO interrupt</description>
25469 …<description>This bit when set by efuse controller logic when the efuse read/write is completed</d…
25475 …<description>enabled crystal stable signal rising edge interrupt. The interrupt can be cleared by …
25481 <description>Encryption Interrupt Triggered</description>
25487 …description>This interrupt is set on HVLDO LV Detector Rise edge. There is a 1cycle AHB clock glit…
25493 …description>This interrupt is set on HVLDO LV Detector Fall edge. There is a 1cycle AHB clock glit…
25501 <description>Link Layer interrupt mask register</description>
25510 …<description>When the Link Layer is in Deep Sleep Mode, firmware can set this bit to wake the Link…
25516 <description>Masks the DSM Entered Interrupt, when disabled.</description>
25522 <description>Masks the DSM Exited Interrupt, when disabled.</description>
25528 <description>Masks the Crystal Stable Interrupt, when disabled.</description>
25534 <description>Mask for RCBLL interrupt</description>
25540 <description>Mask for CYBLERD55 Active Interrupt</description>
25546 <description>Mask for RCB interrupt</description>
25552 <description>Mask for LL interrupt</description>
25558 <description>Mask for GPIO interrupt</description>
25564 <description>This bit enables the efuse interrupt to firmware</description>
25570 <description>Mask for Encryption interrupt</description>
25576 <description>Mask for HVLDO LV Detector Rise edge interrupt</description>
25582 <description>Mask for HVLDO LV Detector Fall edge interrupt</description>
25590 <description>Link Layer primary clock enable</description>
25599 <description>Set this bit 1 to enable the clock to Link Layer.</description>
25605 …<description>If MXD_IF option is 1, this bit needs to be set to enable configuring the correlator …
25611 <description>1: MXD IF option 0: CYBLERD55 correlates Access Code
25612 0: MXD IF option 1: LL correlates Access Code</description>
25618 <description>0: AHB clock (clk_sys) is used as the clock for RCB access
25619 1: LL clock (clk_eco) is used as the clock for RCB access</description>
25625 <description>0: No Soft Reset
25627 Setting this bit will reset entire BLESS_VER3</description>
25633 …<description>Controls the DPSLP entry and exit writes to RD and controls the active domain reset a…
25635 0 - The RD active domain reset and clock. Must be controlled by the FW</description>
25643 <description>BLESS LF clock control and BLESS revision ID indicator</description>
25652 …description>When set to 1, gates the LF clock input to the Link Layer. Ths is done for extended DS…
25658 <description>This bit is used to enable the clock to the encryption engine
25660 1 - Enable the clock to ENC engine</description>
25666 <description>Indicates the m0s8bless IP revision.</description>
25674 <description>External TX PA and RX LNA control</description>
25683 <description>When set to 1, enables the external PA & LNA</description>
25689 <description>Controls the polarity of the chip enable control signal
25691 1 - Low enable, High disable</description>
25697 <description>Controls the polarity of the PA control signal
25699 1 - Low enable, High disable</description>
25705 <description>Controls the polarity of the LNA control signal
25707 1 - Low enable, High disable</description>
25713 … <description>Configures the drive value on the output enables of PA, LNA and CHI_EN signals
25715 1 - drive 1 on the output enable signals</description>
25723 … <description>Link Layer Last Received packet RSSI/Channel energy and channel number</description>
25732 …description>This field captures the RSSI of the packet when a packet reception is complete or give…
25738 … <description>This field indicates the last channel for which the RSSI is captured</description>
25744 …<description>This field indicates if the captured RSSI is for a received packet or is the channel …
25752 <description>BT clock captured on an LL DSM exit</description>
25761 …description>This field captures the LF BT clock captured on an LL DSM exit. This register is valid…
25769 <description>MT Configuration Register</description>
25778 <description>This register bit needs to be set to enable CYBLERD55
25781 On power up this bit needs to be set to make CYBLERD55 active.</description>
25787 <description>This register bit indicates the source for PSoC DeepSleep exit to BLESS
25789 1'b1 - MT_CFG.DEEPSLEEP_EXITED indicates PSoC DeepSleep exit</description>
25795 … <description>This register bit is used by FW to indicate that PSoC is out of DeepSleep
25798 This bit is cleared by HW on exit from DPSLP</description>
25804 …<description>This register bit specifies whether the Active LDO or BUCK in CYBLERD55 is used in ac…
25810 …<description>This register should be set to override the HW generated signal to HVLDO. When set HV…
25816 <description>Override value for HVLDO BYPASS
25818 1'b1: Do not bypass the HVLDO</description>
25824 …description>This register should be set to override the HW generated signal to enable ACTIVE_LDO/B…
25830 <description>Override value for ACT_LDO_EN/BUCK_EN</description>
25836 …description>This register should be set to override the HW generated signal to Digital regulator o…
25842 <description>Override value for digital regulator of CYBLERD55</description>
25848 …description>This register should be set to override the HW generated signal to the retention switc…
25854 <description>Override value for RET_SWITCH</description>
25860 …<description>This register should be set to override the HW generated isolation signal to CYBLERD5…
25866 <description>Override value for isolation to CYBLERD55</description>
25872 …<description>This register should be set to override the HW generated ECO Clock gate. When set LL_…
25878 <description>Override value for LL Clock gate</description>
25884 …<description>This register should be set to override the HW generated enable to HVLSO. When set HV…
25890 <description>Overrie value for HVLDO enable
25892 1'b0: switch to standby LDO</description>
25898 …description>This bit when set indicates that ECO clock should be kept on even in BLESS DPSLP. This…
25904 …<description>This register should be set to override the HW generated reset to CYBLERD55. When set…
25910 <description>Overrie value for CYBLERD55 RESET_N</description>
25916 …<description>This register should be set to override the HW generated XTAL_EN to CYBLERD55. When s…
25922 <description>Overrie value for CYBLERD55 XTAL_EN</description>
25928 …<description>This register should be set to override the HW generated CLK_EN to CYBLERD55. When se…
25934 <description>Overrie value for CYBLERD55 CLK_EN</description>
25940 …<description>This register should be set to override the HW generated RET_LDO_OL_HV to CYBLERD55. …
25946 <description>Overrie value for CYBLERD55 RET_LDO_OL_HV</description>
25952 <description>Reset for HVLDO
25954 1'b0 - HVLDO Enabled</description>
25962 <description>MT Delay configuration for state transitions</description>
25971 …description>This register specifies the startup delay for the HVLDO interms of number of LF Clock …
25977 …<description>This register specifies the time from switching the CYBLERD55 logic to Active regulat…
25983 …<description>This register specifies the time from assertion of ISOLATE_N to switching the CYBLERD…
25989 …<description>This register specifies the time from disabling XTAL to switching of the HVLDO.</desc…
25997 <description>MT Delay configuration for state transitions</description>
26006 …description>This register specifies the time for OSC Startup. After this delay, clock is enabled t…
26012 …description>This register specifies the pre-processing time required in Link Layer. This is esenti…
26018 …description>This register specifes the Active Regulator startup time in CYBLERD55. The delay is in…
26024 …description>This register specifes the Digital LDO startup time in CYBLERD55.The delay is in terms…
26032 <description>MT Delay configuration for state transitions</description>
26041 …<description>This register specifies the time from switching of logic to Retention LDO in CYBLERD5…
26043 …DELAY should be the sum of DIG_LDO_DISABLE_DELAY and the powerdown time of ACTIVE_LDO</description>
26049 …<description>This field holds the delay from the time of diabling Digital LDO to the time at which…
26055 …<description>This field holds the delay after HVLDO Startup to VDDR Stable. Refer to memo AKK-410<…
26063 <description>MT Configuration Register to control VIO switches</description>
26072 <description>Enable to turn on HVLDO (One leg)
26074 1'b1 - Switch is turned on</description>
26080 …<description>Enable to turn on HVLDO (All legs). This must be enabled 64us after enabling SRSS_SWI…
26082 1'b1 - Switch is turned on</description>
26090 <description>MT Status Register</description>
26099 <description>1'b0 - BLESS in DPSLP state
26100 1'b1 - BLESS in ACTIVE state</description>
26106 <description>This register reflects the current state of the MT FSM
26117 4'hA - HVLDO_DISABLE</description>
26123 <description>This register reflects the current state of the HVLDO Startup FSM
26128 3'h4 - HVLDO_SET_BYPASS</description>
26134 …<description>This bit indicates when the Link Layer registers are accessible upon a DSM exit. This…
26136 1'b1 - Link Layer clock is active</description>
26144 <description>Link Layer Power Control FSM Status Register</description>
26153 <description>This register reflects the current state of the LL Power Control FSM
26160 4'h7 - REQ_RF_OFF</description>
26168 <description>HVLDO Configuration register</description>
26177 <description>ADFT enable</description>
26183 <description>ADFT select</description>
26189 <description>Vref ext input enable.</description>
26195 <description>hvldo LV detect status</description>
26203 <description>Radio Buck and Active regulator enable control</description>
26212 <description>Buck enable control. This must be programmed before enabling the Radio.
26214 1'b0 - Buck enable output to radio is controlled from Mode transition FSM</description>
26220 … <description>Active regulator enable control. This must be programmed before enabling the Radio.
26222 1'b1 - Active regulator enable output to radio is controlled from Mode transition FSM</description>
26228 <description>Controls the LPM drift calculation.
26230 0 - Disables the LPM drift mod</description>
26236 <description>Controls the LPM drift multi level compensation.
26238 0 - Disables the LPM drift multi comp</description>
26244 <description>Controls the LPM entry control mode
26246 … LPM must not be entered in the same slot or the subsequent slot as the last LPM exit</description>
26254 <description>EFUSE mode configuration register</description>
26263 <description>This register enables the efuse mode in m0s8bless_ver3</description>
26269 …<description>This bit when set by firmware enables the read from EFUSE macro. It is cleared when t…
26275 …<description>This bit when set by firmware enables the write to EFUSE macro. It is cleared when th…
26283 … <description>EFUSE timing control register (common for Program and Read modes)</description>
26292 <description>Decides the duration of TPGM (in Program mode) or TCKHP (in Read mode)
26294 TCKHP : SCLK high Period</description>
26300 <description>Duration of SCLK LOW (TCLKP_R) or TCKLP_P</description>
26306 … <description>This register specifies the setup time between CS and SCLK (TSR_CLK)</description>
26312 <description>This register specifies the hold time between CS and SCLK
26313 (THR_CLK)</description>
26319 …<description>This field decides setup time between RW & CS (TSR_RW: in read mode) or RW & …
26321 TSP_RW: RW to AVDD setup time into program mode</description>
26327 …<description>This field decides hold time between RW & CS (THR_RW: in read mode) or RW & A…
26329 THP_RW: RW to AVDD hold time out of program mode</description>
26337 <description>EFUSE timing control Register (for Read)</description>
26346 <description>This register specifies the time for data sampling from SCLK HIGH
26347 (TCKDQ_H)</description>
26353 <description>Wait time
26354 DOUT to CS hold time out of read mode (TDQH)</description>
26362 <description>EFUSE timing control Register (for Program)</description>
26371 <description>PGM to SCLK setup time (TS_PGM)
26372 PGM_SCLK_SETUP_TIME <CS_SCLK_SETUP_TIME</description>
26378 <description>PGM to SCLK hold time (TH_PGM)</description>
26384 <description>AVDD to CS setup time into program mode (TSP_AVDD_CS)</description>
26390 <description>AVDD to CS hold time out of program mode (THP_AVDD_CS)</description>
26398 <description>EFUSE Lower read data</description>
26407 … <description>This register has the read value from the Efuse macro, fuse bits[31:0]</description>
26415 <description>EFUSE higher read data</description>
26424 … <description>This register has the read value from the Efuse macro, fuse bits[63:32]</description>
26432 <description>EFUSE lower write word</description>
26441 … <description>This register has the write value to the Efuse macro, fuse bits[31:0]</description>
26449 <description>EFUSE higher write word</description>
26458 … <description>This register has the write value to the Efuse macro, fuse bits[63:32]</description>
26466 <description>Divide by 625 for FW Use</description>
26475 <description>This bit enables the divider for use by FW
26478 This divider can only be used in MMMS mode. Do not enable for legacy operation</description>
26484 <description>This field holds the dividend</description>
26492 <description>Output of divide by 625 divider</description>
26501 …<description>Quotient value from the divider. Available 1 cycle after dividend is programmed.</des…
26507 …<description>Remainder value from the divider. Available 1 cycle after dividend is programmed.</de…
26515 <description>Packet counter 0</description>
26524 …<description>Lower 32-bits of the packet counter value passed as part of Nonce for the packet to b…
26532 <description>Packet counter 2</description>
26541 …<description>Upper 8 bits of the packet counter value passed as part of Nonce for the packet to be…
26549 <description>Master Initialization Vector 0</description>
26558 …<description>This is the IVm field, which contains the master's portion of the initialization vect…
26566 <description>Slave Initialization Vector 0</description>
26575 …<description>This is the IVs field, which contains the slave's portion of the initialization vecto…
26585 <description>Encryption Key register 0-3</description>
26594 …<description>The encryption key / session key which is used in ECB encryption, CCM encryption and …
26602 <description>MIC input register</description>
26611 <description>This is the MIC field used for CCM decryption.</description>
26619 <description>MIC output register</description>
26628 <description>This is the MIC generated during CCM encryption.</description>
26636 <description>Encryption Parameter register</description>
26645 <description>LLID of the packet.</description>
26651 <description>Length of the input data.</description>
26657 …description>The directionBit shall be set to '1' for Data Channel PDUs sent by the master and set …
26663 …<description>3 Most significant bits of the LS byte of the length of the input data. Valid only wh…
26664 …LE is enabled total ENC payload length = {PAYLOAD_LENGTH_LSB_EXT, PAYLOAD_LENGTH_LSB}</description>
26670 … <description>Controls the encryption memory access mode. Valid only when DLE is enabled.
26672 1- The AES is pipelined while memory fetch/store in progress.</description>
26680 <description>Encryption Configuration</description>
26689 <description>1 Start the AES processing</description>
26695 <description>0 - CCM
26696 1 - ECB</description>
26702 <description>Decryption/Encryption
26704 1 - Decrypt</description>
26710 …<description>MS byte of the length of the input data when B0 needs to be completely configurable. …
26711 …d total ENC payload length = {PAYLOAD_LENGTH_MSB, PAYLOAD_LENGTH_MSB, PAYLOAD_LENGTH}</description>
26717 …<description>LS byte of the input data when B0 needs to be completely configurable. Valid only whe…
26723 … <description>Configuration to use B0 DATA provided by FW for CCM computation</description>
26731 <description>Encryption Interrupt enable</description>
26740 <description>Authentication interrupt enable
26742 1 - Enable</description>
26748 <description>ECB processed interrupt enable
26750 1 - Enable</description>
26756 <description>CCM processed interupt enable
26758 1 - Enable</description>
26766 <description>Encryption Interrupt status and clear register</description>
26775 <description>Authentication interrupt.
26778 Writing 1 to this register clears the interrupt.</description>
26784 <description>ECB processed interrupt.
26785 Writing 1 to this register clears the interrupt.</description>
26791 <description>CCM processed interrupt.
26792 Writing 1 to this register clears the interrupt</description>
26798 …<description>Clears the input data. Used for Zero padding of encryption for less than block sized …
26808 <description>Programmable B1 Data register (0-3)</description>
26817 <description>Programmable B1 Data register</description>
26825 <description>Encryption memory base address</description>
26834 …<description>Data values written to Enc memory are written as 16-bit wide data. This memory is val…
26842 <description>LDO Trim register 0</description>
26851 <description>To trim the regulated voltage in steps of 25mV typically</description>
26857 <description>To trim the bias currents for all the active mode blocks</description>
26865 <description>LDO Trim register 1</description>
26874 <description>To trim active regulator reference voltage</description>
26880 <description>To trim standby regulator reference voltage</description>
26888 <description>LDO Trim register 2</description>
26897 <description>To trim standby regulator beta-multiplier current</description>
26903 <description>To trim standby regulator beta-multiplier current</description>
26911 <description>LDO Trim register 3</description>
26920 <description>To trim the trip points of the LV-Detect block</description>
26926 <description>To trim standby regulator beta-multiplier temp-co slope</description>
26936 <description>MXD die Trim registers</description>
26945 <description>MXD trim bits</description>
26953 <description>LDO Trim register 4</description>
26962 <description>To debug post layout or post silicon</description>
26970 <description>LDO Trim register 5</description>
26979 <description>N/A</description>
26990 <description>USB Host and Device Controller</description>
27001 <description>USB Device</description>
27007 <description>Control End point EP0 Data Register</description>
27016 …description>This register is shared for both transmit and receive. The count in the EP0_CNT regist…
27024 <description>USB control 0 Register</description>
27033 …<description>These bits specify the USB device address to which the SIE will respond. This address…
27034 If USB bus reset is detected, these bits are initialized.</description>
27040 <description>This bit enables the device to respond to USB traffic.
27043 …on USB bus reset interrupt, and do not write to this bit during initialization steps.</description>
27051 <description>USB control 1 Register</description>
27060 …description>This bit controls the operation of the internal USB regulator. For applications with s…
27066 …description>This bit is set to turn on the automatic frequency locking of the internal oscillator …
27072 …<description>The Bus Activity bit is a stickybit that detects any non-idle USB event that has occu…
27073 value until firmware clears it.</description>
27079 <description>N/A</description>
27087 <description>USB SIE Data Endpoints Interrupt Enable Register</description>
27096 <description>Enables interrupt for EP1</description>
27102 <description>Enables interrupt for EP2</description>
27108 <description>Enables interrupt for EP3</description>
27114 <description>Enables interrupt for EP4</description>
27120 <description>Enables interrupt for EP5</description>
27126 <description>Enables interrupt for EP6</description>
27132 <description>Enables interrupt for EP7</description>
27138 <description>Enables interrupt for EP8</description>
27146 <description>USB SIE Data Endpoint Interrupt Status</description>
27155 <description>Interrupt status for EP1</description>
27161 <description>Interrupt status for EP2</description>
27167 <description>Interrupt status for EP3</description>
27173 <description>Interrupt status for EP4</description>
27179 <description>Interrupt status for EP5</description>
27185 <description>Interrupt status for EP6</description>
27191 <description>Interrupt status for EP7</description>
27197 <description>Interrupt status for EP8</description>
27205 <description>Non-control endpoint count register</description>
27214 …description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bi…
27220 …description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if C…
27226 <description>No ACK'd transactions since bit was last cleared.</description>
27231 <description>Indicates a transaction ended with an ACK.</description>
27238 …description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set…
27246 <description>Non-control endpoint count register</description>
27255 …description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register…
27263 <description>Non-control endpoint's control Register</description>
27272 …description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the …
27278 <description>Ignore all USB traffic to this endpoint</description>
27283 <description>SETUP: Accept
27285 OUT: NAK</description>
27290 <description>SETUP: Accept
27292 OUT: ACK 0B tokens, NAK others</description>
27297 <description>SETUP: Accept
27299 OUT: STALL</description>
27304 <description>SETUP: Ignore
27306 OUT: Accept Isochronous OUT token</description>
27311 <description>SETUP: Accept
27313 OUT: Stall</description>
27318 <description>SETUP: Ignore
27320 OUT: Ignore</description>
27325 <description>SETUP: Ignore
27327 OUT: NAK</description>
27332 <description>SETUP: Ignore
27335 Change to MODE=8 after one succesfull OUT token.</description>
27340 <description>SETUP: Accept
27342 OUT: Accept data</description>
27347 <description>SETUP: Ignore
27349 OUT: Ignore</description>
27354 <description>SETUP: Ignore
27356 OUT: Ignore</description>
27361 <description>SETUP: Accept
27363 OUT: ACK 0B tokens, NAK others</description>
27370 …description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the regi…
27376 <description>No ACK'd transactions since bit was last cleared.</description>
27381 <description>Indicates a transaction ended with an ACK.</description>
27388 …<description>When set this bit causes an endpoint interrupt to be generated even when a transfer c…
27394 …<description>The Error in transaction bit is set whenever an error is detected. For an IN transact…
27395 … error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
27401 …description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT.…
27409 <description>USBIO Control 0 Register</description>
27418 …<description>Received Data. This read only bit gives the state of the USB differential receiver wh…
27419 If D+=D- (SE0), this value is undefined.</description>
27425 <description>D+ < D- (K state)</description>
27430 <description>D+ > D- (J state)</description>
27437 …<description>Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0…
27443 <description>Force USB K state (D+ is low D- is high).</description>
27448 <description>Force USB J state (D+ is high D- is low).</description>
27455 …<description>Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0.</description>
27461 …<description>USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normall…
27462 transmitting is to force a resume state on the bus.</description>
27470 <description>USBIO control 2 Register</description>
27479 <description>N/A</description>
27485 …description>This bit enables the device to transmit a packet in response to an internally generate…
27491 <description>N/A</description>
27499 <description>USBIO control 1 Register</description>
27508 …<description>This read only bit gives the state of the D- pin when IOMODE bit is '0' and USB does…
27510 This bit is valid if USB Device.</description>
27516 …<description>This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn…
27518 This bit is valid if USB Device.</description>
27524 <description>N/A</description>
27530 …description>This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged …
27538 <description>USB Dynamic reconfiguration register</description>
27547 …<description>This bit is used to enable the dynamic re-configuration for the selected EP. If set t…
27548 Use 0 for EP1, 1 for EP2, etc.</description>
27554 …<description>These bits indicates the EP number for which reconfiguration is required when dyn_con…
27560 …description>This bit indicates the ready status for the dynamic reconfiguration, when set to 1, in…
27568 <description>Start Of Frame Register</description>
27577 <description>It has the lower 8 bits [7:0] of the SOF frame number.</description>
27585 <description>Start Of Frame Register</description>
27594 <description>It has the upper 3 bits [10:8] of the SOF frame number.</description>
27602 <description>Non-control endpoint count register</description>
27611 …description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bi…
27617 …description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if C…
27623 <description>No ACK'd transactions since bit was last cleared.</description>
27628 <description>Indicates a transaction ended with an ACK.</description>
27635 …description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set…
27643 <description>Non-control endpoint count register</description>
27652 …description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register…
27660 <description>Non-control endpoint's control Register</description>
27669 …description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the …
27675 <description>Ignore all USB traffic to this endpoint</description>
27680 <description>SETUP: Accept
27682 OUT: NAK</description>
27687 <description>SETUP: Accept
27689 OUT: ACK 0B tokens, NAK others</description>
27694 <description>SETUP: Accept
27696 OUT: STALL</description>
27701 <description>SETUP: Ignore
27703 OUT: Accept Isochronous OUT token</description>
27708 <description>SETUP: Accept
27710 OUT: Stall</description>
27715 <description>SETUP: Ignore
27717 OUT: Ignore</description>
27722 <description>SETUP: Ignore
27724 OUT: NAK</description>
27729 <description>SETUP: Ignore
27732 Change to MODE=8 after one succesfull OUT token.</description>
27737 <description>SETUP: Accept
27739 OUT: Accept data</description>
27744 <description>SETUP: Ignore
27746 OUT: Ignore</description>
27751 <description>SETUP: Ignore
27753 OUT: Ignore</description>
27758 <description>SETUP: Accept
27760 OUT: ACK 0B tokens, NAK others</description>
27767 …description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the regi…
27773 <description>No ACK'd transactions since bit was last cleared.</description>
27778 <description>Indicates a transaction ended with an ACK.</description>
27785 …<description>When set this bit causes an endpoint interrupt to be generated even when a transfer c…
27791 …<description>The Error in transaction bit is set whenever an error is detected. For an IN transact…
27792 … error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
27798 …description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT.…
27806 <description>Oscillator lock data register 0</description>
27815 …<description>These bits return the lower 8 bits of the oscillator locking circuits adder output.</…
27823 <description>Oscillator lock data register 1</description>
27832 …<description>These bits return the upper 7 bits of the oscillator locking circuits adder output.</…
27840 <description>Endpoint0 control Register</description>
27849 …description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the …
27855 <description>Ignore all USB traffic to this endpoint</description>
27860 <description>SETUP: Accept
27862 OUT: NAK</description>
27867 <description>SETUP: Accept
27869 OUT: ACK 0B tokens, NAK others</description>
27874 <description>SETUP: Accept
27876 OUT: STALL</description>
27881 <description>SETUP: Ignore
27883 OUT: Accept Isochronous OUT token</description>
27888 <description>SETUP: Accept
27890 OUT: Stall</description>
27895 <description>SETUP: Ignore
27897 OUT: Ignore</description>
27902 <description>SETUP: Ignore
27904 OUT: NAK</description>
27909 <description>SETUP: Ignore
27912 Change to MODE=8 after one succesfull OUT token.</description>
27917 <description>SETUP: Accept
27919 OUT: Accept data</description>
27924 <description>SETUP: Ignore
27926 OUT: Ignore</description>
27931 <description>SETUP: Ignore
27933 OUT: Ignore</description>
27938 <description>SETUP: Accept
27940 OUT: ACK 0B tokens, NAK others</description>
27947 …description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the regi…
27953 <description>No ACK'd transactions since bit was last cleared.</description>
27958 <description>Indicates a transaction ended with an ACK.</description>
27965 …description>When set this bit indicates a valid OUT packet has been received and ACKed. This bit i…
27971 …description>When set this bit indicates a valid IN packet has been received. This bit is updated t…
27977 …description>When set this bit indicates a valid SETUP packet was received and ACKed. This bit is f…
27985 <description>Endpoint0 count Register</description>
27994 …description>These bits indicate the number of data bytes in a transaction. For IN transactions fir…
28000 …description>This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0…
28006 <description>No ACK'd transactions since bit was last cleared.</description>
28011 <description>Indicates a transaction ended with an ACK.</description>
28018 …description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set…
28026 <description>Non-control endpoint count register</description>
28035 …description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bi…
28041 …description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if C…
28047 <description>No ACK'd transactions since bit was last cleared.</description>
28052 <description>Indicates a transaction ended with an ACK.</description>
28059 …description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set…
28067 <description>Non-control endpoint count register</description>
28076 …description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register…
28084 <description>Non-control endpoint's control Register</description>
28093 …description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the …
28099 <description>Ignore all USB traffic to this endpoint</description>
28104 <description>SETUP: Accept
28106 OUT: NAK</description>
28111 <description>SETUP: Accept
28113 OUT: ACK 0B tokens, NAK others</description>
28118 <description>SETUP: Accept
28120 OUT: STALL</description>
28125 <description>SETUP: Ignore
28127 OUT: Accept Isochronous OUT token</description>
28132 <description>SETUP: Accept
28134 OUT: Stall</description>
28139 <description>SETUP: Ignore
28141 OUT: Ignore</description>
28146 <description>SETUP: Ignore
28148 OUT: NAK</description>
28153 <description>SETUP: Ignore
28156 Change to MODE=8 after one succesfull OUT token.</description>
28161 <description>SETUP: Accept
28163 OUT: Accept data</description>
28168 <description>SETUP: Ignore
28170 OUT: Ignore</description>
28175 <description>SETUP: Ignore
28177 OUT: Ignore</description>
28182 <description>SETUP: Accept
28184 OUT: ACK 0B tokens, NAK others</description>
28191 …description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the regi…
28197 <description>No ACK'd transactions since bit was last cleared.</description>
28202 <description>Indicates a transaction ended with an ACK.</description>
28209 …<description>When set this bit causes an endpoint interrupt to be generated even when a transfer c…
28215 …<description>The Error in transaction bit is set whenever an error is detected. For an IN transact…
28216 … error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
28222 …description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT.…
28230 <description>Non-control endpoint count register</description>
28239 …description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bi…
28245 …description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if C…
28251 <description>No ACK'd transactions since bit was last cleared.</description>
28256 <description>Indicates a transaction ended with an ACK.</description>
28263 …description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set…
28271 <description>Non-control endpoint count register</description>
28280 …description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register…
28288 <description>Non-control endpoint's control Register</description>
28297 …description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the …
28303 <description>Ignore all USB traffic to this endpoint</description>
28308 <description>SETUP: Accept
28310 OUT: NAK</description>
28315 <description>SETUP: Accept
28317 OUT: ACK 0B tokens, NAK others</description>
28322 <description>SETUP: Accept
28324 OUT: STALL</description>
28329 <description>SETUP: Ignore
28331 OUT: Accept Isochronous OUT token</description>
28336 <description>SETUP: Accept
28338 OUT: Stall</description>
28343 <description>SETUP: Ignore
28345 OUT: Ignore</description>
28350 <description>SETUP: Ignore
28352 OUT: NAK</description>
28357 <description>SETUP: Ignore
28360 Change to MODE=8 after one succesfull OUT token.</description>
28365 <description>SETUP: Accept
28367 OUT: Accept data</description>
28372 <description>SETUP: Ignore
28374 OUT: Ignore</description>
28379 <description>SETUP: Ignore
28381 OUT: Ignore</description>
28386 <description>SETUP: Accept
28388 OUT: ACK 0B tokens, NAK others</description>
28395 …description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the regi…
28401 <description>No ACK'd transactions since bit was last cleared.</description>
28406 <description>Indicates a transaction ended with an ACK.</description>
28413 …<description>When set this bit causes an endpoint interrupt to be generated even when a transfer c…
28419 …<description>The Error in transaction bit is set whenever an error is detected. For an IN transact…
28420 … error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
28426 …description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT.…
28434 <description>Non-control endpoint count register</description>
28443 …description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bi…
28449 …description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if C…
28455 <description>No ACK'd transactions since bit was last cleared.</description>
28460 <description>Indicates a transaction ended with an ACK.</description>
28467 …description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set…
28475 <description>Non-control endpoint count register</description>
28484 …description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register…
28492 <description>Non-control endpoint's control Register</description>
28501 …description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the …
28507 <description>Ignore all USB traffic to this endpoint</description>
28512 <description>SETUP: Accept
28514 OUT: NAK</description>
28519 <description>SETUP: Accept
28521 OUT: ACK 0B tokens, NAK others</description>
28526 <description>SETUP: Accept
28528 OUT: STALL</description>
28533 <description>SETUP: Ignore
28535 OUT: Accept Isochronous OUT token</description>
28540 <description>SETUP: Accept
28542 OUT: Stall</description>
28547 <description>SETUP: Ignore
28549 OUT: Ignore</description>
28554 <description>SETUP: Ignore
28556 OUT: NAK</description>
28561 <description>SETUP: Ignore
28564 Change to MODE=8 after one succesfull OUT token.</description>
28569 <description>SETUP: Accept
28571 OUT: Accept data</description>
28576 <description>SETUP: Ignore
28578 OUT: Ignore</description>
28583 <description>SETUP: Ignore
28585 OUT: Ignore</description>
28590 <description>SETUP: Accept
28592 OUT: ACK 0B tokens, NAK others</description>
28599 …description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the regi…
28605 <description>No ACK'd transactions since bit was last cleared.</description>
28610 <description>Indicates a transaction ended with an ACK.</description>
28617 …<description>When set this bit causes an endpoint interrupt to be generated even when a transfer c…
28623 …<description>The Error in transaction bit is set whenever an error is detected. For an IN transact…
28624 … error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
28630 …description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT.…
28638 <description>Non-control endpoint count register</description>
28647 …description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bi…
28653 …description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if C…
28659 <description>No ACK'd transactions since bit was last cleared.</description>
28664 <description>Indicates a transaction ended with an ACK.</description>
28671 …description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set…
28679 <description>Non-control endpoint count register</description>
28688 …description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register…
28696 <description>Non-control endpoint's control Register</description>
28705 …description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the …
28711 <description>Ignore all USB traffic to this endpoint</description>
28716 <description>SETUP: Accept
28718 OUT: NAK</description>
28723 <description>SETUP: Accept
28725 OUT: ACK 0B tokens, NAK others</description>
28730 <description>SETUP: Accept
28732 OUT: STALL</description>
28737 <description>SETUP: Ignore
28739 OUT: Accept Isochronous OUT token</description>
28744 <description>SETUP: Accept
28746 OUT: Stall</description>
28751 <description>SETUP: Ignore
28753 OUT: Ignore</description>
28758 <description>SETUP: Ignore
28760 OUT: NAK</description>
28765 <description>SETUP: Ignore
28768 Change to MODE=8 after one succesfull OUT token.</description>
28773 <description>SETUP: Accept
28775 OUT: Accept data</description>
28780 <description>SETUP: Ignore
28782 OUT: Ignore</description>
28787 <description>SETUP: Ignore
28789 OUT: Ignore</description>
28794 <description>SETUP: Accept
28796 OUT: ACK 0B tokens, NAK others</description>
28803 …description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the regi…
28809 <description>No ACK'd transactions since bit was last cleared.</description>
28814 <description>Indicates a transaction ended with an ACK.</description>
28821 …<description>When set this bit causes an endpoint interrupt to be generated even when a transfer c…
28827 …<description>The Error in transaction bit is set whenever an error is detected. For an IN transact…
28828 … error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
28834 …description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT.…
28842 <description>Non-control endpoint count register</description>
28851 …description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bi…
28857 …description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if C…
28863 <description>No ACK'd transactions since bit was last cleared.</description>
28868 <description>Indicates a transaction ended with an ACK.</description>
28875 …description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set…
28883 <description>Non-control endpoint count register</description>
28892 …description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register…
28900 <description>Non-control endpoint's control Register</description>
28909 …description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the …
28915 <description>Ignore all USB traffic to this endpoint</description>
28920 <description>SETUP: Accept
28922 OUT: NAK</description>
28927 <description>SETUP: Accept
28929 OUT: ACK 0B tokens, NAK others</description>
28934 <description>SETUP: Accept
28936 OUT: STALL</description>
28941 <description>SETUP: Ignore
28943 OUT: Accept Isochronous OUT token</description>
28948 <description>SETUP: Accept
28950 OUT: Stall</description>
28955 <description>SETUP: Ignore
28957 OUT: Ignore</description>
28962 <description>SETUP: Ignore
28964 OUT: NAK</description>
28969 <description>SETUP: Ignore
28972 Change to MODE=8 after one succesfull OUT token.</description>
28977 <description>SETUP: Accept
28979 OUT: Accept data</description>
28984 <description>SETUP: Ignore
28986 OUT: Ignore</description>
28991 <description>SETUP: Ignore
28993 OUT: Ignore</description>
28998 <description>SETUP: Accept
29000 OUT: ACK 0B tokens, NAK others</description>
29007 …description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the regi…
29013 <description>No ACK'd transactions since bit was last cleared.</description>
29018 <description>Indicates a transaction ended with an ACK.</description>
29025 …<description>When set this bit causes an endpoint interrupt to be generated even when a transfer c…
29031 …<description>The Error in transaction bit is set whenever an error is detected. For an IN transact…
29032 … error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
29038 …description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT.…
29046 <description>Non-control endpoint count register</description>
29055 …description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bi…
29061 …description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if C…
29067 <description>No ACK'd transactions since bit was last cleared.</description>
29072 <description>Indicates a transaction ended with an ACK.</description>
29079 …description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set…
29087 <description>Non-control endpoint count register</description>
29096 …description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register…
29104 <description>Non-control endpoint's control Register</description>
29113 …description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the …
29119 <description>Ignore all USB traffic to this endpoint</description>
29124 <description>SETUP: Accept
29126 OUT: NAK</description>
29131 <description>SETUP: Accept
29133 OUT: ACK 0B tokens, NAK others</description>
29138 <description>SETUP: Accept
29140 OUT: STALL</description>
29145 <description>SETUP: Ignore
29147 OUT: Accept Isochronous OUT token</description>
29152 <description>SETUP: Accept
29154 OUT: Stall</description>
29159 <description>SETUP: Ignore
29161 OUT: Ignore</description>
29166 <description>SETUP: Ignore
29168 OUT: NAK</description>
29173 <description>SETUP: Ignore
29176 Change to MODE=8 after one succesfull OUT token.</description>
29181 <description>SETUP: Accept
29183 OUT: Accept data</description>
29188 <description>SETUP: Ignore
29190 OUT: Ignore</description>
29195 <description>SETUP: Ignore
29197 OUT: Ignore</description>
29202 <description>SETUP: Accept
29204 OUT: ACK 0B tokens, NAK others</description>
29211 …description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the regi…
29217 <description>No ACK'd transactions since bit was last cleared.</description>
29222 <description>Indicates a transaction ended with an ACK.</description>
29229 …<description>When set this bit causes an endpoint interrupt to be generated even when a transfer c…
29235 …<description>The Error in transaction bit is set whenever an error is detected. For an IN transact…
29236 … error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
29242 …description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT.…
29250 <description>Endpoint Configuration Register *1</description>
29259 … <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
29265 …<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to …
29271 …<description>Configuration Setting to prevent CRC bytes from being written to memory and being rea…
29277 …<description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for t…
29282 …<description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generate…
29289 …<description>Configuration Setting to Reset the RA and WA Pointers to their start values at the En…
29295 … <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
29300 …<description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</descript…
29309 <description>Endpoint Interrupt Enable Register *1</description>
29318 <description>IN Endpoint Local Buffer Full Enable</description>
29324 <description>Endpoint DMA Grant Enable</description>
29330 <description>Endpoint Buffer Overflow Enable</description>
29336 <description>Endpoint Buffer Underflow Enable</description>
29342 <description>Endpoint Error in Transaction Interrupt Enable</description>
29348 <description>Endpoint DMA Terminated Enable</description>
29356 <description>Endpoint Interrupt Enable Register *1</description>
29365 <description>IN Endpoint Local Buffer Full Interrupt</description>
29371 <description>Endpoint DMA Grant Interrupt</description>
29377 <description>Endpoint Buffer Overflow Interrupt</description>
29383 <description>Endpoint Buffer Underflow Interrupt</description>
29389 <description>Endpoint DMA Terminated Interrupt</description>
29397 <description>Endpoint Write Address value *1, *2</description>
29406 <description>Write Address for EP</description>
29414 <description>Endpoint Write Address value *1, *2</description>
29423 <description>Write Address for EP</description>
29431 <description>Endpoint Read Address value *1, *2</description>
29440 <description>Read Address for EP</description>
29448 <description>Endpoint Read Address value *1, *2</description>
29457 <description>Read Address for EP</description>
29465 <description>Endpoint Data Register</description>
29474 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
29482 <description>Dedicated Endpoint Buffer Size Register *1</description>
29491 <description>Buffer size for IN Endpoints.</description>
29497 <description>Buffer size for OUT Endpoints.</description>
29505 <description>Endpoint Active Indication Register *1</description>
29514 <description>Indicates that Endpoint is currently active.</description>
29520 <description>Indicates that Endpoint is currently active.</description>
29526 <description>Indicates that Endpoint is currently active.</description>
29532 <description>Indicates that Endpoint is currently active.</description>
29538 <description>Indicates that Endpoint is currently active.</description>
29544 <description>Indicates that Endpoint is currently active.</description>
29550 <description>Indicates that Endpoint is currently active.</description>
29556 <description>Indicates that Endpoint is currently active.</description>
29564 <description>Endpoint Type (IN/OUT) Indication *1</description>
29573 <description>Endpoint Type Indication.</description>
29579 <description>IN outpoint</description>
29584 <description>OUT outpoint</description>
29591 <description>Endpoint Type Indication.</description>
29597 <description>IN outpoint</description>
29602 <description>OUT outpoint</description>
29609 <description>Endpoint Type Indication.</description>
29615 <description>IN outpoint</description>
29620 <description>OUT outpoint</description>
29627 <description>Endpoint Type Indication.</description>
29633 <description>IN outpoint</description>
29638 <description>OUT outpoint</description>
29645 <description>Endpoint Type Indication.</description>
29651 <description>IN outpoint</description>
29656 <description>OUT outpoint</description>
29663 <description>Endpoint Type Indication.</description>
29669 <description>IN outpoint</description>
29674 <description>OUT outpoint</description>
29681 <description>Endpoint Type Indication.</description>
29687 <description>IN outpoint</description>
29692 <description>OUT outpoint</description>
29699 <description>Endpoint Type Indication.</description>
29705 <description>IN outpoint</description>
29710 <description>OUT outpoint</description>
29719 <description>Endpoint Configuration Register *1</description>
29728 … <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
29734 …<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to …
29740 …<description>Configuration Setting to prevent CRC bytes from being written to memory and being rea…
29746 …<description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for t…
29751 …<description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generate…
29758 …<description>Configuration Setting to Reset the RA and WA Pointers to their start values at the En…
29764 … <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
29769 …<description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</descript…
29778 <description>Endpoint Interrupt Enable Register *1</description>
29787 <description>IN Endpoint Local Buffer Full Enable</description>
29793 <description>Endpoint DMA Grant Enable</description>
29799 <description>Endpoint Buffer Overflow Enable</description>
29805 <description>Endpoint Buffer Underflow Enable</description>
29811 <description>Endpoint Error in Transaction Interrupt Enable</description>
29817 <description>Endpoint DMA Terminated Enable</description>
29825 <description>Endpoint Interrupt Enable Register *1</description>
29834 <description>IN Endpoint Local Buffer Full Interrupt</description>
29840 <description>Endpoint DMA Grant Interrupt</description>
29846 <description>Endpoint Buffer Overflow Interrupt</description>
29852 <description>Endpoint Buffer Underflow Interrupt</description>
29858 <description>Endpoint DMA Terminated Interrupt</description>
29866 <description>Endpoint Write Address value *1, *2</description>
29875 <description>Write Address for EP</description>
29883 <description>Endpoint Write Address value *1, *2</description>
29892 <description>Write Address for EP</description>
29900 <description>Endpoint Read Address value *1, *2</description>
29909 <description>Read Address for EP</description>
29917 <description>Endpoint Read Address value *1, *2</description>
29926 <description>Read Address for EP</description>
29934 <description>Endpoint Data Register</description>
29943 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
29951 <description>Arbiter Configuration Register *1</description>
29960 …<description>Enables Auto Memory Configuration. Manual memory configuration by default.</descript…
29966 <description>DMA Access Configuration.</description>
29972 <description>No DMA</description>
29977 <description>Manual DMA</description>
29982 <description>Auto DMA</description>
29989 …<description>Register Configuration Complete Indication. Posedge is detected on this bit. Hence a …
29997 <description>USB Block Clock Enable Register</description>
30006 <description>Clock Enable for Core Logic clocked by AHB bus clock</description>
30014 <description>Arbiter Interrupt Enable *1</description>
30023 <description>Enables interrupt for EP1</description>
30029 <description>Enables interrupt for EP2</description>
30035 <description>Enables interrupt for EP3</description>
30041 <description>Enables interrupt for EP4</description>
30047 <description>Enables interrupt for EP5</description>
30053 <description>Enables interrupt for EP6</description>
30059 <description>Enables interrupt for EP7</description>
30065 <description>Enables interrupt for EP8</description>
30073 <description>Arbiter Interrupt Status *1</description>
30082 <description>Interrupt status for EP1</description>
30088 <description>Interrupt status for EP2</description>
30094 <description>Interrupt status for EP3</description>
30100 <description>Interrupt status for EP4</description>
30106 <description>Interrupt status for EP5</description>
30112 <description>Interrupt status for EP6</description>
30118 <description>Interrupt status for EP7</description>
30124 <description>Interrupt status for EP8</description>
30132 <description>Endpoint Configuration Register *1</description>
30141 … <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
30147 …<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to …
30153 …<description>Configuration Setting to prevent CRC bytes from being written to memory and being rea…
30159 …<description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for t…
30164 …<description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generate…
30171 …<description>Configuration Setting to Reset the RA and WA Pointers to their start values at the En…
30177 … <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
30182 …<description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</descript…
30191 <description>Endpoint Interrupt Enable Register *1</description>
30200 <description>IN Endpoint Local Buffer Full Enable</description>
30206 <description>Endpoint DMA Grant Enable</description>
30212 <description>Endpoint Buffer Overflow Enable</description>
30218 <description>Endpoint Buffer Underflow Enable</description>
30224 <description>Endpoint Error in Transaction Interrupt Enable</description>
30230 <description>Endpoint DMA Terminated Enable</description>
30238 <description>Endpoint Interrupt Enable Register *1</description>
30247 <description>IN Endpoint Local Buffer Full Interrupt</description>
30253 <description>Endpoint DMA Grant Interrupt</description>
30259 <description>Endpoint Buffer Overflow Interrupt</description>
30265 <description>Endpoint Buffer Underflow Interrupt</description>
30271 <description>Endpoint DMA Terminated Interrupt</description>
30279 <description>Endpoint Write Address value *1, *2</description>
30288 <description>Write Address for EP</description>
30296 <description>Endpoint Write Address value *1, *2</description>
30305 <description>Write Address for EP</description>
30313 <description>Endpoint Read Address value *1, *2</description>
30322 <description>Read Address for EP</description>
30330 <description>Endpoint Read Address value *1, *2</description>
30339 <description>Read Address for EP</description>
30347 <description>Endpoint Data Register</description>
30356 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
30364 <description>Common Area Write Address *1</description>
30373 <description>Write Address for Common Area</description>
30381 <description>Endpoint Read Address value *1</description>
30390 <description>Write Address for Common Area</description>
30398 <description>Endpoint Configuration Register *1</description>
30407 … <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
30413 …<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to …
30419 …<description>Configuration Setting to prevent CRC bytes from being written to memory and being rea…
30425 …<description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for t…
30430 …<description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generate…
30437 …<description>Configuration Setting to Reset the RA and WA Pointers to their start values at the En…
30443 … <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
30448 …<description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</descript…
30457 <description>Endpoint Interrupt Enable Register *1</description>
30466 <description>IN Endpoint Local Buffer Full Enable</description>
30472 <description>Endpoint DMA Grant Enable</description>
30478 <description>Endpoint Buffer Overflow Enable</description>
30484 <description>Endpoint Buffer Underflow Enable</description>
30490 <description>Endpoint Error in Transaction Interrupt Enable</description>
30496 <description>Endpoint DMA Terminated Enable</description>
30504 <description>Endpoint Interrupt Enable Register *1</description>
30513 <description>IN Endpoint Local Buffer Full Interrupt</description>
30519 <description>Endpoint DMA Grant Interrupt</description>
30525 <description>Endpoint Buffer Overflow Interrupt</description>
30531 <description>Endpoint Buffer Underflow Interrupt</description>
30537 <description>Endpoint DMA Terminated Interrupt</description>
30545 <description>Endpoint Write Address value *1, *2</description>
30554 <description>Write Address for EP</description>
30562 <description>Endpoint Write Address value *1, *2</description>
30571 <description>Write Address for EP</description>
30579 <description>Endpoint Read Address value *1, *2</description>
30588 <description>Read Address for EP</description>
30596 <description>Endpoint Read Address value *1, *2</description>
30605 <description>Read Address for EP</description>
30613 <description>Endpoint Data Register</description>
30622 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
30630 <description>DMA Burst / Threshold Configuration</description>
30639 <description>DMA Threshold count</description>
30647 <description>DMA Burst / Threshold Configuration</description>
30656 <description>DMA Threshold count</description>
30664 <description>Endpoint Configuration Register *1</description>
30673 … <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
30679 …<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to …
30685 …<description>Configuration Setting to prevent CRC bytes from being written to memory and being rea…
30691 …<description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for t…
30696 …<description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generate…
30703 …<description>Configuration Setting to Reset the RA and WA Pointers to their start values at the En…
30709 … <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
30714 …<description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</descript…
30723 <description>Endpoint Interrupt Enable Register *1</description>
30732 <description>IN Endpoint Local Buffer Full Enable</description>
30738 <description>Endpoint DMA Grant Enable</description>
30744 <description>Endpoint Buffer Overflow Enable</description>
30750 <description>Endpoint Buffer Underflow Enable</description>
30756 <description>Endpoint Error in Transaction Interrupt Enable</description>
30762 <description>Endpoint DMA Terminated Enable</description>
30770 <description>Endpoint Interrupt Enable Register *1</description>
30779 <description>IN Endpoint Local Buffer Full Interrupt</description>
30785 <description>Endpoint DMA Grant Interrupt</description>
30791 <description>Endpoint Buffer Overflow Interrupt</description>
30797 <description>Endpoint Buffer Underflow Interrupt</description>
30803 <description>Endpoint DMA Terminated Interrupt</description>
30811 <description>Endpoint Write Address value *1, *2</description>
30820 <description>Write Address for EP</description>
30828 <description>Endpoint Write Address value *1, *2</description>
30837 <description>Write Address for EP</description>
30845 <description>Endpoint Read Address value *1, *2</description>
30854 <description>Read Address for EP</description>
30862 <description>Endpoint Read Address value *1, *2</description>
30871 <description>Read Address for EP</description>
30879 <description>Endpoint Data Register</description>
30888 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
30896 <description>Bus Reset Count Register</description>
30905 <description>Bus Reset Count Length</description>
30913 <description>Endpoint Configuration Register *1</description>
30922 … <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
30928 …<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to …
30934 …<description>Configuration Setting to prevent CRC bytes from being written to memory and being rea…
30940 …<description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for t…
30945 …<description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generate…
30952 …<description>Configuration Setting to Reset the RA and WA Pointers to their start values at the En…
30958 … <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
30963 …<description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</descript…
30972 <description>Endpoint Interrupt Enable Register *1</description>
30981 <description>IN Endpoint Local Buffer Full Enable</description>
30987 <description>Endpoint DMA Grant Enable</description>
30993 <description>Endpoint Buffer Overflow Enable</description>
30999 <description>Endpoint Buffer Underflow Enable</description>
31005 <description>Endpoint Error in Transaction Interrupt Enable</description>
31011 <description>Endpoint DMA Terminated Enable</description>
31019 <description>Endpoint Interrupt Enable Register *1</description>
31028 <description>IN Endpoint Local Buffer Full Interrupt</description>
31034 <description>Endpoint DMA Grant Interrupt</description>
31040 <description>Endpoint Buffer Overflow Interrupt</description>
31046 <description>Endpoint Buffer Underflow Interrupt</description>
31052 <description>Endpoint DMA Terminated Interrupt</description>
31060 <description>Endpoint Write Address value *1, *2</description>
31069 <description>Write Address for EP</description>
31077 <description>Endpoint Write Address value *1, *2</description>
31086 <description>Write Address for EP</description>
31094 <description>Endpoint Read Address value *1, *2</description>
31103 <description>Read Address for EP</description>
31111 <description>Endpoint Read Address value *1, *2</description>
31120 <description>Read Address for EP</description>
31128 <description>Endpoint Data Register</description>
31137 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
31145 <description>Endpoint Configuration Register *1</description>
31154 … <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
31160 …<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to …
31166 …<description>Configuration Setting to prevent CRC bytes from being written to memory and being rea…
31172 …<description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for t…
31177 …<description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generate…
31184 …<description>Configuration Setting to Reset the RA and WA Pointers to their start values at the En…
31190 … <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
31195 …<description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</descript…
31204 <description>Endpoint Interrupt Enable Register *1</description>
31213 <description>IN Endpoint Local Buffer Full Enable</description>
31219 <description>Endpoint DMA Grant Enable</description>
31225 <description>Endpoint Buffer Overflow Enable</description>
31231 <description>Endpoint Buffer Underflow Enable</description>
31237 <description>Endpoint Error in Transaction Interrupt Enable</description>
31243 <description>Endpoint DMA Terminated Enable</description>
31251 <description>Endpoint Interrupt Enable Register *1</description>
31260 <description>IN Endpoint Local Buffer Full Interrupt</description>
31266 <description>Endpoint DMA Grant Interrupt</description>
31272 <description>Endpoint Buffer Overflow Interrupt</description>
31278 <description>Endpoint Buffer Underflow Interrupt</description>
31284 <description>Endpoint DMA Terminated Interrupt</description>
31292 <description>Endpoint Write Address value *1, *2</description>
31301 <description>Write Address for EP</description>
31309 <description>Endpoint Write Address value *1, *2</description>
31318 <description>Write Address for EP</description>
31326 <description>Endpoint Read Address value *1, *2</description>
31335 <description>Read Address for EP</description>
31343 <description>Endpoint Read Address value *1, *2</description>
31352 <description>Read Address for EP</description>
31360 <description>Endpoint Data Register</description>
31369 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
31377 <description>Endpoint Configuration Register *1</description>
31386 … <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
31392 …<description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to …
31398 …<description>Configuration Setting to prevent CRC bytes from being written to memory and being rea…
31404 …<description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for t…
31409 …<description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generate…
31416 …<description>Configuration Setting to Reset the RA and WA Pointers to their start values at the En…
31422 … <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
31427 …<description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</descript…
31436 <description>Endpoint Interrupt Enable Register *1</description>
31445 <description>IN Endpoint Local Buffer Full Enable</description>
31451 <description>Endpoint DMA Grant Enable</description>
31457 <description>Endpoint Buffer Overflow Enable</description>
31463 <description>Endpoint Buffer Underflow Enable</description>
31469 <description>Endpoint Error in Transaction Interrupt Enable</description>
31475 <description>Endpoint DMA Terminated Enable</description>
31483 <description>Endpoint Interrupt Enable Register *1</description>
31492 <description>IN Endpoint Local Buffer Full Interrupt</description>
31498 <description>Endpoint DMA Grant Interrupt</description>
31504 <description>Endpoint Buffer Overflow Interrupt</description>
31510 <description>Endpoint Buffer Underflow Interrupt</description>
31516 <description>Endpoint DMA Terminated Interrupt</description>
31524 <description>Endpoint Write Address value *1, *2</description>
31533 <description>Write Address for EP</description>
31541 <description>Endpoint Write Address value *1, *2</description>
31550 <description>Write Address for EP</description>
31558 <description>Endpoint Read Address value *1, *2</description>
31567 <description>Read Address for EP</description>
31575 <description>Endpoint Read Address value *1, *2</description>
31584 <description>Read Address for EP</description>
31592 <description>Endpoint Data Register</description>
31601 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
31611 <description>DATA</description>
31620 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
31628 <description>Start Of Frame Register</description>
31637 <description>The frame number (11b)</description>
31645 <description>Oscillator lock data register</description>
31654 … <description>These bits return the oscillator locking circuits adder output.</description>
31662 <description>Endpoint Write Address value *3</description>
31671 <description>Write Address for EP</description>
31679 <description>Endpoint Read Address value *3</description>
31688 <description>Read Address for EP</description>
31696 <description>Endpoint Data Register</description>
31705 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
31713 <description>Endpoint Write Address value *3</description>
31722 <description>Write Address for EP</description>
31730 <description>Endpoint Read Address value *3</description>
31739 <description>Read Address for EP</description>
31747 <description>Endpoint Data Register</description>
31756 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
31764 <description>Endpoint Write Address value *3</description>
31773 <description>Write Address for EP</description>
31781 <description>Endpoint Read Address value *3</description>
31790 <description>Read Address for EP</description>
31798 <description>Endpoint Data Register</description>
31807 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
31815 <description>Common Area Write Address</description>
31824 <description>Write Address for Common Area</description>
31832 <description>Endpoint Write Address value *3</description>
31841 <description>Write Address for EP</description>
31849 <description>Endpoint Read Address value *3</description>
31858 <description>Read Address for EP</description>
31866 <description>Endpoint Data Register</description>
31875 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
31883 <description>DMA Burst / Threshold Configuration</description>
31892 <description>DMA Threshold count</description>
31900 <description>Endpoint Write Address value *3</description>
31909 <description>Write Address for EP</description>
31917 <description>Endpoint Read Address value *3</description>
31926 <description>Read Address for EP</description>
31934 <description>Endpoint Data Register</description>
31943 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
31951 <description>Endpoint Write Address value *3</description>
31960 <description>Write Address for EP</description>
31968 <description>Endpoint Read Address value *3</description>
31977 <description>Read Address for EP</description>
31985 <description>Endpoint Data Register</description>
31994 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
32002 <description>Endpoint Write Address value *3</description>
32011 <description>Write Address for EP</description>
32019 <description>Endpoint Read Address value *3</description>
32028 <description>Read Address for EP</description>
32036 <description>Endpoint Data Register</description>
32045 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
32053 <description>Endpoint Write Address value *3</description>
32062 <description>Write Address for EP</description>
32070 <description>Endpoint Read Address value *3</description>
32079 <description>Read Address for EP</description>
32087 <description>Endpoint Data Register</description>
32096 …<description>Data Register for EP ; This register is linked to the memory, hence reset value is un…
32105 <description>USB Device LPM and PHY Test</description>
32109 <description>Power Control Register</description>
32118 …<description>Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before enteri…
32120 …his bit is invalid if the HOST bit of the Host Control 0 Register (HOST_CTL0) is '1'.</description>
32126 <description>Enables the pull up on the DP.
32128 '1' : Enable.</description>
32134 … <description>Select the resister value if POWER_CTL.DP_EN='1'. This bit is valid in GPIO.
32136 '1' : The resister value is from 1425 to 3090Ohmpull up on the DP</description>
32142 <description>Enables the ~15k pull down on the DP.</description>
32148 …<description>Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disa…
32150 '1' : Enable.</description>
32156 … <description>Select the resister value if POWER_CTL.DM_EN='1'. This bit is valid in GPIO.
32158 '1' : The resister value is from 1425 to 3090Ohmpull up on the DM</description>
32164 <description>Enables the ~15k pull down on the DP.</description>
32170 <description>Enables the single ended receiver on D+.</description>
32176 <description>Enables the signle ended receiver on D-.</description>
32184 <description>USB IO Control Register</description>
32193 …description>The GPIO Drive Mode for DP IO pad. This field only applies if USBIO_CR1.IOMODE =1. Dat…
32199 <description>Mode 0: Output buffer off (high Z). Input buffer off.</description>
32204 <description>Mode 1: Output buffer off (high Z). Input buffer on.
32206 Other values, not supported.</description>
32213 <description>The GPIO Drive Mode for DM IO pad.</description>
32221 <description>Flow Control Register</description>
32230 <description>End Point 1 error response
32232 …s then cause a CRC error, if this is an OUT EP and an overflow occurs then send a NAK</description>
32238 <description>End Point 2 error response</description>
32244 <description>End Point 3 error response</description>
32250 <description>End Point 4 error response</description>
32256 <description>End Point 5 error response</description>
32262 <description>End Point 6 error response</description>
32268 <description>End Point 7 error response</description>
32274 <description>End Point 8 error response</description>
32282 <description>LPM Control Register</description>
32291 <description>LPM enable
32295 …NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below</description>
32301 …<description>LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power reques…
32303 …token will get an ACK response and the device will go to the requested low power mode</description>
32309 …<description>Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the d…
32311 1: a LPM token will get a NYET response</description>
32317 …description>Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not…
32325 <description>LPM Status register</description>
32334 <description>Best Effort Service Latency
32335 …match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor.</description>
32341 <description>0: Device is prohibited from initiating a remote wake
32342 1: Device is allow to wake the host</description>
32350 <description>USB SOF, BUS RESET and EP0 Interrupt Status</description>
32359 <description>Interrupt status for USB SOF</description>
32365 <description>Interrupt status for BUS RESET</description>
32371 <description>Interrupt status for EP0</description>
32377 … <description>Interrupt status for LPM (Link Power Management, L1 entry)</description>
32383 <description>Interrupt status for Resume</description>
32391 <description>USB SOF, BUS RESET and EP0 Interrupt Set</description>
32400 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32406 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32412 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32418 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32424 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32432 <description>USB SOF, BUS RESET and EP0 Interrupt Mask</description>
32441 …<description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
32447 …<description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
32453 …<description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
32459 …<description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
32465 …<description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
32473 <description>USB SOF, BUS RESET and EP0 Interrupt Masked</description>
32482 <description>Logical and of corresponding request and mask bits.</description>
32488 <description>Logical and of corresponding request and mask bits.</description>
32494 <description>Logical and of corresponding request and mask bits.</description>
32500 <description>Logical and of corresponding request and mask bits.</description>
32506 <description>Logical and of corresponding request and mask bits.</description>
32514 <description>Select interrupt level for each interrupt source</description>
32523 <description>USB SOF Interrupt level select</description>
32529 <description>High priority interrupt</description>
32534 <description>Medium priority interrupt</description>
32539 <description>Low priority interrupt</description>
32544 <description>illegal</description>
32551 <description>BUS RESET Interrupt level select</description>
32557 <description>EP0 Interrupt level select</description>
32563 <description>LPM Interrupt level select</description>
32569 <description>Resume Interrupt level select</description>
32575 <description>Arbiter Endpoint Interrupt level select</description>
32581 <description>EP1 Interrupt level select</description>
32587 <description>EP2 Interrupt level select</description>
32593 <description>EP3 Interrupt level select</description>
32599 <description>EP4 Interrupt level select</description>
32605 <description>EP5 Interrupt level select</description>
32611 <description>EP6 Interrupt level select</description>
32617 <description>EP7 Interrupt level select</description>
32623 <description>EP8 Interrupt level select</description>
32631 <description>High priority interrupt Cause register</description>
32640 <description>USB SOF Interrupt</description>
32646 <description>BUS RESET Interrupt</description>
32652 <description>EP0 Interrupt</description>
32658 <description>LPM Interrupt</description>
32664 <description>Resume Interrupt</description>
32670 <description>Arbiter Endpoint Interrupt</description>
32676 <description>EP1 Interrupt</description>
32682 <description>EP2 Interrupt</description>
32688 <description>EP3 Interrupt</description>
32694 <description>EP4 Interrupt</description>
32700 <description>EP5 Interrupt</description>
32706 <description>EP6 Interrupt</description>
32712 <description>EP7 Interrupt</description>
32718 <description>EP8 Interrupt</description>
32726 <description>Medium priority interrupt Cause register</description>
32735 <description>USB SOF Interrupt</description>
32741 <description>BUS RESET Interrupt</description>
32747 <description>EP0 Interrupt</description>
32753 <description>LPM Interrupt</description>
32759 <description>Resume Interrupt</description>
32765 <description>Arbiter Endpoint Interrupt</description>
32771 <description>EP1 Interrupt</description>
32777 <description>EP2 Interrupt</description>
32783 <description>EP3 Interrupt</description>
32789 <description>EP4 Interrupt</description>
32795 <description>EP5 Interrupt</description>
32801 <description>EP6 Interrupt</description>
32807 <description>EP7 Interrupt</description>
32813 <description>EP8 Interrupt</description>
32821 <description>Low priority interrupt Cause register</description>
32830 <description>USB SOF Interrupt</description>
32836 <description>BUS RESET Interrupt</description>
32842 <description>EP0 Interrupt</description>
32848 <description>LPM Interrupt</description>
32854 <description>Resume Interrupt</description>
32860 <description>Arbiter Endpoint Interrupt</description>
32866 <description>EP1 Interrupt</description>
32872 <description>EP2 Interrupt</description>
32878 <description>EP3 Interrupt</description>
32884 <description>EP4 Interrupt</description>
32890 <description>EP5 Interrupt</description>
32896 <description>EP6 Interrupt</description>
32902 <description>EP7 Interrupt</description>
32908 <description>EP8 Interrupt</description>
32916 <description>DFT control</description>
32925 <description>DDFT output select signal</description>
32931 <description>Nothing connected, output 0</description>
32936 <description>Single Ended output of DP</description>
32941 <description>Single Ended output of DM</description>
32946 <description>Output Enable</description>
32951 <description>Differential Receiver output</description>
32956 <description>GPIO output of DP</description>
32961 <description>GPIO output of DM</description>
32968 <description>DDFT input select signal</description>
32974 <description>Nothing connected, output 0</description>
32979 <description>GPIO input of DP</description>
32984 <description>GPIO input of DM</description>
32994 <description>USB Host Controller</description>
32998 <description>Host Control 0 Register.</description>
33007 <description>This bit selects an operating mode of this IP.
33016 * The SUSP bit of the Host Status Register (HOST_STATUS) is set to '0'.</description>
33022 <description>This bit enables the operation of this IP.
33026 - This bit doesn't affect the USB Device.</description>
33034 <description>Host Control 1 Register.</description>
33043 <description>This bit selects the operating clock of USB Host.
33048 - This bit must always be set to '1' in the USB Device mode.</description>
33054 …<description>This bit stops the clock for the USB Host operating unit. When this bit is '1', power…
33059 …zed if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'.</description>
33065 <description>This bit resets the USB Host.
33070 …er (HOST_EP1_CTL) and Host Endpoint 2 Control Register (HOST_EP2_CTL) are set to '1'.</description>
33078 <description>Host Control 2 Register.</description>
33087 …<description>If this bit is set to '1', the target token is retried if a NAK or error* occurs. Ret…
33092 …ialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
33098 …<description>When this bit is set to '1', if the target token is written to the Host Token Endpoin…
33100 '1' : Cancels a token.</description>
33106 …<description>If this bit is set to '1', the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1'…
33111 …t flag (INTR_USBHOST.SOFIRQ) is not set to '1' regardless of the setting of this bit.</description>
33117 …<description>This bit is used to specify the keep-alive function in the low-speed mode. If this bi…
33119 '1' : SE0 output (Keep alive)</description>
33125 <description>N/A</description>
33131 <description>N/A</description>
33137 <description>N/A</description>
33145 <description>Host Error Status Register.</description>
33154 … <description>These flags indicate the status of a handshake packet to be sent or received.
33159 …ault value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
33165 <description>Acknowledge Packet</description>
33170 <description>Non-Acknowledge Packet</description>
33175 <description>Stall Packet</description>
33180 <description>Null Packet</description>
33187 …<description>If this bit is set to '1', it means that a bit stuffing error has been detected. When…
33191 …ault value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
33197 …<description>If this bit is set to '1', it means that the data does not match the TGGL data. When …
33201 …ault value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
33207 …<description>If this bit is set to '1', it means that a CRC error is detected in the USB Host. Whe…
33211 …ault value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
33217 …<description>If this bit is set to '1', it means that no response is returned from the device with…
33221 …ault value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
33227 …<description>When this bit is set to '1', it means that the received data exceeds the specified ma…
33230 …ault value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
33236 …<description>If this bit is set to '1', it means that the SOF token can't be sent in the USB Host …
33240 …ault value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
33248 <description>Host Status Register.</description>
33257 …<description>When this bit is '1', it means that the device is connected. When this bit is '0', it…
33262 …nnected on RST isn't immediate. Read this bit to confirm the transition is complete.</description>
33268 …<description>If this bit is '1', it means that the device is connected in the full-speed mode. Whe…
33273 …nnected on RST isn't immediate. Read this bit to confirm the transition is complete.</description>
33279 …<description>If this bit is set to '1', the USB Host is placed into the suspend state. If this bit…
33288 …he state of the USB bus. To check whether or not the state is updated, read this bit.</description>
33294 …<description>When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN), this bi…
33300 … stop the SOF timer. To check whether or not the SOF timer is stopped, read this bit.</description>
33306 …description>When this bit is set to '1', the USB bus is reset. This bit remains a '1' during USB b…
33312 <description>N/A</description>
33318 …<description>This bit shows that USB Host is being reset internally. If the RST bit of the Host Co…
33324 …(HOST_CTL1) is set to '0' or '1'. Read this bit to confirm the operation is complete.</description>
33330 …<description>This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control…
33335 …t Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete.</description>
33341 …<description>This bit shows whether the device is in USB Host mode. If the HOST bit of the Host Co…
33346 …t Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete.</description>
33354 <description>Host SOF Interrupt Frame Compare Register</description>
33363 …<description>These bits are used to specify the data to be compared with the low-order eight bits …
33367 …default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
33375 <description>Host Retry Timer Setup Register</description>
33384 …<description>These bits are used to specify the retry time in this register. The retry timer is ac…
33385 …ompleted, the retry timer restarts with the value that is set when the timer stopped.</description>
33393 <description>Host Address Register</description>
33402 <description>These bits are used to specify a token address.
33404 …default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
33412 <description>Host EOF Setup Register</description>
33421 …<description>These bits are used to specify the time to disable token sending before transferring …
33427 …default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
33435 <description>Host Frame Setup Register</description>
33444 <description>These bits are used to specify a frame number of SOF.
33448 …Y bit of the Host Status Register (HOST_STATUS) is '1' and a SOF token is in process.</description>
33456 <description>Host Token Endpoint Register</description>
33465 …<description>These bits are used to specify an endpoint to send or receive data to or from the dev…
33467 …default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
33473 …<description>These bits send a token according to the current settings. After operation is complet…
33485 …ed data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'.</description>
33491 <description>Sends no data.</description>
33496 <description>Sends SETUP token.</description>
33501 <description>Sends IN token.</description>
33506 <description>Sends OUT token.</description>
33511 <description>Sends SOF token.</description>
33516 <description>Sends Isochronous IN.</description>
33521 <description>Sends Isochronous OUT.</description>
33526 <description>N/A</description>
33533 …<description>This bit is used to set toggle data. Toggle data is sent depending on the setting of …
33538 …his bit when the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN) is '000'.</description>
33546 <description>Host Endpoint 1 Control Register</description>
33555 …<description>This bit specifies the maximum size transferred by one packet. The configurable range…
33556 …automatic buffer transfer mode (DMAE='1') is used, Endpoint 0,1, or 2 cannot be used,</description>
33562 …<description>When a data transfer request in OUT the direction is transmitted while automatic buff…
33566 …r transfer mode is not set, the NULL bit configuration does not affect communication.</description>
33572 …<description>This bit sets a mode that uses DMA for writing or reading transfer data to/from send/…
33576 …ost EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR).</description>
33582 <description>This bit specifies the transfer direction the Endpoint support.
33586 …nged when INI_ST bit of the Host Endpoint 1 Status Register (HOST_EP1_STATUS) is '1'.</description>
33592 …<description>This bit initializes the send/receive buffer of transfer data. The BFINI bit is also …
33596 …izes the double buffers concurrently and also initializes the EP1DRQ and EP1SPK bits.</description>
33604 <description>Host Endpoint 1 Status Register</description>
33613 …<description>These bits indicate the number of data bytes written to the receive buffer when IN pa…
33616 …e buffer. Therefore, a value read during transfer in the OUT direction has no effect.</description>
33622 <description>This bit shows that there is valid data in the EP1 buffer.
33624 '1' : Valid data in the buffer</description>
33630 …<description>This bit shows that EP1 is initialized. If the init bit of the Host Endpoint 1 Contro…
33634 …gister (HOST_EP1_CTL) is set to '0' or '1'. Read this bit to confirm the transition.</description>
33640 <description>N/A</description>
33648 <description>Host Endpoint 1 Data 1-Byte Register</description>
33657 <description>Data Register for EP1 for 1-byte data</description>
33665 <description>Host Endpoint 1 Data 2-Byte Register</description>
33674 <description>Data Register for EP1 for 2-byte data</description>
33682 <description>Host Endpoint 2 Control Register</description>
33691 …<description>This bit specifies the maximum size transferred by one packet. The configurable range…
33692 …atic buffer transfer mode (DMAE='1') is used, this Endpoint must not set from 0 to 2.</description>
33698 …<description>When a data transfer request in the OUT direction transmitted while packet transfer m…
33702 …r transfer mode is not set, the NULL bit configuration does not affect communication.</description>
33708 …<description>This bit sets a mode that uses DMA for writing or reading transfer data to/from send/…
33712 …ost EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR).</description>
33718 <description>This bit specifies the transfer direction the Endpoint support.
33722 …nged when INI_ST bit of the Host Endpoint 2 Status Register (HOST_EP2_STATUS) is '1'.</description>
33728 …<description>This bit initializes the send/receive buffer of transfer data. The BFINI bit is also …
33732 …izes the double buffers concurrently and also initializes the EP2DRQ and EP2SPK bits.</description>
33740 <description>Host Endpoint 2 Status Register</description>
33749 …<description>These bits indicate the number of data bytes written to the receive buffer when IN pa…
33752 …e buffer. Therefore, a value read during transfer in the OUT direction has no effect.</description>
33758 <description>This bit shows that there is valid data in the EP2 buffer.
33760 '1' : Valid data in the buffer</description>
33766 …<description>This bit shows that EP2 is initialized. If the BFINI bit of the Host Endpoint 2 Contr…
33770 …FINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '0' or '1'.</description>
33776 <description>N/A</description>
33784 <description>Host Endpoint 2 Data 1-Byte Register</description>
33793 <description>Data Register for EP2 for 1-byte data.</description>
33801 <description>Host Endpoint 2 Data 2-Byte Register</description>
33810 <description>Data Register for EP2 for 2 byte data.</description>
33818 <description>Host Interrupt Level 1 Selection Register</description>
33827 … <description>These bits assign SOFIRQ interrupt flag to selected interrupt signals.</description>
33833 <description>High priority interrupt</description>
33838 <description>Medium priority interrupt</description>
33843 <description>Low priority interrupt</description>
33848 <description>N/A</description>
33855 … <description>These bits assign DIRQ interrupt flag to selected interrupt signals.</description>
33861 … <description>These bits assign CNNIRQ interrupt flag to selected interrupt signals.</description>
33867 … <description>These bits assign URIRQ interrupt flag to selected interrupt signals.</description>
33873 … <description>These bits assign URIRQ interrupt flag to selected interrupt signals.</description>
33879 … <description>These bits assign RWKIRQ interrupt flag to selected interrupt signals.</description>
33885 <description>N/A</description>
33891 … <description>These bits assign TCAN interrupt flag to selected interrupt signals.</description>
33899 <description>Host Interrupt Level 2 Selection Register</description>
33908 … <description>These bits assign EP1_DRQ interrupt flag to selected interrupt signals.</description>
33914 <description>High priority interrupt</description>
33919 <description>Medium priority interrupt</description>
33924 <description>Low priority interrupt</description>
33929 <description>N/A</description>
33936 … <description>These bits assign EP1_SPK interrupt flag to selected interrupt signals.</description>
33942 … <description>These bits assign EP2_DRQ interrupt flag to selected interrupt signals.</description>
33948 … <description>These bits assign EP2_SPK interrupt flag to selected interrupt signals.</description>
33956 <description>Interrupt USB Host Cause High Register</description>
33965 <description>SOFIRQ interrupt</description>
33971 <description>DIRQ interrupt</description>
33977 <description>CNNIRQ interrupt</description>
33983 <description>CMPIRQ interrupt</description>
33989 <description>URIRQ interrupt</description>
33995 <description>RWKIRQ interrupt</description>
34001 <description>N/A</description>
34007 <description>TCAN interrupt</description>
34015 <description>Interrupt USB Host Cause Medium Register</description>
34024 <description>SOFIRQ interrupt</description>
34030 <description>DIRQ interrupt</description>
34036 <description>CNNIRQ interrupt</description>
34042 <description>CMPIRQ interrupt</description>
34048 <description>URIRQ interrupt</description>
34054 <description>RWKIRQ interrupt</description>
34060 <description>N/A</description>
34066 <description>TCAN interrupt</description>
34074 <description>Interrupt USB Host Cause Low Register</description>
34083 <description>SOFIRQ interrupt</description>
34089 <description>DIRQ interrupt</description>
34095 <description>CNNIRQ interrupt</description>
34101 <description>CMPIRQ interrupt</description>
34107 <description>URIRQ interrupt</description>
34113 <description>RWKIRQ interrupt</description>
34119 <description>N/A</description>
34125 <description>TCAN interrupt</description>
34133 <description>Interrupt USB Host Endpoint Cause High Register</description>
34142 <description>EP1DRQ interrupt</description>
34148 <description>EP1SPK interrupt</description>
34154 <description>EP2DRQ interrupt</description>
34160 <description>EP2SPK interrupt</description>
34168 <description>Interrupt USB Host Endpoint Cause Medium Register</description>
34177 <description>EP1DRQ interrupt</description>
34183 <description>EP1SPK interrupt</description>
34189 <description>EP2DRQ interrupt</description>
34195 <description>EP2SPK interrupt</description>
34203 <description>Interrupt USB Host Endpoint Cause Low Register</description>
34212 <description>EP1DRQ interrupt</description>
34218 <description>EP1SPK interrupt</description>
34224 <description>EP2DRQ interrupt</description>
34230 <description>EP2SPK interrupt</description>
34238 <description>Interrupt USB Host Register</description>
34247 …<description>If this bit is set to '1', it means that SOF token sending is started. When this bit …
34251 …ault value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
34257 …<description>If this bit is set to '1', it means that a device disconnection is detected. When thi…
34261 …ault value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
34267 …<description>If this bit is set to '1', it means that a device connection is detected. When this b…
34271 …ault value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
34277 …<description>If this bit is set to '1', it means that a token is completed. When this bit is '0', …
34286 …ed data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'.</description>
34292 …<description>If this bit is set to '1', it means that USB bus resetting is ended. When this bit is…
34296 …tial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
34302 …<description>If this bit is set to '1', it means that remote Wake-up is ended. When this bit is '0…
34306 …ault value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
34312 <description>N/A</description>
34318 …<description>If this bit is set to '1', it means that token sending is canceled based on the setti…
34322 …ault value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
34330 <description>Interrupt USB Host Set Register</description>
34339 …description>This bit sets SOFIRQ bit. If this bit is written to '1', SOFIRQ is set to '1'. However…
34345 …description>This bit sets DIRQ bit. If this bit is written to '1', DIRQ is set to '1'. However, if…
34351 …description>This bit sets CNNIRQ bit. If this bit is written to '1', CNNIRQ is set to '1'. However…
34357 …description>This bit sets CMPIRQ bit. If this bit is written to '1', CMPIRQ is set to '1'. However…
34363 …description>This bit sets URIRQ bit. If this bit is written to '1', URIRQ is set to '1'. However, …
34369 …description>This bit sets RWKIRQ bit. If this bit is written to '1', RWKIRQ is set to '1'. However…
34375 <description>N/A</description>
34381 …description>This bit sets TCAN bit. If this bit is written to '1', TCAN is set to '1'. However, if…
34389 <description>Interrupt USB Host Mask Register</description>
34398 <description>This bit masks the interrupt by SOF flag.
34400 '1' : Enables</description>
34406 <description>This bit masks the interrupt by DIRQ flag.
34408 '1' : Enables</description>
34414 <description>This bit masks the interrupt by CNNIRQ flag.
34416 '1' : Enables</description>
34422 <description>This bit masks the interrupt by CMPIRQ flag.
34424 '1' : Enables</description>
34430 <description>This bit masks the interrupt by URIRQ flag.
34432 '1' : Enables</description>
34438 <description>This bit masks the interrupt by RWKIRQ flag.
34440 '1' : Enables</description>
34446 <description>N/A</description>
34452 <description>This bit masks the interrupt by TCAN flag.
34454 '1' : Enables</description>
34462 <description>Interrupt USB Host Masked Register</description>
34471 <description>This bit indicates the interrupt by SOF flag.
34473 '1' : Request the interrupt by SOF</description>
34479 <description>This bit indicates the interrupt by DIRQ flag.
34481 '1' : Request the interrupt by DIRQ</description>
34487 <description>This bit indicates the interrupt by CNNIRQ flag.
34489 '1' : Request the interrupt by CNNIRQ</description>
34495 <description>This bit indicates the interrupt by CMPIRQ flag.
34497 '1' : Request the interrupt by CMPIRQ</description>
34503 <description>This bit indicates the interrupt by URIRQ flag.
34505 '1' : Request the interrupt by URIRQ</description>
34511 <description>This bit indicates the interrupt by RWKIRQ flag.
34513 '1' : Request the interrupt by RWKIRQ</description>
34519 <description>N/A</description>
34525 <description>This bit indicates the interrupt by TCAN flag.
34527 '1' : Request the interrupt by TCAN</description>
34535 <description>Interrupt USB Host Endpoint Register</description>
34544 …<description>This bit indicates that the EP1 packet transfer has normally ended, and processing of…
34548 … is set at the same time. Also while the DRQ bit is not set, '1' must not be written.</description>
34554 …<description>This bit indicates that the data size transferred from the host does not satisfy the …
34558 - The EP1SPK bit is not set during data transfer in the OUT direction.</description>
34564 …<description>This bit indicates that the EP2 packet transfer has normally ended, and processing of…
34568 … is set at the same time. Also while the DRQ bit is not set, '1' must not be written.</description>
34574 …<description>This bit indicates that the data size transferred from the host does not satisfy the …
34578 - The SPK bit is not set during data transfer in the OUT direction.</description>
34586 <description>Interrupt USB Host Endpoint Set Register</description>
34595 …<description>This bit sets EP1DRQ bit. If this bit is written to '1', EP1DRQ is set to '1'. Howeve…
34597 …e Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1DRQ can't be set to '1'.</description>
34603 …<description>This bit sets EP1SPK bit. If this bit is written to '1', EP1SPK is set to '1'. Howeve…
34605 …e Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1SPK can't be set to '1'.</description>
34611 …<description>This bit sets EP2DRQ bit. If this bit is written to '1', EP2DRQ is set to '1'. Howeve…
34613 …e Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2DRQ can't be set to '1'.</description>
34619 …<description>This bit sets EP2SPK bit. If this bit is written to '1', EP2SPK is set to '1'. Howeve…
34621 …e Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2SPK can't be set to '1'.</description>
34629 <description>Interrupt USB Host Endpoint Mask Register</description>
34638 <description>This bit masks the interrupt by EP1DRQ flag.
34640 '1' : Enables</description>
34646 <description>This bit masks the interrupt by EP1SPK flag.
34648 '1' : Enables</description>
34654 <description>This bit masks the interrupt by EP2DRQ flag.
34656 '1' : Enables</description>
34662 <description>This bit masks the interrupt by EP2SPK flag.
34664 '1' : Enables</description>
34672 <description>Interrupt USB Host Endpoint Masked Register</description>
34681 <description>This bit indicates the interrupt by EP1DRQ flag.
34683 '1' : Request the interrupt by EP1DRQ</description>
34689 <description>This bit indicates the interrupt by EP1SPK flag.
34691 '1' : Request the interrupt by EP1SPK</description>
34697 <description>This bit indicates the interrupt by EP2DRQ flag.
34699 '1' : Request the interrupt by EP2DRQ</description>
34705 <description>This bit indicates the interrupt by EP2SPK flag.
34707 '1' : Request the interrupt by EP2SPK</description>
34715 <description>Host DMA Enable Register</description>
34724 <description>This bit enables DMA Request by EP1DRQ.
34726 '1' : Enable</description>
34732 <description>This bit enables DMA Request by EP2DRQ.
34734 '1' : Enable</description>
34742 <description>Host Endpoint 1 Block Register</description>
34751 …<description>Set the total byte number for DMA transfer. If HOST_EP1_RW1_DR or HOST_EP1_RW2_DR is …
34752 - Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP1DRQE='1')</description>
34760 <description>Host Endpoint 2 Block Register</description>
34769 …<description>Set the total byte number for DMA transfer. If HOST_EP2_RW1_DR or HOST_EP2_RW2_DR is …
34770 - Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP2DRQE='1')</description>
34781 <description>Serial Memory Interface</description>
34792 <description>Control</description>
34801 <description>Mode of operation.
34803 ….BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface.</description>
34809 …description>'0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a seq…
34814 …description>1': XIP mode. eXecute-In-Place mode: incoming read and write transfers over the AHB-Li…
34821 …<description>Specifies device interface receiver clock 'clk_if_rx' source. MISO data is captured o…
34827 …is fixed and is 'spi_clk_out' MOSI data is driven on the falling edge of 'clk_if_tx'.</description>
34833 …<description>Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in…
34843 …_out[]' are '1'/inactive, 'spi_data_out[]' are '1' and 'spi_clk_out' is '0'/inactive.</description>
34849 …<description>Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or t…
34851 This field is not used for test controller accesses.</description>
34857 …description>0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polli…
34862 …description>1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructu…
34869 <description>IP enable:
34873 …IP is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur.</description>
34879 <description>N/A</description>
34884 <description>N/A</description>
34893 <description>Status</description>
34902 … <description>Cache, cryptography, XIP, device interface or any other logic busy in the IP:
34908 When BUSY is '0', the mode of operation (XIP_MODE or MMIO_MODE) can be safely changed.</description>
34916 <description>Transmitter command FIFO status</description>
34925 …<description>Number of entries that are used in the TX command FIFO (available in both XIP_MODE an…
34933 <description>Transmitter command FIFO write</description>
34942 … <description>Command data. The higher two bits DATA[19:18] specify the specific command
34964 …the number of dummy cycles (minus 1). In dummy cycles, the data lines are not driven.</description>
34972 <description>Transmitter data FIFO control</description>
34981 …<description>Determines when the TX data FIFO 'tr_tx_req' trigger is activated (trigger activatio…
34982 - Trigger is active when TX_DATA_FIFO_STATUS.USED <= TRIGGER_LEVEL.</description>
34990 <description>Transmitter data FIFO status</description>
34999 …<description>Number of entries that are used in the TX data FIFO (available in both XIP_MODE and M…
35007 <description>Transmitter data FIFO write</description>
35016 <description>TX data (written to TX data FIFO).</description>
35024 <description>Transmitter data FIFO write</description>
35033 <description>TX data (written to TX data FIFO, first byte).</description>
35039 <description>TX data (written to TX data FIFO, second byte).</description>
35047 <description>Transmitter data FIFO write</description>
35056 <description>TX data (written to TX data FIFO, first byte).</description>
35062 <description>TX data (written to TX data FIFO, second byte).</description>
35068 <description>TX data (written to TX data FIFO, third byte).</description>
35074 <description>TX data (written to TX data FIFO, fourth byte).</description>
35082 <description>Receiver data FIFO control</description>
35091 …<description>Determines when RX data FIFO 'tr_rx_req' trigger is activated (trigger activation req…
35092 - Trigger is active when RX_DATA_FIFO_STATUS.USED > TRIGGER_LEVEL.</description>
35100 <description>Receiver data FIFO status</description>
35109 …<description>Number of entries that are used in the RX data FIFO (available in both XIP_MODE and M…
35117 <description>Receiver data FIFO read</description>
35126 <description>RX data (read from RX data FIFO).</description>
35134 <description>Receiver data FIFO read</description>
35143 <description>RX data (read from RX data FIFO, first byte).</description>
35149 <description>RX data (read from RX data FIFO, second byte).</description>
35157 <description>Receiver data FIFO read</description>
35166 <description>RX data (read from RX data FIFO, first byte).</description>
35172 <description>RX data (read from RX data FIFO, second byte).</description>
35178 <description>RX data (read from RX data FIFO, third byte).</description>
35184 <description>RX data (read from RX data FIFO, fourth byte).</description>
35192 <description>Receiver data FIFO silent read</description>
35201 <description>RX data (read from RX data FIFO).</description>
35209 <description>Slow cache control</description>
35218 …<description>Specifies the cache way for which cache information is provided in SLOW_CA_STATUS0/1/…
35224 …<description>Specifies the cache set for which cache information is provided in SLOW_CA_STATUS0/1/…
35230 <description>Prefetch enable:
35234 Prefetching requires the cache to be enabled; i.e. ENABLED is '1'.</description>
35240 <description>Cache enable:
35242 '1': Enabled.</description>
35250 <description>Slow cache command</description>
35259 <description>Cache and prefetch buffer invalidation.
35264 …irmware should invalidate the cache and prefetch buffer only when STATUS.BUSY is '0'.</description>
35272 <description>Fast cache control</description>
35281 <description>See SLOW_CA_CTL.WAY.</description>
35287 <description>See SLOW_CA_CTL.SET_ADDR.</description>
35293 <description>See SLOW_CA_CTL.PREF_EN.</description>
35299 <description>See SLOW_CA_CTL.ENABLED.</description>
35307 <description>Fast cache command</description>
35316 <description>See SLOW_CA_CMD.INV.</description>
35324 <description>Cryptography Command</description>
35333 …<description>SW sets this field to '1' to start a AES-128 forward block cipher operation (on the a…
35337 Note: An operation can only be started in MMIO_MODE.</description>
35345 <description>Cryptography input 0</description>
35354 … <description>Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0].</description>
35362 <description>Cryptography input 1</description>
35371 … <description>Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0].</description>
35379 <description>Cryptography input 2</description>
35388 … <description>Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0].</description>
35396 <description>Cryptography input 3</description>
35405 … <description>Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0].</description>
35413 <description>Cryptography key 0</description>
35422 <description>Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0].</description>
35430 <description>Cryptography key 1</description>
35439 <description>Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0].</description>
35447 <description>Cryptography key 2</description>
35456 <description>Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0].</description>
35464 <description>Cryptography key 3</description>
35473 <description>Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0].</description>
35481 <description>Cryptography output 0</description>
35490 … <description>Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0].</description>
35498 <description>Cryptography output 1</description>
35507 … <description>Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0].</description>
35515 <description>Cryptography output 2</description>
35524 … <description>Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0].</description>
35532 <description>Cryptography output 3</description>
35541 … <description>Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0].</description>
35549 <description>Interrupt register</description>
35558 …<description>Activated in MMIO mode, when a TX data FIFO trigger 'tr_tx_req' is activated.</descri…
35564 …<description>Activated in MMIO mode, when a RX data FIFO trigger 'tr_rx_req' is activated.</descri…
35570 <description>Activated in XIP mode, if:
35574 …uest address is a multiple of 2 and the number of requested Bytes is a multiple of 2.</description>
35580 …description>Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_F…
35586 …description>Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIF…
35592 …description>Activated in MMIO mode, on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FI…
35600 <description>Interrupt set register</description>
35609 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
35615 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
35621 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
35627 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
35633 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
35639 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
35647 <description>Interrupt mask register</description>
35656 … <description>Mask bit for corresponding bit in interrupt request register.</description>
35662 … <description>Mask bit for corresponding bit in interrupt request register.</description>
35668 … <description>Mask bit for corresponding bit in interrupt request register.</description>
35674 … <description>Mask bit for corresponding bit in interrupt request register.</description>
35680 … <description>Mask bit for corresponding bit in interrupt request register.</description>
35686 … <description>Mask bit for corresponding bit in interrupt request register.</description>
35694 <description>Interrupt masked register</description>
35703 <description>Logical and of corresponding request and mask bits.</description>
35709 <description>Logical and of corresponding request and mask bits.</description>
35715 <description>Logical and of corresponding request and mask bits.</description>
35721 <description>Logical and of corresponding request and mask bits.</description>
35727 <description>Logical and of corresponding request and mask bits.</description>
35733 <description>Logical and of corresponding request and mask bits.</description>
35743 <description>Device (only used in XIP mode)</description>
35747 <description>Control</description>
35756 <description>Write enable:
35758 '1': write transfers are allowed to this device.</description>
35764 <description>Cryptography on read/write accesses:
35766 '1': enabled.</description>
35772 …<description>Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to th…
35776 …] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes.</description>
35782 <description>Device enable:
35784 '1': Enabled.</description>
35792 <description>Device region base address</description>
35801 …<description>Specifies the base address of the device region. If the device region is 2^m Bytes, A…
35805 …IP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24].</description>
35813 <description>Device region mask</description>
35822 …<description>Specifies the size of the device region. All '1' bits are used to compare the incomin…
35826 …a transfer request that is not in any device region results in an AHB-Lite bus error.</description>
35834 <description>Address control</description>
35843 <description>Specifies the size of the XIP device address in Bytes:
35848 …address is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.</description>
35854 <description>Specifies if the AHB-Lite bus transfer address is divided by 2 or not:
35858 …f Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.</description>
35866 <description>Read command control</description>
35875 <description>Command byte code.</description>
35881 <description>Width of data transfer:
35885 '3': 8 bits/cycle (octal data transfer).</description>
35891 <description>Presence of command field:
35893 '1': present</description>
35901 <description>Read address control</description>
35910 <description>Width of transfer.</description>
35918 <description>Read mode control</description>
35927 <description>Mode byte code.</description>
35933 <description>Width of transfer.</description>
35939 <description>Presence of mode field:
35941 '1': present</description>
35949 <description>Read dummy control</description>
35958 <description>Number of dummy cycles (minus 1):
35963 Note: this field specifies dummy cycles, not dummy Bytes!</description>
35969 <description>Presence of dummy cycles:
35971 '1': present</description>
35979 <description>Read data control</description>
35988 <description>Width of transfer.</description>
35996 <description>Write command control</description>
36005 <description>Command byte code.</description>
36011 <description>Width of transfer.</description>
36017 <description>Presence of command field:
36019 '1': present</description>
36027 <description>Write address control</description>
36036 <description>Width of transfer.</description>
36044 <description>Write mode control</description>
36053 <description>Mode byte code.</description>
36059 <description>Width of transfer.</description>
36065 <description>Presence of mode field:
36067 '1': present</description>
36075 <description>Write dummy control</description>
36084 <description>Number of dummy cycles (minus 1):
36087 '31': 32 cycles.</description>
36093 <description>Presence of dummy cycles:
36095 '1': present</description>
36103 <description>Write data control</description>
36112 <description>Width of transfer.</description>
36123 <description>Serial Communications Block (SPI/UART/I2C)</description>
36134 <description>Generic control</description>
36143 <description>N/A</description>
36149 …<description>Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C)…
36151 In UART mode this field should be '0'.</description>
36157 …<description>Internally clocked mode ('0') or externally clocked mode ('1') operation. In internal…
36159 In UART mode this field should be '0'.</description>
36165 …<description>Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the ser…
36167 In UART mode this field should be '0'.</description>
36173 <description>Determines the number of bits per FIFO data element:
36175 …IFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 7].</description>
36181 <description>Determines CMD_RESP mode of operation:
36183 '1': CMD_RESP mode enabled (also requires EC_AM_MODE and EC_OP_MODE to be set to '1').</description>
36189 …<description>Determines whether a received matching address is accepted in the RX FIFO ('1') or no…
36193 …ed address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO.</description>
36199 …description>Only used in externally clocked mode. If the externally clocked logic and the MMIO SW …
36205 <description>N/A</description>
36211 <description>Inter-Integrated Circuits (I2C) mode.</description>
36216 <description>Serial Peripheral Interface (SPI) mode.</description>
36221 … <description>Universal Asynchronous Receiver/Transmitter (UART) mode.</description>
36228 …<description>IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as f…
36233 …use re-initialization of the design and associated state is lost (e.g. FIFO content).</description>
36241 <description>Generic status</description>
36250 …description>Indicates whether the externally clocked logic is potentially accessing the EZ memory …
36258 <description>Command/response control</description>
36267 …description>I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode re…
36273 …description>I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode w…
36281 <description>Command/response status</description>
36290 …<description>I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read …
36294 … is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable.</description>
36300 …<description>I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read…
36304 … is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable.</description>
36310 <description>Indicates whether there is an ongoing bus transfer to the IP.
36316 …In case of NO address match, the field is set to '0' after the failing address match.</description>
36322 …<description>Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are relia…
36326 Note that this update lasts one I2C clock cycle, or two SPI clock cycles.</description>
36334 <description>SPI control</description>
36343 …<description>Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in maste…
36347 …parated by slave deselection: independent of the availability of TX FIFO data frames.</description>
36353 <description>Only used in SPI Texas Instruments' submode.
36357 …ulse on the SELECT line that coincides with the transfer of the first data frame bit.</description>
36363 …<description>Indicates the clock phase. This field, together with the CPOL field, indicates when M…
36371 in SPI TI submode, only CPOL=0 CPHA=1 mode is valid.</description>
36377 …<description>Indicates the clock polarity. This field, together with the CPHA field, indicates whe…
36379 - CPOL is '1': SCLK is '1' when not transmitting data.</description>
36385 … <description>Changes the SCLK edge on which MISO is captured. Only used in master mode.
36389 …SCLK from the master to the slave and transmitting MISO from the slave to the master.</description>
36395 <description>Only applicable in master mode.
36397 …ave devices that use SCLK for functional operation other than just SPI functionality.</description>
36403 …<description>Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal…
36408 '1': low/'0' active precede/coincide pulse.</description>
36414 <description>Slave select polarity.</description>
36420 <description>Slave select polarity.</description>
36426 <description>Slave select polarity.</description>
36432 …<description>Local loopback control (does NOT affect the information on the pins). Only used in ma…
36434 …er words, in loopback mode the SPI master receives on MISO what it transmits on MOSI.</description>
36440 <description>N/A</description>
36446 …description>SPI Motorola submode. In master mode, when not transmitting data (SELECT is inactive),…
36451 …description>SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is sta…
36456 …description>SPI National Semiconductors submode. In master mode, when not transmitting data, SCLK …
36463 <description>Selects one of the four incoming/outgoing SPI slave select signals:
36468 The IP should be disabled when changes are made to this field.</description>
36474 …description>Master ('1') or slave ('0') mode. In master mode, transmission will commence on availa…
36482 <description>SPI status</description>
36491 …description>SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For M…
36497 …description>Indicates whether the externally clocked logic is potentially accessing the EZ memory …
36503 …description>SPI current EZ address. Current address pointer. This field is only reliable in intern…
36509 …description>SPI base EZ address. Address as provided by a SPI write transfer. This field is only r…
36517 <description>UART control</description>
36526 …<description>Local loopback control (does NOT affect the information on the pins). When '0', the t…
36528 This allows a SCB UART transmitter to communicate with its receiver counterpart.</description>
36534 <description>N/A</description>
36540 <description>Standard UART submode.</description>
36545 …description>SmartCard (ISO7816) submode. Support for negative acknowledgement (NACK) on the receiv…
36550 …<description>Infrared Data Association (IrDA) submode. Return to Zero modulation scheme.</descript…
36559 <description>UART transmitter control</description>
36568 …description>Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit peri…
36574 …description>Parity bit. When '0', the transmitter generates an even parity. When '1', the transmit…
36580 …description>Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submode…
36586 …<description>When '1', a data frame is retransmitted when a negative acknowledgement is received. …
36594 <description>UART receiver control</description>
36603 …<description>Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit per…
36605 …mount of stop bits, the idle ('1') time between data frames and the data frame value.</description>
36611 …description>Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expe…
36617 …description>Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. …
36623 …description>Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This …
36629 …description>Behavior when a parity check fails. When '0', received data is send to the RX FIFO. Wh…
36635 …description>Behavior when an error is detected in a start or stop period. When '0', received data …
36641 …description>Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL…
36647 …description>Only applicable in standard UART submode. When '1', the receiver performs break detect…
36653 …description>Only applicable in standard UART submode. When '1', the receiver skips start bit detec…
36659 …description>Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a …
36667 <description>UART receiver status</description>
36676 …description>Amount of peripheral clock periods that constitute the transmission of a 0x55 data fra…
36684 <description>UART flow control</description>
36693 …description>Trigger level. When the receiver FIFO has less entries than the amount of this field, …
36699 <description>Polarity of the RTS output signal 'uart_rts_out':
36703 …ts_out' is '1'. This represents an inactive state assuming a low/'0' active polarity.</description>
36709 <description>Polarity of the CTS input signal 'uart_cts_in':
36711 …/'1' active; 'uart_cts_in' is '1' when active and 'uart_cts_in' is '0' when inactive.</description>
36717 <description>Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:
36721 … subjected to signal polarity changes as indicated by RTS_POLARITY and CTS_POLARITY).</description>
36729 <description>I2C control</description>
36738 …<description>Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral cl…
36740 …ing, the IF high time should be >= 5 IP clock cycles and <= 16 IP clock cycles.</description>
36746 …<description>Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral cloc…
36748 …ring, the IF low time should be >= 7 IP clock cycles and <= 16 IP clock cycles.</description>
36754 …<description>When '1', a received data element by the master is immediately ACK'd when the receive…
36760 …description>When '1', a received data element byte the master is immediately NACK'd when the recei…
36766 …description>When '1', a received general call slave address is immediately NACK'd (no ACK or clock…
36772 …description>When '1', a received (matching) slave address is immediately ACK'd when the receiver F…
36778 …description>When '1', a received data element by the slave is immediately ACK'd when the receiver …
36784 …<description>For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or g…
36796 …e internally clocked logic will handle the ongoing transfer as soon as it is enabled.</description>
36802 <description>For internally clocked logic only. Only used when:
36806 - 0: clock stretching is performed (till the receiver FIFO is no longer full).</description>
36812 …description>Local loopback control (does NOT affect the information on the pins). Only applicable …
36818 <description>Slave mode enabled ('1') or not ('0').</description>
36824 …description>Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be e…
36832 <description>I2C status</description>
36841 …<description>I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected …
36845 …master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions).</description>
36851 …description>Indicates whether the externally clocked logic is potentially accessing the EZ memory …
36857 …description>I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is…
36863 …description>I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master…
36869 …description>I2C slave current EZ address. Current address pointer. This field is only reliable in …
36875 …description>I2C slave base EZ address. Address as provided by an I2C write transfer. This field is…
36883 <description>I2C master command</description>
36892 …description>When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is tra…
36898 …description>When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', not…
36904 …<description>When '1', attempt to transmit an acknowledgement (ACK). When this action is performed…
36910 …description>When '1', attempt to transmit a negative acknowledgement (NACK). When this action is p…
36916 …<description>When '1', attempt to transmit a STOP. When this action is performed, the hardware set…
36917 …STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP.</description>
36925 <description>I2C slave command</description>
36934 …description>When '1', attempt to transmit an acknowledgement (ACK). When this action is performed,…
36940 …description>When '1', attempt to transmit a negative acknowledgement (NACK). When this action is p…
36948 <description>I2C configuration</description>
36957 …<description>Trim bits for 'i2c_sda_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details…
36961 0: disable clock_scb_en, enable ec_busy_pp (grant I2CS_EC or SPIS_EC access)</description>
36967 <description>Selection of 'i2c_sda_in' filter delay:
36969 '1: 50 ns (filter enabled).</description>
36975 …<description>Trim bits for 'i2c_scl_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details…
36981 <description>Selection of 'i2c_scl_in' filter delay:
36983 '1: 50 ns (filter enabled).</description>
36989 …<description>Trim bits for 'i2c_sda_out' 50 ns filter 0. See s8i2cs BROS (001-59539) for more deta…
36995 …<description>Trim bits for 'i2c_sda_out' 50 ns filter 1. See s8i2cs BROS (001-59539) for more deta…
37001 …<description>Trim bits for 'i2c_sda_out' 50 ns filter 2. See s8i2cs BROS (001-59539) for more deta…
37007 <description>Selection of cumulative 'i2c_sda_out' filter delay:
37011 '3': 150 ns (filters 0, 1 and 2 enabled).</description>
37019 <description>Transmitter control</description>
37028 …description>Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. Thi…
37034 …<description>Least significant bit first ('0') or most significant bit first ('1'). For I2C, this …
37040 … <description>Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'.
37047 - SPI mode, 'spi_miso' IO cell.</description>
37055 <description>Transmitter FIFO control</description>
37064 …description>Trigger level. When the transmitter FIFO has less entries than the number of this fiel…
37070 …description>When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated.…
37076 …description>When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze …
37084 <description>Transmitter FIFO status</description>
37093 …<description>Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to F…
37099 …description>Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). …
37105 …<description>FIFO read pointer: FIFO location from which a data frame is read by the hardware.</de…
37111 … <description>FIFO write pointer: FIFO location at which a new data frame is written.</description>
37119 <description>Transmitter FIFO write</description>
37128 …<description>Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH o…
37130 A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'.</description>
37138 <description>Receiver control</description>
37147 …description>Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame.…
37153 …<description>Least significant bit first ('0') or most significant bit first ('1'). For I2C, this …
37159 …description>Median filter. When '1', a digital 3 taps median filter is performed on input interfac…
37167 <description>Receiver FIFO control</description>
37176 …description>Trigger level. When the receiver FIFO has more entries than the number of this field, …
37182 …description>When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Inval…
37188 …<description>When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advanc…
37196 <description>Receiver FIFO status</description>
37205 …<description>Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_D…
37211 …description>Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or n…
37217 … <description>FIFO read pointer: FIFO location from which a data frame is read.</description>
37223 …<description>FIFO write pointer: FIFO location at which a new data frame is written by the hardwar…
37231 <description>Slave address and mask</description>
37240 <description>Slave device address.
37244 …ddressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read).</description>
37250 …description>Slave device address mask. This field is a mask that specifies which of the ADDR field…
37258 <description>Receiver FIFO read</description>
37267 …<description>Data read from the receiver FIFO. Reading a data frame will remove the data frame fro…
37271 A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'.</description>
37279 <description>Receiver FIFO read silent</description>
37288 …<description>Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame…
37290 A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'.</description>
37298 <description>Active clocked interrupt signal</description>
37307 … <description>Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0.</description>
37313 … <description>Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0.</description>
37319 … <description>Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0.</description>
37325 … <description>Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0.</description>
37331 …<description>Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0.<…
37337 …<description>Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0…
37345 <description>Externally clocked I2C interrupt request</description>
37354 <description>Wake up request. Active on incoming slave request (with address match).
37356 Only used when EC_AM is '1'.</description>
37362 <description>STOP detection. Activated on the end of a every transfer (I2C STOP).
37364 …r a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'.</description>
37370 …<description>STOP detection after a write transfer occurred. Activated on the end of a write trans…
37372 …r a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'.</description>
37378 …<description>STOP detection after a read transfer occurred. Activated on the end of a read transfe…
37380 …r a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'.</description>
37388 <description>Externally clocked I2C interrupt mask</description>
37397 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37403 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37409 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37415 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37423 <description>Externally clocked I2C interrupt masked</description>
37432 <description>Logical and of corresponding request and mask bits.</description>
37438 <description>Logical and of corresponding request and mask bits.</description>
37444 <description>Logical and of corresponding request and mask bits.</description>
37450 <description>Logical and of corresponding request and mask bits.</description>
37458 <description>Externally clocked SPI interrupt request</description>
37467 …<description>Wake up request. Active on incoming slave request when externally clocked selection i…
37469 Only used when EC_AM is '1'.</description>
37475 … <description>STOP detection. Activated on the end of a every transfer (SPI deselection).
37477 Only available in EZ and CMD_RESP mode and when EC_OP is '1'.</description>
37483 …<description>STOP detection after a write transfer occurred. Activated on the end of a write trans…
37485 Only used in EZ and CMD_RESP modes and when EC_OP is '1'.</description>
37491 …<description>STOP detection after a read transfer occurred. Activated on the end of a read transfe…
37493 Only used in EZ and CMD_RESP modes and when EC_OP is '1'.</description>
37501 <description>Externally clocked SPI interrupt mask</description>
37510 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37516 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37522 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37528 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37536 <description>Externally clocked SPI interrupt masked</description>
37545 <description>Logical and of corresponding request and mask bits.</description>
37551 <description>Logical and of corresponding request and mask bits.</description>
37557 <description>Logical and of corresponding request and mask bits.</description>
37563 <description>Logical and of corresponding request and mask bits.</description>
37571 <description>Master interrupt request</description>
37580 …description>I2C master lost arbitration: the value driven by the master on the SDA line is not the…
37586 …description>I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typi…
37592 …description>I2C master acknowledgement. Set to '1', when the master receives a ACK (typically afte…
37598 … <description>I2C master STOP. Set to '1', when the master has transmitted a STOP.</description>
37604 … <description>I2C master bus error (unexpected detection of START or STOP condition).</description>
37610 …description>SPI master transfer done event: all data frames in the transmit FIFO are sent, the tra…
37618 <description>Master interrupt set request</description>
37627 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37633 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37639 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37645 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37651 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37657 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37665 <description>Master interrupt mask</description>
37674 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37680 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37686 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37692 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37698 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37704 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37712 <description>Master interrupt masked request</description>
37721 <description>Logical and of corresponding request and mask bits.</description>
37727 <description>Logical and of corresponding request and mask bits.</description>
37733 <description>Logical and of corresponding request and mask bits.</description>
37739 <description>Logical and of corresponding request and mask bits.</description>
37745 <description>Logical and of corresponding request and mask bits.</description>
37751 <description>Logical and of corresponding request and mask bits.</description>
37759 <description>Slave interrupt request</description>
37768 …description>I2C slave lost arbitration: the value driven on the SDA line is not the same as the va…
37774 …description>I2C slave negative acknowledgement received. Set to '1', when the slave receives a NAC…
37780 …<description>I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typica…
37786 …<description>I2C STOP event for I2C write transfer intended for this slave (address matching is pe…
37790 …nicates an I2C address and EZ address, will not result in this event being detected).</description>
37796 …<description>I2C STOP event for I2C (read or write) transfer intended for this slave (address matc…
37798 …result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd.</description>
37804 … <description>I2C slave START received. Set to '1', when START or REPEATED START event is detected.
37806 … Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL.</description>
37812 …description>I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (includ…
37818 …description>I2C slave general call address received. If CTRL.ADDR_ACCEPT, the received address 0x…
37824 …description>I2C slave bus error (unexpected detection of START or STOP condition). This should not…
37830 … <description>SPI slave deselected after a write EZ SPI transfer occurred.</description>
37836 <description>SPI slave deselected after any EZ SPI transfer occurred.</description>
37842 …description>SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decid…
37850 <description>Slave interrupt set request</description>
37859 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37865 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37871 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37877 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37883 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37889 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37895 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37901 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37907 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37913 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37919 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37925 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
37933 <description>Slave interrupt mask</description>
37942 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37948 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37954 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37960 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37966 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37972 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37978 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37984 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37990 … <description>Mask bit for corresponding bit in interrupt request register.</description>
37996 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38002 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38008 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38016 <description>Slave interrupt masked request</description>
38025 <description>Logical and of corresponding request and mask bits.</description>
38031 <description>Logical and of corresponding request and mask bits.</description>
38037 <description>Logical and of corresponding request and mask bits.</description>
38043 <description>Logical and of corresponding request and mask bits.</description>
38049 <description>Logical and of corresponding request and mask bits.</description>
38055 <description>Logical and of corresponding request and mask bits.</description>
38061 <description>Logical and of corresponding request and mask bits.</description>
38067 <description>Logical and of corresponding request and mask bits.</description>
38073 <description>Logical and of corresponding request and mask bits.</description>
38079 <description>Logical and of corresponding request and mask bits.</description>
38085 <description>Logical and of corresponding request and mask bits.</description>
38091 <description>Logical and of corresponding request and mask bits.</description>
38099 <description>Transmitter interrupt request</description>
38108 … <description>Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL.
38110 Only used in FIFO mode.</description>
38116 … <description>TX FIFO is not full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2)
38120 Only used in FIFO mode.</description>
38126 <description>TX FIFO is empty; i.e. it has 0 entries.
38128 Only used in FIFO mode.</description>
38134 <description>Attempt to write to a full TX FIFO.
38136 Only used in FIFO mode.</description>
38142 …<description>Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer …
38144 Only used in FIFO mode.</description>
38150 …description>AHB-Lite write transfer can not get access to the EZ memory (EZ data access), due to a…
38156 …description>UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1', wh…
38162 …description>UART transmitter done event. This happens when the IP is done transferring all data in…
38168 …description>UART lost arbitration: the value driven on the TX line is not the same as the value ob…
38176 <description>Transmitter interrupt set request</description>
38185 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
38191 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
38197 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
38203 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
38209 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
38215 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
38221 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
38227 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
38233 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
38241 <description>Transmitter interrupt mask</description>
38250 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38256 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38262 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38268 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38274 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38280 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38286 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38292 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38298 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38306 <description>Transmitter interrupt masked request</description>
38315 <description>Logical and of corresponding request and mask bits.</description>
38321 <description>Logical and of corresponding request and mask bits.</description>
38327 <description>Logical and of corresponding request and mask bits.</description>
38333 <description>Logical and of corresponding request and mask bits.</description>
38339 <description>Logical and of corresponding request and mask bits.</description>
38345 <description>Logical and of corresponding request and mask bits.</description>
38351 <description>Logical and of corresponding request and mask bits.</description>
38357 <description>Logical and of corresponding request and mask bits.</description>
38363 <description>Logical and of corresponding request and mask bits.</description>
38371 <description>Receiver interrupt request</description>
38380 … <description>More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL.
38382 Only used in FIFO mode.</description>
38388 <description>RX FIFO is not empty.
38390 Only used in FIFO mode.</description>
38396 …<description>RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. De…
38400 Only used in FIFO mode.</description>
38406 …<description>Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a dat…
38408 Only used in FIFO mode.</description>
38414 <description>Attempt to read from an empty RX FIFO.
38416 Only used in FIFO mode.</description>
38422 …description>AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses), due to …
38428 …<description>Frame error in received data frame. Set to '1', when event is detected. Write with '1…
38432 …the RX FIFO; i.e. the RX FIFO does not have error flags to tag erroneous data frames.</description>
38438 …description>Parity error in received data frame. Set to '1', when event is detected. Write with '1…
38444 …description>LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR…
38450 …description>Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit pe…
38458 <description>Receiver interrupt set request</description>
38467 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
38473 … <description>Write with '1' to set corresponding bit in interrupt status register.</description>
38479 … <description>Write with '1' to set corresponding bit in interrupt status register.</description>
38485 … <description>Write with '1' to set corresponding bit in interrupt status register.</description>
38491 … <description>Write with '1' to set corresponding bit in interrupt status register.</description>
38497 … <description>Write with '1' to set corresponding bit in interrupt status register.</description>
38503 … <description>Write with '1' to set corresponding bit in interrupt status register.</description>
38509 … <description>Write with '1' to set corresponding bit in interrupt status register.</description>
38515 … <description>Write with '1' to set corresponding bit in interrupt status register.</description>
38521 … <description>Write with '1' to set corresponding bit in interrupt status register.</description>
38529 <description>Receiver interrupt mask</description>
38538 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38544 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38550 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38556 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38562 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38568 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38574 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38580 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38586 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38592 … <description>Mask bit for corresponding bit in interrupt request register.</description>
38600 <description>Receiver interrupt masked request</description>
38609 <description>Logical and of corresponding request and mask bits.</description>
38615 <description>Logical and of corresponding request and mask bits.</description>
38621 <description>Logical and of corresponding request and mask bits.</description>
38627 <description>Logical and of corresponding request and mask bits.</description>
38633 <description>Logical and of corresponding request and mask bits.</description>
38639 <description>Logical and of corresponding request and mask bits.</description>
38645 <description>Logical and of corresponding request and mask bits.</description>
38651 <description>Logical and of corresponding request and mask bits.</description>
38657 <description>Logical and of corresponding request and mask bits.</description>
38663 <description>Logical and of corresponding request and mask bits.</description>
38705 <description>Continuous Time Block Mini</description>
38716 <description>global CTB and power control</description>
38725 <description>- 0: CTB IP disabled off during DeepSleep power mode
38726 - 1: CTB IP remains enabled during DeepSleep power mode (if ENABLED=1)</description>
38732 <description>- 0: CTB IP disabled (put analog in power down, open all switches)
38733 - 1: CTB IP enabled</description>
38741 <description>Opamp0 and resistor0 control</description>
38750 …<description>Opamp0 power level, assumes Cload=15pF for the (internal only) 1x driver or 50pF for …
38756 <description>Off</description>
38761 <description>Low power mode (IDD: 350uA, GBW: 1MHz for both 1x/10x)</description>
38766 … <description>Medium power mode (IDD: 600uA, GBW: 3MHz for 1x & 2.5MHz for 10x)</description>
38771 …<description>High power mode for highest GBW (IDD: 1500uA, GBW: 8MHz for 1x & 6MHz for 10x)</d…
38776 <description>N/A</description>
38781 …<description>Power Saver Low power mode (IDD: ~20uA with 1uA bias from AREF, GBW: ~100kHz for 1x/1…
38786 …<description>Power Saver Medium power mode (IDD: ~40uA with 1uA bias from AREF, GBW: ~100kHz for 1…
38791 …<description>Power Saver Medium power mode (IDD: ~60uA with 1uA bias from AREF, GBW: ~200kHz for 1…
38798 <description>Opamp0 output strength select 0=1x, 1=10x
38799 This setting sets specific requirements for OA0_BOOST_EN and OA0_COMP_TRIM</description>
38805 <description>Opamp0 comparator enable</description>
38811 <description>Opamp0 hysteresis enable (10mV)</description>
38817 …description>Opamp0 bypass comparator output synchronization for DSI (trigger) output: 0=synchroniz…
38823 <description>Opamp0 comparator DSI (trigger) out level :
38825 1=level, DSI output is a synchronized version of the comparator output</description>
38831 …<description>Opamp0 comparator edge detect for interrupt and pulse mode of DSI (trigger)</descript…
38837 <description>Disabled, no interrupts will be detected</description>
38842 <description>Rising edge</description>
38847 <description>Falling edge</description>
38852 <description>Both rising and falling edges</description>
38859 <description>Opamp0 pump enable</description>
38865 …description>Opamp0 gain booster enable for class A output, for risk mitigation only, not user sele…
38873 <description>Opamp1 and resistor1 control</description>
38882 <description>Opamp1 power level: see description of OA0_PWR_MODE</description>
38888 <description>Opamp1 output strength select 0=1x, 1=10x
38889 This setting sets specific requirements for OA1_BOOST_EN and OA1_COMP_TRIM</description>
38895 <description>Opamp1 comparator enable</description>
38901 <description>Opamp1 hysteresis enable (10mV)</description>
38907 …<description>Opamp1 bypass comparator output synchronization for DSI output: 0=synchronize, 1=bypa…
38913 <description>Opamp1 comparator DSI (trigger) out level :
38915 1=level, DSI output is a synchronized version of the comparator output</description>
38921 …<description>Opamp1 comparator edge detect for interrupt and pulse mode of DSI (trigger)</descript…
38927 <description>Disabled, no interrupts will be detected</description>
38932 <description>Rising edge</description>
38937 <description>Falling edge</description>
38942 <description>Both rising and falling edges</description>
38949 <description>Opamp1 pump enable</description>
38955 …description>Opamp1 gain booster enable for class A output, for risk mitigation only, not user sele…
38963 <description>Comparator status</description>
38972 <description>Opamp0 current comparator status</description>
38978 <description>Opamp1 current comparator status</description>
38986 <description>Interrupt request register</description>
38995 …<description>Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Writ…
39001 …<description>Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Writ…
39009 <description>Interrupt request set register</description>
39018 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39024 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39032 <description>Interrupt request mask</description>
39041 … <description>Mask bit for corresponding bit in interrupt request register.</description>
39047 … <description>Mask bit for corresponding bit in interrupt request register.</description>
39055 <description>Interrupt request masked</description>
39064 <description>Logical and of corresponding request and mask bits.</description>
39070 <description>Logical and of corresponding request and mask bits.</description>
39078 <description>Opamp0 switch control</description>
39087 <description>Opamp0 positive terminal amuxbusa</description>
39093 <description>Opamp0 positive terminal P0</description>
39099 <description>Opamp0 positive terminal ctbbus0</description>
39105 <description>Opamp0 negative terminal P1</description>
39111 <description>Opamp0 negative terminal Opamp0 output</description>
39117 <description>Opamp0 output sarbus0 (ctbbus2 in CTB)</description>
39123 <description>Opamp0 output switch to short 1x with 10x drive</description>
39131 <description>Opamp0 switch control clear</description>
39140 <description>see corresponding bit in OA0_SW</description>
39146 <description>see corresponding bit in OA0_SW</description>
39152 <description>see corresponding bit in OA0_SW</description>
39158 <description>see corresponding bit in OA0_SW</description>
39164 <description>see corresponding bit in OA0_SW</description>
39170 <description>see corresponding bit in OA0_SW</description>
39176 <description>see corresponding bit in OA0_SW</description>
39184 <description>Opamp1 switch control</description>
39193 <description>Opamp1 positive terminal amuxbusb</description>
39199 <description>Opamp1 positive terminal P5</description>
39205 <description>Opamp1 positive terminal ctbbus1</description>
39211 <description>Opamp1 positive terminal to vref1</description>
39217 <description>Opamp1 negative terminal P4</description>
39223 <description>Opamp1 negative terminal Opamp1 output</description>
39229 <description>Opamp1 output sarbus0 (ctbbus2 in CTB)</description>
39235 <description>Opamp1 output sarbus1 (ctbbus3 in CTB)</description>
39241 <description>Opamp1 output switch to short 1x with 10x drive</description>
39249 <description>Opamp1 switch control clear</description>
39258 <description>see corresponding bit in OA1_SW</description>
39264 <description>see corresponding bit in OA1_SW</description>
39270 <description>see corresponding bit in OA1_SW</description>
39276 <description>see corresponding bit in OA1_SW</description>
39282 <description>see corresponding bit in OA1_SW</description>
39288 <description>see corresponding bit in OA1_SW</description>
39294 <description>see corresponding bit in OA1_SW</description>
39300 <description>see corresponding bit in OA1_SW</description>
39306 <description>see corresponding bit in OA1_SW</description>
39314 <description>CTDAC connection switch control</description>
39323 <description>CTDAC Reference opamp output to ctdrefdrive</description>
39329 <description>ctdrefsense to opamp input</description>
39335 <description>ctdvout to opamp input</description>
39341 <description>P6 pin to Hold capacitor</description>
39347 …description>ctdvout to Hold capacitor (Sample switch). Note this switch will temporarily be opened…
39353 …<description>Drive the CTDAC output with CTBM 1x output during hold mode in Sample and Hold operat…
39359 <description>Hold capacitor connect</description>
39365 <description>Hold capacitor to opamp input</description>
39371 <description>Hold capacitor isolation (from all the other switches)</description>
39377 …<description>Hold capacitor leakage reduction (drive other side of CIS to capacitor voltage)</desc…
39385 <description>CTDAC connection switch control clear</description>
39394 <description>see corresponding bit in CTD_SW</description>
39400 <description>see corresponding bit in CTD_SW</description>
39406 <description>see corresponding bit in CTD_SW</description>
39412 <description>see corresponding bit in CTD_SW</description>
39418 <description>see corresponding bit in CTD_SW</description>
39424 <description>see corresponding bit in CTD_SW</description>
39430 <description>see corresponding bit in CTD_SW</description>
39436 <description>see corresponding bit in CTD_SW</description>
39442 <description>see corresponding bit in CTD_SW</description>
39448 <description>see corresponding bit in CTD_SW</description>
39456 <description>CTB bus switch control</description>
39465 <description>for P22, D51 (dsi_out[2])</description>
39471 <description>for P33, D52, D62 (dsi_out[3])</description>
39477 <description>Hold capacitor Sample switch (COS)</description>
39485 <description>CTB bus switch Sar Sequencer control</description>
39494 <description>for D51</description>
39500 <description>for D52, D62</description>
39508 <description>CTB bus switch control status</description>
39517 <description>see OA0O_D51 bit in OA0_SW</description>
39523 <description>see OA1O_D52 bit in OA1_SW</description>
39529 <description>see OA1O_D62 bit in OA1_SW</description>
39535 <description>see COS bit in CTD_SW</description>
39543 <description>Opamp0 trim control</description>
39552 <description>Opamp0 offset trim</description>
39560 <description>Opamp0 trim control</description>
39569 <description>Opamp0 slope offset drift trim</description>
39577 <description>Opamp0 trim control</description>
39586 <description>Opamp0 Compensation Capacitor Trim.
39587 Value depends on the drive strength setting - 1x mode: set to 01; 10x mode: set to 11</description>
39595 <description>Opamp1 trim control</description>
39604 <description>Opamp1 offset trim</description>
39612 <description>Opamp1 trim control</description>
39621 <description>Opamp1 slope offset drift trim</description>
39629 <description>Opamp1 trim control</description>
39638 <description>Opamp1 Compensation Capacitor Trim.
39639 Value depends on the drive strength setting - 1x mode: set to 01; 10x mode: set to 11</description>
39649 <description>Continuous Time DAC</description>
39660 <description>Global CTDAC control</description>
39669 …description>To prevent glitches after VALUE changes from propagating the output switch can be open…
39675 …<description>Force CTDAC.CO6 switch open after each VALUE change for the set number of clock cycle…
39681 …<description>Force CTB.COS switch open after each VALUE change for the set number of clock cycles.…
39687 …<description>Output enable, intended to be used during the Hold phase of the Sample and Hold when …
39692 1: output enabled, CTDAC output drives the programmed VALUE</description>
39698 …<description>By closing the bottom switch in the R2R network the output is lifted by one LSB, effe…
39700 1: Range is [1, 4096] * Vref / 4096</description>
39706 <description>DAC mode, this determines the Value decoding</description>
39712 <description>Unsigned 12-bit VDAC, i.e. no value decoding.</description>
39717 <description>Virtual signed 12-bits' VDAC. Value decoding:
39718 …ed number 0x000. This is the same as the SAR handles 12-bit 'virtual' signed numbers.</description>
39723 <description>N/A</description>
39728 <description>N/A</description>
39735 … <description>Select the output value when the output is disabled (OUT_EN=0) (for risk mitigation)
39737 1: output Vssa or Vref when disabled (see OUT_EN description)</description>
39743 … <description>DSI strobe input Enable. This enables CTDAC updates to be further throttled by DSI.
39745 …o a CTDAC update if allowed by the DSI strobe (throttle), see below for level or edge</description>
39751 <description>Select level or edge detect for DSI strobe
39753 …be signal remains high the CTDAC will do a next DAC value update on each CTDAC clock.</description>
39759 <description>- 0: CTDAC IP disabled off during DeepSleep power mode
39760 - 1: CTDAC IP remains enabled during DeepSleep power mode (if ENABLED=1)</description>
39766 <description>0: CTDAC IP disabled (put analog in power down, open all switches)
39767 1: CTDAC IP enabled</description>
39775 <description>Interrupt request register</description>
39784 …description>VDAC Interrupt: hardware sets this interrupt when VDAC next value field is empty, i.e.…
39792 <description>Interrupt request set register</description>
39801 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39809 <description>Interrupt request mask</description>
39818 … <description>Mask bit for corresponding bit in interrupt request register.</description>
39826 <description>Interrupt request masked</description>
39835 <description>Logical and of corresponding request and mask bits.</description>
39843 <description>CTDAC switch control</description>
39852 <description>VDDA supply to ctdrefdrive</description>
39858 …<description>ctdvout to P6 pin. Note this switch will temporarily be opened for deglitching if DEG…
39866 <description>CTDAC switch control clear</description>
39875 <description>see corresponding bit in CTD_SW</description>
39881 <description>see corresponding bit in CTD_SW</description>
39889 <description>DAC Value</description>
39898 <description>Value, in CTDAC_MODE 1 this value is decoded</description>
39906 <description>Next DAC value (double buffering)</description>
39915 <description>Next value for CTDAC_VAL.VALUE</description>
39925 <description>SAR ADC with Sequencer</description>
39935 <description>Analog control register.</description>
39944 <description>VREF buffer low power mode.</description>
39950 … <description>full power (100 percent) (default), bypass cap, max clk_sar is 18MHz.</description>
39955 <description>80 percent power</description>
39960 <description>60 percent power</description>
39965 <description>50 percent power</description>
39970 <description>40 percent power</description>
39975 <description>30 percent power</description>
39980 <description>20 percent power</description>
39985 <description>10 percent power</description>
39992 <description>SARADC internal VREF selection.</description>
39998 <description>VREF0 from PRB (VREF buffer on)</description>
40003 <description>VREF1 from PRB (VREF buffer on)</description>
40008 <description>VREF2 from PRB (VREF buffer on)</description>
40013 <description>VREF from AROUTE (VREF buffer on)</description>
40018 <description>1.024V from BandGap (VREF buffer on)</description>
40023 … <description>External precision Vref direct from a pin (low impedance path).</description>
40028 <description>Vdda/2 (VREF buffer on)</description>
40033 <description>Vdda.</description>
40040 <description>VREF bypass cap enable for when VREF buffer is on</description>
40046 <description>SARADC internal NEG selection for Single ended conversion</description>
40052 …description>NEG input of SARADC is connected to 'vssa_kelvin', gives more precision around zero. N…
40057 … <description>NEG input of SARADC is connected to VSSA in AROUTE close to the SARADC</description>
40062 <description>NEG input of SARADC is connected to P1 pin of SARMUX</description>
40067 <description>NEG input of SARADC is connected to P3 pin of SARMUX</description>
40072 <description>NEG input of SARADC is connected to P5 pin of SARMUX</description>
40077 <description>NEG input of SARADC is connected to P7 pin of SARMUX</description>
40082 <description>NEG input of SARADC is connected to an ACORE in AROUTE</description>
40087 … <description>NEG input of SARADC is shorted with VREF input of SARADC.</description>
40094 …<description>Hardware control: 0=only firmware control, 1=hardware control masked by firmware sett…
40100 … <description>Set the comparator latch delay in accordance with SAR conversion rate</description>
40106 <description>2.5ns delay, use this for 2.5Msps</description>
40111 <description>4.0ns delay, use this for 2.0Msps</description>
40116 <description>10ns delay, use this for 1.5Msps</description>
40121 <description>12ns delay, use this for 1.0Msps or less</description>
40128 … <description>Spare controls, not yet designated, for late changes done with an ECO</description>
40134 <description>deprecated</description>
40140 …<description>For normal ADC operation this bit must be set, for all reference choices - internal, …
40141 Setting this bit is critical to proper function of switches inside SARREF block.</description>
40147 <description>Comparator power mode.</description>
40153 …<description>Power = 100 percent, Use this for SAR Clock Frequency greater than 18MHz</description>
40158 <description>N/A</description>
40163 …<description>Power = 60 percent, Use this for SAR Clock Frequency greater than 1.8MHz up to 18MHz.…
40168 <description>N/A</description>
40173 <description>N/A</description>
40178 <description>N/A</description>
40183 …<description>Power = 20 percent, Use this for SAR Clock Frequency less than or equal to 1.8MHz</de…
40188 <description>N/A</description>
40195 <description>- 0: SARMUX IP disabled off during DeepSleep power mode
40196 - 1: SARMUX IP remains enabled during DeepSleep power mode (if ENABLED=1)</description>
40202 <description>- 0: bypass clock domain synchronization of the DSI config signals.
40203 - 1: synchronize the DSI config signals to peripheral clock domain.</description>
40209 …<description>SAR sequencer takes configuration from DSI signals (note this also has the same effec…
40211 …NJ_START_EN and channel configurations in CHAN_CONFIG and INJ_CHAN_CONFIG are ignored</description>
40217 …<description>Disable SAR sequencer from enabling routing switches (note DSI and firmware can alway…
40219 …rough DSI) to set the switches to route the signal to be converted through the SARMUX</description>
40225 …<description>- 0: SAR IP disabled (put analog in power down and stop clocks), also can clear FW_TR…
40226 - 1: SAR IP enabled.</description>
40234 <description>Sample control register.</description>
40243 …description>Left align data in data[15:0], default data is right aligned in data[11:0], with sign …
40249 <description>Output data from a single ended conversion as a signed value
40251 …ing), then SINGLE_ENDED_SIGNED must be configured identically to DIFFERENTIAL_SIGNED.</description>
40257 … <description>Default: result data is unsigned (zero extended if needed)</description>
40262 <description>result data is signed (sign extended if needed)</description>
40269 …<description>Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or …
40271 …ing), then DIFFERENTIAL_SIGNED must be configured identically to SINGLE_ENDED_SIGNED.</description>
40277 <description>result data is unsigned (zero extended if needed)</description>
40282 … <description>Default: result data is signed (sign extended if needed)</description>
40289 …<description>Averaging Count for channels that have averaging enabled (AVG_EN). A channel will be …
40291 … a 12-bit resolution the averaging count should be set to 16 or less (AVG_CNT=<3).</description>
40297 …<description>Averaging shifting: after averaging the result is shifted right to fit in 12 bits.</d…
40303 …<description>Averaging mode, in DSI mode this bit is ignored and only AccuNDump mode is available…
40309 …<description>Accumulate and Dump (1st order accumulate and dump filter): a channel will be sampled…
40314 …<description>Interleaved: Each scan (trigger) one sample is taken per channel and averaged over se…
40321 …<description>- 0: Wait for next FW_TRIGGER (one shot) or hardware trigger (e.g. from TPWM for peri…
40322 - 1: Continuously scan enabled channels, ignore triggers.</description>
40328 <description>- 0: firmware trigger only: disable hardware trigger tr_sar_in.
40329 - 1: enable hardware trigger tr_sar_in (e.g. from TCPWM, GPIO or UDB).</description>
40335 …<description>- 0: trigger signal is a pulse input, a positive edge detected on the trigger signal …
40336 …l input, as long as the trigger signal remains high the SAR will do continuous scans.</description>
40342 <description>- 0: bypass clock domain synchronization of the trigger signal.
40343 …he SAR clock domain, if needed an edge detect is done in the peripheral clock domain.</description>
40349 …<description>Select whether UABs are scheduled or unscheduled. When no UAB is scanned this selecti…
40355 …description>Unscheduled UABs: one or more of the UABs scanned by the SAR is not scheduled, for eac…
40360 …<description>Scheduled UABs: All UABs scanned by the SAR are assumed to be properly scheduled, i.e…
40361 …sample period (using UAB.STARTUP_DELAY). Normally this scheduling is done by Creator.</description>
40368 …<description>For unscheduled UAB_SCAN_MODE only, do the following if an invalid sample is received:
40370 …: could be never if the UAB valid window is incorrectly schedule w.r.t. SAR sampling)</description>
40376 <description>Static UAB Valid select
40384 7=UAB3 half 1 Valid output</description>
40390 <description>Enable static UAB Valid selection (override Hardware)</description>
40396 …description>Ignore UAB valid signal, including the dynamic/Hardware from AROUTE and the static Val…
40402 …description>SAR output trigger enable (used for UAB synchronization). To ensure multiple UABs star…
40408 …description>Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardwa…
40416 <description>Sample time specification ST0 and ST1</description>
40425 …description>Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is one clock…
40431 <description>Sample time1</description>
40439 <description>Sample time specification ST2 and ST3</description>
40448 <description>Sample time2</description>
40454 <description>Sample time3</description>
40462 <description>Global range detect threshold register.</description>
40471 <description>Low threshold for range detect.</description>
40477 <description>High threshold for range detect.</description>
40485 <description>Global range detect mode register.</description>
40494 <description>Range condition select.</description>
40500 <description>result < RANGE_LOW</description>
40505 <description>RANGE_LOW <= result < RANGE_HIGH</description>
40510 <description>RANGE_HIGH <= result</description>
40515 <description>result < RANGE_LOW || RANGE_HIGH <= result</description>
40524 <description>Enable bits for the channels</description>
40533 <description>Channel enable.
40535 - 1: the corresponding channel is enabled, it will be included in the next scan.</description>
40543 <description>Start control register (firmware trigger).</description>
40552 …description>When firmware writes a 1 here it will trigger the next scan of enabled channels, hardw…
40562 <description>Channel configuration register.</description>
40571 … <description>Address of the pin to be sampled by this channel (connected to Vplus)</description>
40577 …<description>Address of the port that contains the pin to be sampled by this channel (connected to…
40583 <description>SARMUX pins.</description>
40588 <description>CTB0</description>
40593 <description>CTB1</description>
40598 <description>CTB2</description>
40603 <description>CTB3</description>
40608 <description>AROUTE virtual port2 (VPORT2)</description>
40613 <description>AROUTE virtual port1 (VPORT1)</description>
40618 <description>SARMUX virtual port (VPORT0)</description>
40625 <description>Differential enable for this channel.
40628 … the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).</description>
40634 …<description>Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used…
40640 …<description>Sample time select: select which of the 4 global sample times to use for this channel…
40646 <description>Address of the neg pin to be sampled by this channel.</description>
40652 …<description>Address of the neg port that contains the pin to be sampled by this channel.</descrip…
40658 <description>SARMUX pins.</description>
40663 <description>AROUTE virtual port2 (VPORT2)</description>
40668 <description>AROUTE virtual port1 (VPORT1)</description>
40673 <description>SARMUX virtual port (VPORT0)</description>
40680 …description>1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is …
40686 <description>DSI data output enable for this channel.
40688 … channel number, is sent out on the DSI communication channel for processing in UDBs.</description>
40698 <description>Channel working data register</description>
40707 …<description>SAR conversion working data of the channel. The data is written here right after samp…
40713 … <description>mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register</description>
40719 … <description>mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register</description>
40729 <description>Channel result data register</description>
40738 …description>SAR conversion result of the channel. The data is copied here from the WORK field afte…
40744 … <description>mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register</description>
40750 … <description>mirror bit of corresponding bit in SAR_SATURATE_INTR register</description>
40756 <description>mirror bit of corresponding bit in SAR_RANGE_INTR register</description>
40762 … <description>mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register</description>
40770 <description>Channel working data register 'updated' bits</description>
40779 …description>If set the corresponding WORK register was updated, i.e. was already sampled during th…
40787 <description>Channel result data register 'updated' bits</description>
40796 …description>If set the corresponding RESULT register was updated, i.e. was sampled during the prev…
40804 <description>Channel working data register 'new value' bits</description>
40813 …<description>If set the corresponding WORK data received a new value, i.e. was already sampled dur…
40815 …raging this New Value bit is an OR of all the valid bits received by each conversion.</description>
40823 <description>Channel result data register 'new value' bits</description>
40832 …<description>If set the corresponding RESULT data received a new value, i.e. was sampled during th…
40834 …raging this New Value bit is an OR of all the valid bits received by each conversion.</description>
40842 <description>Interrupt request register.</description>
40851 …description>End Of Scan Interrupt: hardware sets this interrupt after completing a scan of all the…
40857 …description>Overflow Interrupt: hardware sets this interrupt when it sets a new EOS_INTR while tha…
40863 …description>Firmware Collision Interrupt: hardware sets this interrupt when FW_TRIGGER is asserted…
40869 …description>DSI Collision Interrupt: hardware sets this interrupt when the DSI trigger signal is a…
40875 …description>Injection End of Conversion Interrupt: hardware sets this interrupt after completing t…
40881 …description>Injection Saturation Interrupt: hardware sets this interrupt if an injection conversio…
40887 …description>Injection Range detect Interrupt: hardware sets this interrupt if the injection conver…
40893 …description>Injection Collision Interrupt: hardware sets this interrupt when the injection trigger…
40901 <description>Interrupt set request register</description>
40910 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
40916 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
40922 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
40928 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
40934 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
40940 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
40946 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
40952 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
40960 <description>Interrupt mask register.</description>
40969 … <description>Mask bit for corresponding bit in interrupt request register.</description>
40975 … <description>Mask bit for corresponding bit in interrupt request register.</description>
40981 … <description>Mask bit for corresponding bit in interrupt request register.</description>
40987 … <description>Mask bit for corresponding bit in interrupt request register.</description>
40993 … <description>Mask bit for corresponding bit in interrupt request register.</description>
40999 … <description>Mask bit for corresponding bit in interrupt request register.</description>
41005 … <description>Mask bit for corresponding bit in interrupt request register.</description>
41011 … <description>Mask bit for corresponding bit in interrupt request register.</description>
41019 <description>Interrupt masked request register</description>
41028 <description>Logical and of corresponding request and mask bits.</description>
41034 <description>Logical and of corresponding request and mask bits.</description>
41040 <description>Logical and of corresponding request and mask bits.</description>
41046 <description>Logical and of corresponding request and mask bits.</description>
41052 <description>Logical and of corresponding request and mask bits.</description>
41058 <description>Logical and of corresponding request and mask bits.</description>
41064 <description>Logical and of corresponding request and mask bits.</description>
41070 <description>Logical and of corresponding request and mask bits.</description>
41078 <description>Saturate interrupt request register.</description>
41087 …description>Saturate Interrupt: hardware sets this interrupt for each channel if a conversion resu…
41095 <description>Saturate interrupt set request register</description>
41104 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41112 <description>Saturate interrupt mask register.</description>
41121 … <description>Mask bit for corresponding bit in interrupt request register.</description>
41129 <description>Saturate interrupt masked request register</description>
41138 <description>Logical and of corresponding request and mask bits.</description>
41146 <description>Range detect interrupt request register.</description>
41155 …description>Range detect Interrupt: hardware sets this interrupt for each channel if the conversio…
41163 <description>Range detect interrupt set request register</description>
41172 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41180 <description>Range detect interrupt mask register.</description>
41189 … <description>Mask bit for corresponding bit in interrupt request register.</description>
41197 <description>Range interrupt masked request register</description>
41206 <description>Logical and of corresponding request and mask bits.</description>
41214 <description>Interrupt cause register</description>
41223 <description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
41229 <description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
41235 <description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
41241 <description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
41247 <description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
41253 <description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
41259 <description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
41265 <description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
41271 <description>Reduction OR of all SAR_SATURATION_INTR_MASKED bits</description>
41277 <description>Reduction OR of all SAR_RANGE_INTR_MASKED bits</description>
41285 <description>Injection channel configuration register.</description>
41294 …description>Address of the pin to be sampled by this injection channel. If differential is enabled…
41300 …<description>Address of the port that contains the pin to be sampled by this channel.</description>
41306 <description>SARMUX pins.</description>
41311 <description>CTB0</description>
41316 <description>CTB1</description>
41321 <description>CTB2</description>
41326 <description>CTB3</description>
41331 <description>AROUTE virtual port</description>
41336 <description>SARMUX virtual port</description>
41343 <description>Differential enable for this channel.
41345 …ing value is stored in the corresponding data register. (INJ_PIN_ADDR[0] is ignored).</description>
41351 …<description>Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used…
41357 …<description>Injection sample time select: select which of the 4 global sample times to use for th…
41363 <description>Injection channel tailgating.
41365 …n is sampled after the next trigger and after all enabled channels have been scanned.</description>
41371 …description>Set by firmware to enable the injection channel. If INJ_TAILGATING is not set this bit…
41379 <description>Injection channel result register</description>
41388 <description>SAR conversion result of the channel.</description>
41394 …<description>The data in this register received a new value (only relevant for UAB, this bit shows…
41400 <description>mirror bit of corresponding bit in SAR_INTR register</description>
41406 <description>mirror bit of corresponding bit in SAR_INTR register</description>
41412 <description>mirror bit of corresponding bit in SAR_INTR register</description>
41418 <description>mirror bit of corresponding bit in SAR_INTR register</description>
41426 <description>Current status of internal SAR registers (mostly for debug)</description>
41435 …<description>current channel being sampled (channel 16 indicates the injection channel), only vali…
41441 …description>the current switch status, including DSI and sequencer controls, of the switch in the …
41447 …description>If high then the SAR is busy with a conversion. This bit is always high when CONTINUOU…
41455 <description>Current averaging status (for debug)</description>
41464 <description>the current value of the averaging accumulator</description>
41470 …<description>If high then the SAR is in the middle of Interleaved averaging spanning several scans…
41471 …t can be cleared by changing the averaging mode to ACCUNDUMP or by disabling the SAR.</description>
41477 …description>the current value of the averaging counter. Note that the value shown is updated after…
41485 <description>SARMUX Firmware switch controls</description>
41494 …<description>Firmware control: 0=open, 1=close switch between pin P0 and vplus signal. Write with …
41500 …<description>Firmware control: 0=open, 1=close switch between pin P1 and vplus signal. Write with …
41506 …<description>Firmware control: 0=open, 1=close switch between pin P2 and vplus signal. Write with …
41512 …<description>Firmware control: 0=open, 1=close switch between pin P3 and vplus signal. Write with …
41518 …<description>Firmware control: 0=open, 1=close switch between pin P4 and vplus signal. Write with …
41524 …<description>Firmware control: 0=open, 1=close switch between pin P5 and vplus signal. Write with …
41530 …<description>Firmware control: 0=open, 1=close switch between pin P6 and vplus signal. Write with …
41536 …<description>Firmware control: 0=open, 1=close switch between pin P7 and vplus signal. Write with …
41542 …<description>Firmware control: 0=open, 1=close switch between pin P0 and vminus signal. Write with…
41548 …<description>Firmware control: 0=open, 1=close switch between pin P1 and vminus signal. Write with…
41554 …<description>Firmware control: 0=open, 1=close switch between pin P2 and vminus signal. Write with…
41560 …<description>Firmware control: 0=open, 1=close switch between pin P3 and vminus signal. Write with…
41566 …<description>Firmware control: 0=open, 1=close switch between pin P4 and vminus signal. Write with…
41572 …<description>Firmware control: 0=open, 1=close switch between pin P5 and vminus signal. Write with…
41578 …<description>Firmware control: 0=open, 1=close switch between pin P6 and vminus signal. Write with…
41584 …<description>Firmware control: 0=open, 1=close switch between pin P7 and vminus signal. Write with…
41590 …<description>Firmware control: 0=open, 1=close switch between vssa_kelvin and vminus signal. Write…
41596 …description>Firmware control: 0=open, 1=close switch between temperature sensor and vplus signal, …
41602 …<description>Firmware control: 0=open, 1=close switch between amuxbusa and vplus signal. Write wit…
41608 …<description>Firmware control: 0=open, 1=close switch between amuxbusb and vplus signal. Write wit…
41614 …<description>Firmware control: 0=open, 1=close switch between amuxbusa and vminus signal. Write wi…
41620 …<description>Firmware control: 0=open, 1=close switch between amuxbusb and vminus signal. Write wi…
41626 …<description>Firmware control: 0=open, 1=close switch between sarbus0 and vplus signal. Write with…
41632 …<description>Firmware control: 0=open, 1=close switch between sarbus1 and vplus signal. Write with…
41638 …<description>Firmware control: 0=open, 1=close switch between sarbus0 and vminus signal. Write wit…
41644 …<description>Firmware control: 0=open, 1=close switch between sarbus1 and vminus signal. Write wit…
41650 …<description>Firmware control: 0=open, 1=close switch between P4 and coreio0 signal. Write with '1…
41656 …<description>Firmware control: 0=open, 1=close switch between P5 and coreio1 signal. Write with '1…
41662 …<description>Firmware control: 0=open, 1=close switch between P6 and coreio2 signal. Write with '1…
41668 …<description>Firmware control: 0=open, 1=close switch between P7 and coreio3 signal. Write with '1…
41676 <description>SARMUX Firmware switch control clear</description>
41685 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41691 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41697 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41703 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41709 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41715 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41721 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41727 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41733 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41739 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41745 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41751 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41757 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41763 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41769 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41775 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41781 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41787 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41793 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41799 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41805 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41811 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41817 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41823 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41829 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41835 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41841 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41847 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41853 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41859 <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
41867 <description>SARMUX switch DSI control</description>
41876 <description>for P0 switches</description>
41882 <description>for P1 switches</description>
41888 <description>for P2 switches</description>
41894 <description>for P3 switches</description>
41900 <description>for P4 switches</description>
41906 <description>for P5 switches</description>
41912 <description>for P6 switches</description>
41918 <description>for P7 switches</description>
41924 <description>for vssa switch</description>
41930 <description>for temp switch</description>
41936 <description>for amuxbusa switch</description>
41942 <description>for amuxbusb switches</description>
41948 <description>for sarbus0 switch</description>
41954 <description>for sarbus1 switch</description>
41962 <description>SARMUX switch Sar Sequencer control</description>
41971 <description>for P0 switches</description>
41977 <description>for P1 switches</description>
41983 <description>for P2 switches</description>
41989 <description>for P3 switches</description>
41995 <description>for P4 switches</description>
42001 <description>for P5 switches</description>
42007 <description>for P6 switches</description>
42013 <description>for P7 switches</description>
42019 <description>for vssa switch</description>
42025 <description>for temp switch</description>
42031 <description>for amuxbusa switch</description>
42037 <description>for amuxbusb switches</description>
42043 <description>for sarbus0 switch</description>
42049 <description>for sarbus1 switch</description>
42057 <description>SARMUX switch status</description>
42066 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42072 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42078 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42084 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42090 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42096 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42102 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42108 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42114 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42120 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42126 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42132 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42138 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42144 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42150 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42156 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42162 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42168 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42174 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42180 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42186 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42192 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42198 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42204 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42210 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42216 <description>switch status of corresponding bit in MUX_SWITCH0</description>
42224 <description>Analog trim register.</description>
42233 <description>Attenuation cap trimming</description>
42239 <description>Attenuation cap trimming</description>
42247 <description>Analog trim register.</description>
42256 <description>SAR Reference buffer trim</description>
42266 <description>PASS top-level MMIO (DSABv2, INTR)</description>
42276 <description>Interrupt cause register</description>
42285 <description>CTB0 interrupt pending</description>
42291 <description>CTB1 interrupt pending</description>
42297 <description>CTB2 interrupt pending</description>
42303 <description>CTB3 interrupt pending</description>
42309 <description>CTDAC0 interrupt pending</description>
42315 <description>CTDAC1 interrupt pending</description>
42321 <description>CTDAC2 interrupt pending</description>
42327 <description>CTDAC3 interrupt pending</description>
42335 <description>AREF configuration</description>
42339 <description>global AREF control</description>
42348 … <description>Control bit to trade off AREF settling and noise performance</description>
42354 …<description>Nominal noise normal startup mode (meets normal mode settling and noise specification…
42359 …<description>High noise fast startup mode (meets fast mode settling and noise specifications)</des…
42366 …<description>BIAS Current Control for all AREF Amplifiers. (These are risk mitigation bits that s…
42370 …r increased bias: increase in total AREF IDDA, lower noise and shorter startup times)</description>
42376 <description>AREF control signals (RMB).
42388 1: VBG offset correction DAC is enabled while VBG startup is active</description>
42394 …<description>CTB IPTAT current scaler. This bit must be set in order to operate the CTB amplifier…
42396 1: 100nA</description>
42402 …<description>Re-direct the CTB IPTAT output current. This can be used to reduce amplifier bias gli…
42406 …n be disabled and therefore the corresponding Opamp<n>.IZTAT/IPTAT will be HiZ.</description>
42412 <description>iztat current select control</description>
42418 <description>Use 250nA IZTAT from SRSS</description>
42423 <description>Use locally generated 250nA</description>
42430 … <description>CTBm charge pump clock source select. This field has nothing to do with the AREF.
42432 1: Use one of the CLK_PERI dividers</description>
42438 <description>bandgap voltage select control</description>
42444 <description>Use 0.8V Vref from SRSS</description>
42449 <description>Use locally generated Vref</description>
42454 <description>Use externally supplied Vref (aref_ext_vref)</description>
42461 … <description>AREF DeepSleep Operation Modes (only applies if DEEPSLEEP_ON = 1)</description>
42467 <description>All blocks 'OFF' in DeepSleep</description>
42472 …<description>IPTAT bias generator 'ON' in DeepSleep (used for fast AREF wakeup only: IPTAT outputs…
42477 …<description>IPTAT bias generator and outputs 'ON' in DeepSleep (used for biasing the CTBm with a …
42479 …uires that the CTB_IPTAT_REDIRECT be set if the CTBm opamp is to operate in DeepSleep</description>
42484 …description>IPTAT, VREF, and IZTAT generators 'ON' in DeepSleep. This mode provides identical AREF…
42491 <description>- 0: AREF IP disabled/off during DeepSleep power mode
42492 - 1: AREF IP remains enabled during DeepSleep power mode (if ENABLED=1)</description>
42498 <description>Disable AREF</description>
42507 <description>VREF Trim bits</description>
42516 <description>N/A</description>
42524 <description>VREF Trim bits</description>
42533 <description>N/A</description>
42541 <description>VREF Trim bits</description>
42550 <description>N/A</description>
42558 <description>VREF Trim bits</description>
42567 <description>Obsolete</description>
42575 <description>IZTAT Trim bits</description>
42584 <description>N/A</description>
42592 <description>IZTAT Trim bits</description>
42601 <description>IZTAT temperature correction trim (RMB)
42605 As this is a Risk Mitigation Register, it should be loaded with 0x08.</description>
42613 <description>IPTAT Trim bits</description>
42622 <description>IPTAT trim
42624 0xF : Maximum IPTAT current (~350nA at room)</description>
42630 <description>CTMB PTAT Current Trim
42632 0xF : Maximum CTMB IPTAT Current (~1.1uA)</description>
42640 <description>ICTAT Trim bits</description>
42649 <description>ICTAT trim
42651 0x0F : Maximum ICTAT current (~350nA at room)</description>
42661 <description>I2S registers</description>
42672 <description>Control</description>
42681 <description>Enables the I2S TX component:
42683 '1': Enabled.</description>
42689 <description>Enables the I2S RX component:
42691 '1': Enabled.</description>
42699 <description>Clock control</description>
42708 <description>Frequency divisor for generating I2S clock frequency.
42716 '63': 64 x</description>
42722 <description>Selects clock to be used by I2S:
42724 '1': External clock ('clk_i2s_if')</description>
42732 <description>Command</description>
42741 <description>Transmitter enable:
42743 '1': Enabled.</description>
42749 <description>Pause enable:
42751 '1': Enabled ('0' data is sent over I2S, instead of TX FIFO data).</description>
42757 <description>Receiver enable:
42759 '1': Enabled.</description>
42767 <description>Trigger control</description>
42776 … <description>Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission
42778 '1': Enabled.</description>
42784 … <description>Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception
42786 '1': Enabled.</description>
42794 <description>Transmitter control</description>
42803 …<description>Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX …
42813 (Note: This bit is connected to AR38U12.TX_CFG.TX_BCLKINV)</description>
42819 … <description>SDO transmitted at SCK falling edge when TX_CTL.SCKI_POL=0</description>
42824 … <description>SDO transmitted at SCK rising edge when TX_CTL.SCKI_POL=0</description>
42831 <description>Specifies number of channels per frame:
42834 (Note: These bits are connected to AR38U12.TX_CFG.TX_CHSET)</description>
42840 <description>1 channel</description>
42845 <description>2 channels</description>
42850 <description>3 channels</description>
42855 <description>4 channels</description>
42860 <description>5 channels</description>
42865 <description>6 channels</description>
42870 <description>7 channels</description>
42875 <description>8 channels</description>
42882 <description>Set interface in master or slave mode:
42884 (Note: This bit is connected to AR38U12.TX_CFG.TX_MS)</description>
42890 <description>Slave</description>
42895 <description>Master</description>
42902 <description>Select I2S, left-justified or TDM:
42904 (Note: These bits are connected to AR38U12.TX_CFG.TX_I2S_MODE)</description>
42910 <description>Left Justified</description>
42915 <description>I2S mode</description>
42920 <description>TDM mode A, the 1st Channel align to WSO
42921 Rising Edge</description>
42926 <description>TDM mode B, the 1st Channel align to WSO
42927 Rising edge with1 SCK Delay</description>
42934 <description>Set WS pulse width in TDM mode:
42937 Note: When not TDM mode, must be '1'.</description>
42943 <description>Pulse width is 1 SCK period</description>
42948 <description>Pulse width is 1 channel length</description>
42955 <description>Set overhead value:
42958 (Note: This bit is connected to AR38U12.TX_CFG.TX_OVHDATA)</description>
42964 <description>Set watchdog for 'tx_ws_in':
42966 '1': Enabled.</description>
42972 <description>Channel length in number of bits:
42977 (Note: These bits are connected to AR38U12.TX_CFG.TX_CHLEN)</description>
42983 <description>8-bit</description>
42988 <description>16-bit</description>
42993 <description>18-bit</description>
42998 <description>20-bit</description>
43003 <description>24-bit</description>
43008 <description>32-bit</description>
43015 <description>Word length in number of bits:
43020 (Note: These bits are connected to AR38U12.TX_CFG.TX_IWL)</description>
43026 <description>8-bit</description>
43031 <description>16-bit</description>
43036 <description>18-bit</description>
43041 <description>20-bit</description>
43046 <description>24-bit</description>
43051 <description>32-bit</description>
43058 <description>TX master bit clock polarity.
43061 …nsmitter is in master mode, serial data is transmitted from the rising bit clock edge</description>
43067 <description>TX slave bit clock polarity.
43068 … signal is not affected by this bit setting. See TX_CTL.B_CLOCK_INV for more details.</description>
43076 <description>Transmitter watchdog</description>
43085 …description>Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is dis…
43093 <description>Receiver control</description>
43102 …<description>Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master…
43112 (Note: This bit is connected to AR38U12.TX_CFG.RX_BCLKINV)</description>
43118 <description>SDI received at SCK rising edge when RX_CTL.SCKO_POL=0</description>
43123 <description>SDI received at SCK falling edge when RX_CTL.SCKO_POL=0</description>
43130 <description>Specifies number of channels per frame:
43133 (Note: These bits are connected to AR38U12.RX_CFG.RX_CHSET)</description>
43139 <description>1 channel</description>
43144 <description>2 channels</description>
43149 <description>3 channels</description>
43154 <description>4 channels</description>
43159 <description>5 channels</description>
43164 <description>6 channels</description>
43169 <description>7 channels</description>
43174 <description>8 channels</description>
43181 <description>Set interface in master or slave mode:
43183 (Note: This bit is connected to AR38U12.TX_CFG.RX_MS)</description>
43189 <description>Slave</description>
43194 <description>Master</description>
43201 <description>Select I2S, left-justified or TDM:
43203 (Note: These bits are connected to AR38U12.RX_CFG.RX_I2S_MODE)</description>
43209 <description>Left Justified</description>
43214 <description>I2S mode</description>
43219 <description>TDM mode A, the 1st Channel align to WSO
43220 Rising Edge</description>
43225 <description>TDM mode B, the 1st Channel align to WSO
43226 Rising edge with1 SCK Delay</description>
43233 <description>Set WS pulse width in TDM mode:
43236 Note: When not TDM mode, must be '1'.</description>
43242 <description>Pulse width is 1 SCK period</description>
43247 <description>Pulse width is 1 channel length</description>
43254 <description>Set watchdog for 'rx_ws_in'
43256 '1': Enabled.</description>
43262 <description>Channel length in number of bits:
43267 (Note: These bits are connected to AR38U12.RX_CFG.RX_CHLEN)</description>
43273 <description>8-bit</description>
43278 <description>16-bit</description>
43283 <description>18-bit</description>
43288 <description>20-bit</description>
43293 <description>24-bit</description>
43298 <description>32-bit</description>
43305 <description>Word length in number of bits:
43310 (Note: These bits are connected to AR38U12.RX_CFG.RX_IWL)</description>
43316 <description>8-bit</description>
43321 <description>16-bit</description>
43326 <description>18-bit</description>
43331 <description>20-bit</description>
43336 <description>24-bit</description>
43341 <description>32-bit</description>
43348 …<description>When reception word length is shorter than the word length of RX_FIFO_RD, extension m…
43350 …SB word is '1', then it is extended by '1', if MSB is '0' then it is extended by '0')</description>
43356 <description>RX master bit clock polarity.
43357 …) signal is not affected by this bit setting.See RX_CTL.B_CLOCK_INV for more details.</description>
43363 <description>RX slave bit clock polarity.
43366 … When receiver is in slave mode, serial data is sampled on the falling bit clock edge</description>
43374 <description>Receiver watchdog</description>
43383 …description>Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is dis…
43391 <description>TX FIFO control</description>
43400 …<description>Trigger level. When the TX FIFO has less entries than the number of this field, a tra…
43406 …description>When '1', the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for a…
43412 …description>When '1', hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not …
43420 <description>TX FIFO status</description>
43429 …<description>Number of entries in the TX FIFO. The field value is in the range [0, 256].</descript…
43435 …description>TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.Th…
43441 …description>TX FIFO write pointer: FIFO location at which a new data frame is written by the host.…
43449 <description>TX FIFO write</description>
43458 … <description>Data written into the TX FIFO. Behavior is similar to that of a PUSH operation.
43459 Note: Don't access to this register while TX_FIFO_CTL.CLEAR is '1'.</description>
43467 <description>RX FIFO control</description>
43476 …<description>Trigger level. When the RX FIFO has more entries than the number of this field, a rec…
43477 …mode (RX_CTL.I2S_MODE = '2' or '3'), it can configure up to [256 - (RX_CTL.CH_NR+2)].</description>
43483 …description>When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for a…
43489 …description>When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the R…
43497 <description>RX FIFO status</description>
43506 …<description>Number of entries in the RX FIFO. The field value is in the range [0, 256].</descript…
43512 …description>RX FIFO read pointer: FIFO location from which a data frame is read by the host. This …
43518 …description>RX FIFO write pointer: FIFO location at which a new data frame is written by the hardw…
43526 <description>RX FIFO read</description>
43535 …<description>Data read from the RX FIFO. Reading a data frame will remove the data frame from the …
43538 …id after CMD.RX_START is set '1'. Therefore we recommend software discard those data.</description>
43546 <description>RX FIFO silent read</description>
43555 …<description>Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from …
43558 …id after CMD.RX_START is set '1'. Therefore we recommend software discard those data.</description>
43566 <description>Interrupt register</description>
43575 …<description>Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL…
43581 <description>TX FIFO is not full.</description>
43587 <description>TX FIFO is empty; i.e. it has 0 entries.</description>
43593 <description>Attempt to write to a full TX FIFO.</description>
43599 …<description>Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer …
43605 <description>Triggers (sets to '1') when the Tx watchdog event occurs.</description>
43611 …<description>More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL…
43617 <description>RX FIFO is not empty.</description>
43623 <description>RX FIFO is full.</description>
43629 <description>Attempt to write to a full RX FIFO.</description>
43635 <description>Attempt to read from an empty RX FIFO.</description>
43641 <description>Triggers (sets to '1') when the Rx watchdog event occurs.</description>
43649 <description>Interrupt set register</description>
43658 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
43664 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
43670 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
43676 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
43682 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
43688 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
43694 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
43700 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
43706 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
43712 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
43718 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
43724 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
43732 <description>Interrupt mask register</description>
43741 … <description>Mask bit for corresponding bit in interrupt request register.</description>
43747 … <description>Mask bit for corresponding bit in interrupt request register.</description>
43753 … <description>Mask bit for corresponding bit in interrupt request register.</description>
43759 … <description>Mask bit for corresponding bit in interrupt request register.</description>
43765 … <description>Mask bit for corresponding bit in interrupt request register.</description>
43771 … <description>Mask bit for corresponding bit in interrupt request register.</description>
43777 … <description>Mask bit for corresponding bit in interrupt request register.</description>
43783 … <description>Mask bit for corresponding bit in interrupt request register.</description>
43789 … <description>Mask bit for corresponding bit in interrupt request register.</description>
43795 … <description>Mask bit for corresponding bit in interrupt request register.</description>
43801 … <description>Mask bit for corresponding bit in interrupt request register.</description>
43807 … <description>Mask bit for corresponding bit in interrupt request register.</description>
43815 <description>Interrupt masked register</description>
43824 <description>Logical and of corresponding request and mask bits.</description>
43830 <description>Logical and of corresponding request and mask bits.</description>
43836 <description>Logical and of corresponding request and mask bits.</description>
43842 <description>Logical and of corresponding request and mask bits.</description>
43848 <description>Logical and of corresponding request and mask bits.</description>
43854 <description>Logical and of corresponding request and mask bits.</description>
43860 <description>Logical and of corresponding request and mask bits.</description>
43866 <description>Logical and of corresponding request and mask bits.</description>
43872 <description>Logical and of corresponding request and mask bits.</description>
43878 <description>Logical and of corresponding request and mask bits.</description>
43884 <description>Logical and of corresponding request and mask bits.</description>
43890 <description>Logical and of corresponding request and mask bits.</description>
43900 <description>PDM registers</description>
43911 <description>Control</description>
43920 <description>Right channel PGA gain:
43926 (Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_R)</description>
43932 <description>Left channel PGA gain:
43938 (Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_L)</description>
43944 <description>Soft mute function to mute the volume smoothly
43947 (Note: This bit is connected to AR36U12.PDM_CORE_CFG.SOFT_MUTE)</description>
43953 <description>Set fine gain step for smooth PGA or Soft-Mute attenuation transition.
43956 (Note: This bit is connected to AR36U12.PDM_CORE2_CFG.SEL_STEP)</description>
43962 <description>Enables the PDM component:
43964 '1': Enabled.</description>
43972 <description>Clock control</description>
43981 <description>PDM CLK (FPDM_CLK) (1st divider):
43984 Note: configure a frequency of PDM CLK as lower than or equal 50MHz with this divider.</description>
43990 <description>Divide by 1</description>
43995 <description>Divide by 2 (no 50 percent duty cycle)</description>
44000 <description>Divide by 3 (no 50 percent duty cycle)</description>
44005 <description>Divide by 4 (no 50 percent duty cycle)</description>
44012 <description>MCLKQ divider (2nd divider)
44015 AR36U12.PDM_CORE2_CFG.DIV_MCLKQ)</description>
44021 <description>Divide by 1</description>
44026 <description>Divide by 2 (no 50 percent duty cycle)</description>
44031 <description>Divide by 3 (no 50 percent duty cycle)</description>
44036 <description>Divide by 4 (no 50 percent duty cycle)</description>
44043 <description>PDM CKO (FPDM_CKO) clock divider (3rd divider):
44049 AR36U12.PDM_CORE_CFG.MCLKDIV)</description>
44055 … <description>SINC Decimation Rate. For details, see the data sheet provided by Archband.
44057 (Note: These bits are connected to AR36U12.PDM_CORE_CFG.SINC_RATE)</description>
44065 <description>Mode control</description>
44074 <description>Specifies PCM output channels as mono or stereo:
44076 (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_CHSET)</description>
44082 <description>Channel disabled</description>
44087 <description>Mono left channel enable</description>
44092 <description>Mono right channel enable</description>
44097 <description>Stereo channel enable</description>
44104 <description>Input data L/R channel swap:
44107 (Note: This bit is connected to AR36U12.PDM_CORE_CFG.LRSWAP)</description>
44113 <description>Set time step for gain change during PGA or soft mute operation in
44115 (Note: These bits are connected to AR36U12.PDM_CORE_CFG.S_CYCLES)</description>
44121 <description>64steps</description>
44126 <description>96steps</description>
44131 <description>128steps</description>
44136 <description>160steps</description>
44141 <description>192steps</description>
44146 <description>256steps</description>
44151 <description>384steps</description>
44156 <description>512steps</description>
44163 …<description>Phase difference from the rising edge of internal sampler clock (CLK_IS) to that of P…
44165 (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PDMCKO_DLY)</description>
44171 <description>CLK_IS is 3*PDM_CLK period early</description>
44176 <description>CLK_IS is 2*PDM_CLK period early</description>
44181 <description>CLK_IS is 1*PDM_CLK period early</description>
44186 <description>CLK_IS is the same as PDM_CKO</description>
44191 <description>CLK_IS is 1*PDM_CLK period late</description>
44196 <description>CLK_IS is 2*PDM_CLK period late</description>
44201 <description>CLK_IS is 3*PDM_CLK period late</description>
44206 <description>CLK_IS is 4*PDM_CLK period late</description>
44213 <description>Adjust high pass filter coefficients.
44215 (Note: These bits are connected to AR36U12.PDM_CORE_CFG.HPGAIN)</description>
44221 <description>Enable high pass filter (active low)
44224 (Note: This bit is connected to AR36U12.PDM_CORE_CFG.ADCHPD)</description>
44232 <description>Data control</description>
44241 <description>PCM Word Length in number of bits:
44243 (Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_IWL)</description>
44249 <description>16-bit</description>
44254 <description>18-bit</description>
44259 <description>20-bit</description>
44264 <description>24-bit</description>
44271 …<description>When reception word length is shorter than the word length of RX_FIFO_RD, extension m…
44273 …SB word is '1', then it is extended by '1', if MSB is '0' then it is extended by '0')</description>
44281 <description>Command</description>
44290 <description>Enable data streaming flow:
44293 (Note: This bit is connected to AR36U12.PDM_CORE_CFG.PDMA_EN)</description>
44301 <description>Trigger control</description>
44310 <description>Trigger output ('tr_pdm_rx_req') enable for requests of DMA transfer
44312 '1': Enabled.</description>
44320 <description>RX FIFO control</description>
44329 …<description>Trigger level. When the RX FIFO has more entries than the number of this field, a rec…
44330 …H_SET = '1' or '2'), up to 253 in Stereo channel enabled (MODE_CTL.PCM_CH_SET = '3').</description>
44336 …description>When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for a…
44342 …description>When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the R…
44350 <description>RX FIFO status</description>
44359 …<description>Number of entries in the RX FIFO. The field value is in the range [0, 255]. When this…
44365 …description>RX FIFO read pointer: RX FIFO location from which a data frame is read by the host.Thi…
44371 …description>RX FIFO write pointer: RX FIFO location at which a new data frame is written by the ha…
44379 <description>RX FIFO read</description>
44388 …<description>Data read from the RX FIFO. Reading a data frame will remove the data frame from the …
44389 Note: Don't access to this bit while RX_FIFO_CTL.CLEAR is '1'.</description>
44397 <description>RX FIFO silent read</description>
44406 …<description>Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from …
44407 Note: Don't access to this bit while RX_FIFO_CTL.CLEAR is '1'.</description>
44415 <description>Interrupt register</description>
44424 …<description>More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTL.…
44430 <description>RX FIFO is not empty.</description>
44436 <description>Attempt to write to a full RX FIFO</description>
44442 <description>Attempt to read from an empty RX FIFO</description>
44450 <description>Interrupt set register</description>
44459 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
44465 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
44471 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
44477 … <description>Write with '1' to set corresponding bit in interrupt request register.</description>
44485 <description>Interrupt mask register</description>
44494 … <description>Mask bit for corresponding bit in interrupt request register.</description>
44500 … <description>Mask bit for corresponding bit in interrupt request register.</description>
44506 … <description>Mask bit for corresponding bit in interrupt request register.</description>
44512 … <description>Mask bit for corresponding bit in interrupt request register.</description>
44520 <description>Interrupt masked register</description>
44529 <description>Logical and of corresponding request and mask bits.</description>
44535 <description>Logical and of corresponding request and mask bits.</description>
44541 <description>Logical and of corresponding request and mask bits.</description>
44547 <description>Logical and of corresponding request and mask bits.</description>