Searched +full:cs1 +full:- +full:freq (Results 1 – 3 of 3) sorted by relevance
3 # SPDX-License-Identifier: Apache-2.07 compatible: "microchip,xec-qmspi-ldma"9 include: [spi-controller.yaml, pinctrl-device.yaml]30 pinctrl-0:33 pinctrl-names:39 QMSPI data lines 1, 2, or 4. 1 data line is full-duplex40 MOSI and MISO or half-duplex on MOSI only. Lines set to 242 Defaults to 1 for full duplex driver's support for full-duplex spi.44 - 145 - 2[all …]
5 * SPDX-License-Identifier: Apache-2.017 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>27 /* SAF EC Portal read/write flash access limited to 1-64 bytes */61 * Delay before first Poll-1 command after suspend in 20 ns units99 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()107 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()109 regs->SAF_CS1_CFG_P2M = val; in mchp_saf_poll2_mask_wr()117 regs->SAF_CS0_CM_PRF = val; in mchp_saf_cm_prefix_wr()119 regs->SAF_CS1_CM_PRF = val; in mchp_saf_cm_prefix_wr()128 * Each protection region is composed of 4 32-bit registers[all …]
5 * SPDX-License-Identifier: Apache-2.020 /* SAF EC Portal read/write flash access limited to 1-64 bytes */44 * Delay before first Poll-1 command after suspend in 20 ns units75 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()83 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()85 regs->SAF_CS1_CFG_P2M = val; in mchp_saf_poll2_mask_wr()93 regs->SAF_CS0_CM_PRF = val; in mchp_saf_cm_prefix_wr()95 regs->SAF_CS1_CM_PRF = val; in mchp_saf_cm_prefix_wr()105 return -ETIMEDOUT; in xec_saf_spin_yield()122 * Each protection region is composed of 4 32-bit registers[all …]
