| /Zephyr-latest/subsys/settings/src/ |
| D | settings_store.c | 27 void settings_src_register(struct settings_store *cs) in settings_src_register() argument
29 sys_slist_append(&settings_load_srcs, &cs->cs_next); in settings_src_register()
32 void settings_dst_register(struct settings_store *cs) in settings_dst_register() argument
34 settings_save_dst = cs; in settings_dst_register()
44 struct settings_store *cs; in settings_load_subtree() local
57 SYS_SLIST_FOR_EACH_CONTAINER(&settings_load_srcs, cs, cs_next) { in settings_load_subtree()
58 cs->cs_itf->csi_load(cs, &arg); in settings_load_subtree()
70 struct settings_store *cs; in settings_load_subtree_direct() local
84 SYS_SLIST_FOR_EACH_CONTAINER(&settings_load_srcs, cs, cs_next) { in settings_load_subtree_direct()
85 cs->cs_itf->csi_load(cs, &arg); in settings_load_subtree_direct()
[all …]
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| /Zephyr-latest/dts/bindings/spi/ |
| D | nxp,s32-spi.yaml | 17 num-cs:
37 spi-sck-cs-delay:
41 deactivating Chip Select at the stop of transfer. If CS remains
44 This value will affect to all inner CS signals of SPI module when active.
45 This value will not be applied for CS lines controlled by GPIO.
47 spi-cs-sck-delay:
51 of clock signal at the start of transfer. If CS remains asserted
54 This value will affect to all inner CS signals of SPI module when active.
55 This value will not be applied for CS lines controlled by GPIO.
57 spi-cs-cs-delay:
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| D | espressif,esp32-spi.yaml | 47 clk-as-cs:
50 Support to toggle the CS while the clock toggles
52 Output clock on CS line if CS is active
54 positive-cs:
56 description: Make CS positive during a transaction instead of negative
68 cs-setup-time:
74 cs-hold-time:
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| D | microchip,xec-qmspi.yaml | 48 description: Delay in system clocks from CS# assertion to first clock edge
53 description: Delay in system clocks from last clock edge to CS# de-assertion
58 description: Delay in system clocks from CS# de-assertion to driving HOLD# and WP#
63 description: Delay in system clocks from CS# de-assertion to CS# assertion
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| D | spi-controller.yaml | 21 cs-gpios:
26 corresponds to the child node that the CS gpio controls.
31 cs-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>,
48 GPIO flags GPIO_ACTIVE_LOW. Similarly, "spi-device@1" has CS GPIO
58 SPI controllers with dedicated CS pins do not need to define
59 the cs-gpios property.
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| D | microchip,xec-qmspi-ldma.yaml | 57 Delay in QMSPI main clocks from CS# assertion to first clock edge.
64 Delay in QMSPI main clocks from last clock edge to CS# de-assertion.
71 Delay in QMSPI main clocks from CS# de-assertion to driving HOLD#
78 Delay in QMSPI main clocks from CS# de-assertion to CS# assertion.
85 Allows different frequencies for CS#0 and CS1# devices. This applies
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| D | intel,penwell-spi.yaml | 15 cs-gpios:
18 pw,cs-mode:
27 pw,cs-output:
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| /Zephyr-latest/include/zephyr/bluetooth/ |
| D | cs.h | 14 * @brief LE Channel Sounding (CS)
15 * @defgroup bt_le_cs Channel Sounding (CS)
31 * @brief Macro for getting a specific channel bit in CS channel map
41 * @brief Macro for setting a specific channel bit value in CS channel map
65 /** Default CS settings in the local Controller */
67 /** Enable CS initiator role. */
69 /** Enable CS reflector role. */
75 * for all CS transmissions.
83 /** CS Test CS_SYNC Antenna Identifier */
91 /** CS SNR control options */
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| /Zephyr-latest/tests/drivers/spi/dt_spec/src/ |
| D | main.c | 21 LOG_DBG("spi_cs.config.cs.gpio.port = %p", spi_cs.config.cs.gpio.port); in ZTEST()
22 LOG_DBG("spi_cs.config.cs.gpio.pin = %u", spi_cs.config.cs.gpio.pin); in ZTEST()
26 zassert_equal(spi_cs.config.cs.gpio.port, DEVICE_DT_GET(DT_NODELABEL(test_gpio)), ""); in ZTEST()
27 zassert_equal(spi_cs.config.cs.gpio.pin, 0x10, ""); in ZTEST()
33 LOG_DBG("spi_no_cs.config.cs.gpio.port = %p", spi_no_cs.config.cs.gpio.port); in ZTEST()
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| /Zephyr-latest/subsys/bluetooth/host/ |
| D | hci_common.c | 45 struct bt_hci_evt_cmd_status *cs; in bt_hci_cmd_status_create() local
47 buf = bt_hci_evt_create(BT_HCI_EVT_CMD_STATUS, sizeof(*cs)); in bt_hci_cmd_status_create()
49 cs = net_buf_add(buf, sizeof(*cs)); in bt_hci_cmd_status_create()
50 cs->status = status; in bt_hci_cmd_status_create()
51 cs->ncmd = 1U; in bt_hci_cmd_status_create()
52 cs->opcode = sys_cpu_to_le16(op); in bt_hci_cmd_status_create()
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| /Zephyr-latest/samples/bluetooth/channel_sounding/ |
| D | README.rst | 12 The CS Test sample shows how to us the CS test command to override randomization of certain channel
16 The connected CS sample shows how to set up regular channel sounding procedures on a connection
57 Here is an example output from the connected CS sample:
70 CS capability exchange completed.
71 CS config creation complete. ID: 0
72 CS security enabled.
73 CS procedures enabled.
82 Found device with name CS Sample, connecting...
85 CS capability exchange completed.
86 CS config creation complete. ID: 0
[all …]
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| /Zephyr-latest/include/zephyr/devicetree/ |
| D | spi.h | 28 * SPI bus controllers use the "cs-gpios" property for configuring
36 * cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
50 * @return 1 if "spi" has a cs-gpios property, 0 otherwise
55 * @brief Number of chip select GPIOs in a SPI controller's cs-gpios property
61 * cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
75 * @return Logical length of spi's cs-gpios property, or 0 if "spi" doesn't
76 * have a cs-gpios property
88 * cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
130 * cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
157 * bus node's cs-gpios property has no pin cell.
[all …]
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| /Zephyr-latest/soc/nxp/s32/s32k1/ |
| D | soc.c | 31 if ((IP_WDOG->CS & WDOG_CS_CMD32EN_MASK) != 0U) { in z_arm_watchdog_init()
37 while (!(IP_WDOG->CS & WDOG_CS_ULK_MASK)) { in z_arm_watchdog_init()
42 IP_WDOG->CS = (uint32_t) ((IP_WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK; in z_arm_watchdog_init()
45 while (!(IP_WDOG->CS & WDOG_CS_RCS_MASK)) { in z_arm_watchdog_init()
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| /Zephyr-latest/tests/bluetooth/host/cs/bt_le_cs_parse_pct/ |
| D | CMakeLists.txt | 10 ${ZEPHYR_BASE}/tests/bluetooth/host/cs/mocks
14 add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/host/cs/mocks mocks)
22 ${ZEPHYR_BASE}/subsys/bluetooth/host/cs.c
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| /Zephyr-latest/tests/bluetooth/host/cs/bt_le_cs_step_data_parse/ |
| D | CMakeLists.txt | 10 ${ZEPHYR_BASE}/tests/bluetooth/host/cs/mocks
14 add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/host/cs/mocks mocks)
22 ${ZEPHYR_BASE}/subsys/bluetooth/host/cs.c
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| /Zephyr-latest/include/zephyr/arch/x86/ia32/ |
| D | exception.h | 22 * always operates at ring 0, only the EIP, CS and EFLAGS registers are pushed
48 unsigned int cs; member
56 uint32_t cs; member
59 /* These are only present if cs = USER_CODE_SEG */
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| /Zephyr-latest/tests/bluetooth/host/cs/bt_le_cs_set_valid_chmap_bits/ |
| D | CMakeLists.txt | 11 ${ZEPHYR_BASE}/tests/bluetooth/host/cs/mocks
15 add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/host/cs/mocks mocks)
23 ${ZEPHYR_BASE}/subsys/bluetooth/host/cs.c
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| /Zephyr-latest/soc/espressif/common/ |
| D | Kconfig.spiram | 153 menu "PSRAM clock and cs IO for ESP32-DOWD"
164 int "PSRAM CS IO number"
168 The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use
171 endmenu # PSRAM clock and cs IO for ESP32-DOWD
173 menu "PSRAM clock and cs IO for ESP32-D2WD"
184 int "PSRAM CS IO number"
191 endmenu # PSRAM clock and cs IO for ESP32-D2WD
193 menu "PSRAM clock and cs IO for ESP32-PICO"
196 int "PSRAM CS IO number"
200 The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
[all …]
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| /Zephyr-latest/drivers/fpga/ |
| D | fpga_ice40_bitbang.c | 22 * Note: When loading a bitstream, the iCE40 has a 'quirk' in that the CS
25 * CS polarity is normal (active low). Zephyr's SPI driver model currently
28 * The logical alternative would be to put the CS into GPIO mode, perform 3
29 * separate SPI transfers (inverting CS polarity as necessary) and then
82 volatile gpio_port_pins_t *clear, gpio_port_pins_t cs, in fpga_ice40_spi_send_data() argument
89 *clear |= cs; in fpga_ice40_spi_send_data()
113 *set |= cs; in fpga_ice40_spi_send_data()
126 gpio_port_pins_t cs; in fpga_ice40_load() local
146 cs = BIT(config->bus.config.cs.gpio.pin); in fpga_ice40_load()
167 gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH) || in fpga_ice40_load()
[all …]
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| /Zephyr-latest/drivers/spi/ |
| D | spi_b91.c | 47 /* disable hardware cs flow control */
52 /* loop through all cs pins (cs0..cs2) */ in spi_b91_hw_cs_disable()
54 /* get CS pin defined in device tree */ in spi_b91_hw_cs_disable()
57 /* if CS pin is defined in device tree */ in spi_b91_hw_cs_disable()
60 /* disable CS pin for PSPI */ in spi_b91_hw_cs_disable()
63 /* disable CS pin for MSPI */ in spi_b91_hw_cs_disable()
70 /* config cs flow control: hardware or software */
79 /* disable all hardware CS pins */ in spi_b91_config_cs()
92 /* loop through all cs pins: cs0, cs1 and cs2 */ in spi_b91_config_cs()
94 /* get cs pin defined in device tree */ in spi_b91_config_cs()
[all …]
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| /Zephyr-latest/soc/atmel/sam0/common/ |
| D | soc_samr3x_radio_off.c | 15 const struct gpio_dt_spec cs = GPIO_DT_SPEC_GET(DT_NODELABEL(sercom4), cs_gpios); in radio_off_setup() local
17 if (!gpio_is_ready_dt(&reset) || !gpio_is_ready_dt(&cs)) { in radio_off_setup()
26 ret = gpio_pin_configure_dt(&cs, GPIO_OUTPUT_INACTIVE); in radio_off_setup()
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| /Zephyr-latest/boards/shields/x_nucleo_idb05a1/doc/ |
| D | index.rst | 20 but CS and SCK signals are not the standard Arduino SPI_CS and SPI_SCK signals.
37 Also shield expects SPI CS to be available on Arduino pin A1 instead of usual
38 Arduino UNO R3 SPI CS D10.
39 This is not a problem as CS signal is software driven gpio on Arduino A1
40 see cs-gpios in x_nucleo_idb05a1.overlay
50 - CS: To use D10 instead of A1, remove R2 and add R7
55 The stm32mp157c_dk2 board is known to need those CS/IRQ pin modifications
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| /Zephyr-latest/boards/shields/x_nucleo_bnrg2a1/doc/ |
| D | index.rst | 20 but CS signal is not the standard Arduino SPI_CS signal.
33 Out of the box, X-NUCLEO-BNRG2A1 shield expects SPI CS to be available on
34 Arduino pin A1 instead of usual Arduino UNO R3 SPI CS D10.
35 This is not a problem as CS signal is software driven gpio on Arduino A1
36 see cs-gpios in x_nucleo_bnrg2a1.overlay
46 - CS: To use D1 instead of A1, unmount R76 and mount R86
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| /Zephyr-latest/samples/drivers/spi_bitbang/src/ |
| D | main.c | 23 struct spi_cs_control *cs) in test_basic_write_9bit_words() argument
30 config.cs = *cs; in test_basic_write_9bit_words()
50 struct spi_cs_control *cs) in test_9bit_loopback_partial() argument
57 config.cs = *cs; in test_9bit_loopback_partial()
89 void test_8bit_xfer(const struct device *dev, struct spi_cs_control *cs) in test_8bit_xfer() argument
96 config.cs = *cs; in test_8bit_xfer()
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| /Zephyr-latest/include/zephyr/arch/x86/intel64/ |
| D | syscall.h | 39 * loaded from LSTAR MSR, masks RFLAGS with the low 32 bits of EFER.SFMASK. CS
41 * for CS, +8 for SS)
43 * SYSRET loads RIP from RCX and RFLAGS from r11. CS and SS are set with
44 * values derived from STAR MSR bits 63:48 (+8 for CS, +16 for SS)
173 int cs; in arch_is_user_context() local
175 __asm__ volatile ("mov %%cs, %[cs_val]" : [cs_val] "=r" (cs)); in arch_is_user_context()
177 return (cs & 0x3) != 0; in arch_is_user_context()
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