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/Zephyr-latest/samples/subsys/pm/latency/
Dsample.yaml20 - "<inf> app: Setting latency constraint: 30ms"
28 - "<inf> dev_test: Adding latency constraint: 20ms"
29 - "<inf> app: Latency constraint changed: 20ms"
36 - "<inf> app: Updating latency constraint: 10ms"
37 - "<inf> app: Latency constraint changed: 10ms"
38 - "<inf> dev_test: Latency constraint changed: 10ms"
42 - "<inf> app: Updating latency constraint: 30ms"
43 - "<inf> app: Latency constraint changed: 20ms"
44 - "<inf> dev_test: Latency constraint changed: 20ms"
46 - "<inf> dev_test: Removing latency constraint"
[all …]
/Zephyr-latest/samples/subsys/pm/latency/src/
Dmain.c19 LOG_INF("Latency constraint changed: none"); in on_latency_changed()
21 LOG_INF("Latency constraint changed: %" PRId32 "ms", in on_latency_changed()
40 /* test without any latency constraint */ in main()
48 /* add an application level latency constraint */ in main()
49 LOG_INF("Setting latency constraint: 30ms"); in main()
52 /* test with an application level constraint */ in main()
60 /* open test device (adds its own latency constraint) */ in main()
72 /* update application level latency constraint */ in main()
73 LOG_INF("Updating latency constraint: 10ms"); in main()
84 /* restore application level latency constraint */ in main()
[all …]
Dtest.c23 LOG_INF("Latency constraint changed: none"); in on_latency_changed()
25 LOG_INF("Latency constraint changed: %" PRId32 "ms", in on_latency_changed()
34 LOG_INF("Adding latency constraint: 20ms"); in dev_test_open()
44 LOG_INF("Removing latency constraint"); in dev_test_close()
/Zephyr-latest/subsys/pm/policy/
Dpolicy_device_lock.c20 * @brief Synthesize the name of the object that holds a device pm constraint.
27 * @brief initialize a device pm constraint with information from devicetree.
70 * @brief Helper macro to initialize a pm state device constraint
80 * @brief Helper macro to initialize a pm state device constraint
/Zephyr-latest/lib/open-amp/
Dresource_table.h29 #define VRING_ALIGNMENT 16 /* fixed to match with Linux constraint */
/Zephyr-latest/drivers/serial/
Duart_ite_it8xxx2.c60 * can directly set the constraint for standby. in uart1_wui_isr()
80 * can directly set the constraint for standby. in uart2_wui_isr()
Duart_npcx.c825 * Set pm constraint to prevent the system enter suspend state within in uart_npcx_isr()
947 * Set pm constraint to prevent the system enter suspend state within in uart_npcx_rx_wk_isr()
Duart_mcux_lpuart.c182 * transmission completes. Set the power constraint, and enable in mcux_lpuart_poll_out()
304 * transmission is complete. Release pm constraint. in mcux_lpuart_irq_tx_disable()
Duart_stm32.c683 /* If an interrupt transmission is in progress, the pm constraint is already managed by the in uart_stm32_poll_out_visitor()
695 * constraint when done in uart_stm32_poll_out_visitor()
1251 * constraint will be released at the same time TC IT in uart_stm32_isr()
/Zephyr-latest/doc/services/pm/
Dsystem.rst68 pm_system_resume:e -> lock:e [constraint=false lhed="cluster_0"]
102 power savings, with the constraint that the sum of the minimum residency value (see
Ddevice_runtime.rst52 ACTIVE -> SUSPENDING [constraint=false]
53 SUSPENDING -> SUSPENDED [constraint=false];
Ddevice.rst310 .. _pm-device-constraint:
/Zephyr-latest/subsys/logging/frontends/
DKconfig82 Option can be enabled for memory constraint cases to remove all logging
/Zephyr-latest/tests/subsys/pm/power_states_api/src/
Dmain.c86 * state due the constraint set by `test_dev`. in ZTEST()
/Zephyr-latest/dts/bindings/sensor/
Dnxp,fxos8700-common.yaml119 time limit constraint specified by the PULSE_TMLT register, but the end
/Zephyr-latest/arch/xtensa/
DKconfig53 constraint of the vector table entry and moved the default
/Zephyr-latest/drivers/led_strip/
Dws2812_gpio.c48 * constraint in the below assembly.
/Zephyr-latest/arch/xtensa/core/
Dmmu.c109 * instruction fetches this produces a critical ordering constraint:
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/
Dtestcase.yaml3 # To reflect this constraint on such boards, a specific fixture "mco_sb_closed" is provided.
/Zephyr-latest/include/zephyr/pm/
Dpolicy.h33 * microseconds. SYS_FOREVER_US value lifts the latency constraint. Other values
/Zephyr-latest/subsys/debug/gdbstub/
Dgdbstub.c306 /* Read memory with alignment constraint */
445 /* Write memory with alignment constraint */
/Zephyr-latest/include/zephyr/audio/
Ddmic.h145 * CONSTRAINT: The LEFT and RIGHT channels of EACH PDM controller needs
/Zephyr-latest/boards/intel/socfpga_std/cyclonev_socdk/doc/
Dindex.rst126 * soc_system_timing.sdc : Synopsys Desing Constraint FILE.
/Zephyr-latest/drivers/entropy/
Dentropy_stm32.c424 * being populated. The ISR will release the constraint again when the in start_pool_filling()
/Zephyr-latest/include/zephyr/toolchain/
Dgcc.h512 * the value to ~(value). Thus "n"(~(value)) is set in operand constraint

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