Searched full:consecutively (Results 1 – 10 of 10) sorted by relevance
| /Zephyr-latest/dts/bindings/mbox/ |
| D | nxp,mbox-imx-mu.yaml | 17 Setting this value to N, will enable channels 0 to N-1, consecutively.
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| D | nxp,mbox-mailbox.yaml | 25 Setting this value to N, will enable channels 0 to N-1, consecutively.
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| D | nxp,s32-mru.yaml | 52 Setting this value to N, will enable channels 0 to N-1, consecutively.
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| /Zephyr-latest/soc/openisa/rv32m1/ |
| D | soc.h | 71 * - the INTMUX output IRQ numbers are arranged consecutively in rv32m1_intmux_channel()
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| /Zephyr-latest/drivers/ethernet/ |
| D | eth_xlnx_gem_priv.h | 552 /* The values of this enum are consecutively numbered */
567 /* The values of this enum are consecutively numbered */
582 /* The values of this enum are consecutively numbered */
604 /* The values of this enum are consecutively numbered */
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| /Zephyr-latest/tests/drivers/hwinfo/api/src/ |
| D | main.c | 67 "Two consecutively readings don't match"); in ZTEST()
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| /Zephyr-latest/drivers/sensor/ams/tsl2561/ |
| D | tsl2561.c | 157 /* Read data register's lower and upper bytes consecutively */ in tsl2561_sample_fetch()
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| /Zephyr-latest/doc/connectivity/networking/api/ |
| D | sockets.rst | 54 descriptors are small integers, consecutively assigned from zero, shared
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_mchp_xec_v2.c | 52 /* Each GPIO pin 32-bit control register located consecutively in memory */
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| /Zephyr-latest/drivers/ethernet/dwc_xgmac/ |
| D | eth_dwc_xgmac_priv.h | 683 /* The values of this enum are consecutively numbered */
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