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/Zephyr-latest/drivers/clock_control/
DKconfig.npcx1 # NPCX Clock controller driver configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 bool "NPCX clock controller driver"
11 Enable support for NPCX clock controller driver.
16 bool "Generate LFCLK by on-chip Crystal Oscillator"
18 When this option is enabled, the internal 32.768 KHz clock (LFCLK)
19 is generated by the on-chip Crystal Oscillator (XTOSC).
20 This includes an on-chip oscillator, to which an external crystal
24 bool "Indicates that the clock controller supports APB4 bus"
30 bool "Indicates that the clock controller supports FIU1 bus"
DKconfig.npcm1 # NPCM Clock controller driver configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 bool "NPCM clock controller driver"
11 Enable support for NPCM clock controller driver.
DKconfig.numaker1 # NuMaker clock controller driver configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 bool "NuMaker system clock controller driver"
11 Enable support for NuMaker system clock controller driver
DKconfig1 # Clock controller driver configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 # Clock controller drivers
10 bool "Clock controller drivers"
12 Enable support for hardware clock controller. Such hardware can
13 provide clock for other subsystem, and thus can be also used for
14 power efficiency by controlling their clock. Note that this has
20 int "Clock control init priority"
23 Clock control driver device initialization priority.
26 module-str = clock control
/Zephyr-latest/dts/bindings/clock/
Draspberrypi,pico-clock-controller.yaml1 # Copyright (c) 2022 Andrei-Edward Popa
2 # SPDX-License-Identifier: Apache-2.0
4 description: Raspberry Pi Pico clock controller node
6 compatible: "raspberrypi,pico-clock-controller"
8 include: [base.yaml, clock-controller.yaml, pinctrl-device.yaml]
14 "#clock-cells":
17 clock-cells:
18 - clk-id
Daspeed,ast10x0-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Aspeed AST10X0 Clock Controller
6 compatible: "aspeed,ast10x0-clock"
8 include: [clock-controller.yaml, base.yaml]
11 "#clock-cells":
14 clock-cells:
15 - clk_id
Datmel,sam-pmc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Atmel Power Management Controller (PMC)
7 The Power Management Controller (PMC) optimizes power consumption by
9 the clock inputs to many of the peripherals and the processor.
16 clocks = <&pmc PMC_TYPE_PERIPHERAL p-id>;
20 In this example the clock-type was defined as PMC_TYPE_PERIPHERAL and the
21 peripheral-id was defined as p-id. The p-id number should be consulted on
24 NOTE: The predefined clock type cell is defined at
27 The clock-type constants are:
34 compatible: "atmel,sam-pmc"
[all …]
Dst,stm32-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-prescaler = <1>;
[all …]
Dintel,agilex-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Agilex clock controller node
6 compatible: "intel,agilex-clock"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
17 clock-cells:
18 - clkid
Dintel,agilex5-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Agilex5 clock controller node
6 compatible: "intel,agilex5-clock"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
17 clock-cells:
18 - clkid
Dnuvoton,numaker-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Nuvoton NuMaker Peripheral Clock Controller (PCC)
6 compatible: "nuvoton,numaker-pcc"
8 include: [clock-controller.yaml, base.yaml]
11 "#clock-cells":
14 clock-cells:
15 - clock-module-index # Same as u32ModuleIdx on invoking BSP CLK driver CLK_SetModuleClock()
16 - clock-source # Same as u32ClkSrc on invoking BSP CLK driver CLK_SetModuleClock()
17 - clock-divider # Same as u32ClkDiv on invoking BSP CLK driver CLK_SetModuleClock()
Dnxp,imx-anatop.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: i.MX ANATOP (Analog Clock Controller Module) IP node
6 compatible: "nxp,imx-anatop"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
18 description: Number of items to expect in a clock specifier
20 "#pll-clock-cells":
26 clock-cells:
27 - name
28 - offset
[all …]
Dambiq,clkctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Ambiq Apollo Series SoC Clock Controller
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
11 clock-frequency:
13 description: output clock frequency (Hz)
16 pinctrl-0:
19 pinctrl-names:
22 "#clock-cells":
Dnxp,imx-ccm.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: i.MX CCM (Clock Controller Module) IP node
6 compatible: "nxp,imx-ccm"
8 include: [clock-controller.yaml, base.yaml]
11 "#clock-cells":
14 clock-cells:
15 - name
16 - offset
17 - bits
Datmel,samc2x-gclk.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Atmel SAMC2x Generic Clock Controller (GCLK)
6 compatible: "atmel,samc2x-gclk"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
17 clock-cells:
18 - periph_ch
Datmel,samd2x-gclk.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Atmel SAMD2x Generic Clock Controller (GCLK)
6 compatible: "atmel,samd2x-gclk"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
17 clock-cells:
18 - clkctrl_id
Datmel,samd5x-gclk.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Atmel SAMD5x Generic Clock Controller (GCLK)
6 compatible: "atmel,samd5x-gclk"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
17 clock-cells:
18 - periph_ch
Datmel,saml2x-gclk.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Atmel SAML2x Generic Clock Controller (GCLK)
6 compatible: "atmel,saml2x-gclk"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
17 clock-cells:
18 - periph_ch
/Zephyr-latest/include/zephyr/devicetree/
Dclocks.h9 * SPDX-License-Identifier: Apache-2.0
20 * @defgroup devicetree-clocks Devicetree Clocks API
26 * @brief Test if a node has a clocks phandle-array property at a given index
28 * This expands to 1 if the given index is valid clocks property phandle-array index.
33 * n1: node-1 {
37 * n2: node-2 {
49 * @param idx index of a clocks property phandle-array whose existence to check
56 * @brief Test if a node has a clock-names array property holds a given name
58 * This expands to 1 if the name is available as clocks-name array property cell.
63 * n1: node-1 {
[all …]
/Zephyr-latest/dts/riscv/wch/
Dch32v00x.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/clock/ch32v00x-clocks.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "wch,qingke-v2";
25 clock-frequency = <DT_FREQ_M(48)>;
[all …]
/Zephyr-latest/dts/bindings/phy/
Drenesas,ra-usbphyc.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Renesas RA USBHS internal PHY controller
6 compatible: "renesas,ra-usbphyc"
8 include: phy-controller.yaml
11 clock:
14 Clock source for PHY clock in case internal clock is using
16 phys-clock-src:
19 - "internal"
20 - "xtal"
22 Select clock source for PHY clock as XTAL or use internal clock
[all …]
/Zephyr-latest/dts/bindings/test/
Dvnd,clock.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Test Clock Controller
6 compatible: "vnd,clock"
8 include: [clock-controller.yaml, base.yaml]
11 "#clock-cells":
14 clock-cells:
15 - bus
16 - bits
/Zephyr-latest/dts/riscv/microchip/
Dmpfs.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
18 clock-frequency = <0>;
23 hlic0: interrupt-controller {
24 compatible = "riscv,cpu-intc";
25 #address-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/st/wb0/
Dstm32wb0.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/pwm/pwm.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/clock/stm32wb0_clock.h>
13 #include <zephyr/dt-bindings/reset/stm32wb0_reset.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
25 zephyr,flash-controller = &flash;
[all …]
/Zephyr-latest/dts/bindings/i3c/
Dnxp,mcux-i3c.yaml4 # SPDX-License-Identifier: Apache-2.0
6 description: NXP MCUX I3C controller
8 compatible: "nxp,mcux-i3c"
10 include: [i3c-controller.yaml, pinctrl-device.yaml]
19 i3c-od-scl-hz:
22 Open Drain Frequency for the I3C controller. When undefined, use
23 the controller default or as specified by the I3C specification.
25 clk-divider:
27 description: Main clock divider for I3C
30 clk-divider-tc:
[all …]

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