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Searched +full:clkout +full:- +full:source (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/dts/bindings/clock/
Dnxp,kinetis-ke1xf-sim.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-ke1xf-sim"
14 clkout-source:
16 description: clkout clock source
18 clkout-divider:
20 description: clkout divider
Dnxp,kinetis-sim.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-sim"
14 pllfll-select:
19 er32k-select:
24 clkout-source:
26 description: clkout clock source
28 clkout-divider:
30 description: clkout divider
32 "#clock-cells":
36 clock-cells:
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/Zephyr-latest/drivers/clock_control/
Dclock_control_lpc11u6x.h4 * SPDX-License-Identifier: Apache-2.0
70 volatile uint32_t sys_pll_clk_sel; /* System PLL clock source */
71 volatile uint32_t sys_pll_clk_uen; /* System PLL source update */
72 volatile uint32_t usb_pll_clk_sel; /* USB PLL clock source */
73 volatile uint32_t usb_pll_clk_uen; /* USB PLL clock source
86 volatile uint32_t frg_clk_div; /* USART 1-4 fractional baud
94 volatile uint32_t clk_out_sel; /* CLKOUT source select */
95 volatile uint32_t clk_out_uen; /* CLKOUT source update */
96 volatile uint32_t clk_out_div; /* CLKOUT divider */
98 volatile uint32_t uart_frg_div; /* USART1-4 fractional
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Dclock_control_mcux_scg.c2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
8 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/clock/kinetis_scg.h>
119 return -EINVAL; in mcux_scg_get_rate()
140 #error Unsupported SCG clkout clock source in mcux_scg_init()
/Zephyr-latest/dts/bindings/rtc/
Dnxp,pcf8523.yaml1 # Copyright (c) 2019-2023 Henrik Brix Andersen <henrik@brixandersen.dk>
2 # SPDX-License-Identifier: Apache-2.0
9 - name: rtc-device.yaml
10 - name: i2c-device.yaml
11 - name: pm.yaml
12 property-allowlist:
13 - wakeup-source
16 quartz-load-femtofarads:
19 - 7000
20 - 12500
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/Zephyr-latest/boards/nxp/twr_ke18f/
Dtwr_ke18f.dts2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/clock/kinetis_scg.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include "twr_ke18f-pinctrl.dtsi"
13 #include <zephyr/dt-bindings/input/input-event-codes.h>
27 pwm-led0 = &orange_pwm_led;
28 pwm-led1 = &yellow_pwm_led;
29 pwm-led2 = &green_pwm_led;
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/Zephyr-latest/drivers/rtc/
Drtc_pcf8523.c2 * Copyright (c) 2019-2023 Henrik Brix Andersen <henrik@brixandersen.dk>
4 * SPDX-License-Identifier: Apache-2.0
108 /* The PCF8523 only supports two-digit years, calculate offset to use */
109 #define PCF8523_YEARS_OFFSET (2000 - 1900)
114 /* Helper macro to guard int1-gpios related code */
152 const struct pcf8523_config *config = dev->config; in pcf8523_read_regs()
155 err = i2c_write_read_dt(&config->i2c, &addr, sizeof(addr), buf, len); in pcf8523_read_regs()
171 const struct pcf8523_config *config = dev->config; in pcf8523_write_regs()
178 err = i2c_write_dt(&config->i2c, block, sizeof(block)); in pcf8523_write_regs()
219 const struct pcf8523_config *config = dev->config; in pcf8523_int1_enable_unlocked()
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/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dsoc.c2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
159 /* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */ in usb_device_clock_init()
176 /* Wait until host_needclk de-asserts */ in usb_device_clock_init()
177 while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK) { in usb_device_clock_init()
183 USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; in usb_device_clock_init()
203 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; in soc_reset_hook()
220 /* Configure FRO clock source */ in rt5xx_clock_init()
230 * clock source to avoid instruction/data fetch issue when updating PLL and Main in rt5xx_clock_init()
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/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dboard.c3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
61 SYSCON->AHBCLKCTRLSET[0] |= SYSCON_AHBCLKCTRL0_FLEXSPI_MASK; in enable_cache64()
64 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK; in enable_cache64()
65 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK; in enable_cache64()
67 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) { in enable_cache64()
70 CACHE64_CTRL0->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK | CACHE64_CTRL_CCR_ENCACHE_MASK); in enable_cache64()
76 CACHE64_POLSEL0->REG0_TOP = 0x7FFC00; in enable_cache64()
77 CACHE64_POLSEL0->REG1_TOP = 0x0; in enable_cache64()
78 CACHE64_POLSEL0->POLSEL = in enable_cache64()
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/Zephyr-latest/doc/releases/
Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
82 image states). Use of a truncated hash or non-sha256 hash will still work
88 registration function at boot-up. If applications register this then
93 application code, these will now automatically be registered at boot-up (this
129 This may cause out-of-tree scripts or commands to fail if they have relied
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