Searched full:clk_lse (Results 1 – 25 of 89) sorted by relevance
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| /Zephyr-latest/boards/arduino/portenta_h7/ |
| D | arduino_portenta_h7_stm32h747xx_m7_4_10_0.overlay | 7 &clk_lse {
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/ |
| D | core_init.overlay | 27 &clk_lse {
72 &clk_lse {
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| /Zephyr-latest/samples/boards/st/mco/boards/ |
| D | nucleo_u5a5zj_q.overlay | 2 &clk_lse {
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| D | stm32f746g_disco.overlay | 2 &clk_lse {
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| /Zephyr-latest/samples/boards/st/power_mgmt/serial_wakeup/boards/ |
| D | nucleo_wl55jc.overlay | 23 &clk_lse {
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| D | stm32l562e_dk.overlay | 9 &clk_lse {
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/ |
| D | msis_24.overlay | 12 &clk_lse {
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| D | msis_48.overlay | 12 &clk_lse {
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| D | pll_msis_160.overlay | 12 &clk_lse {
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| D | pll_msis_ahb_2_40.overlay | 12 &clk_lse {
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| D | clear_clocks.overlay | 22 &clk_lse {
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| /Zephyr-latest/dts/arm/rakwireless/ |
| D | rak3172.dtsi | 13 &clk_lse {
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| /Zephyr-latest/dts/arm/olimex/ |
| D | bb-stm32wl.dtsi | 10 &clk_lse {
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/ |
| D | clear_f0_f1_f3_clocks.overlay | 22 &clk_lse {
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| D | clear_f2_f4_f7_clocks.overlay | 22 &clk_lse {
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| /Zephyr-latest/dts/arm/seeed_studio/ |
| D | lora-e5.dtsi | 15 &clk_lse {
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| /Zephyr-latest/boards/st/nucleo_wb05kz/ |
| D | nucleo_wb05kz.dts | 76 &clk_lse {
96 slow-clock = <&clk_lse>;
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| /Zephyr-latest/boards/st/nucleo_wb09ke/ |
| D | nucleo_wb09ke.dts | 76 &clk_lse {
96 slow-clock = <&clk_lse>;
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/ |
| D | clear_clocks.overlay | 17 &clk_lse {
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| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32wb0-rcc.yaml | 33 The slow clock can be either clk_lsi, clk_lse, or clk_16mhz_div512.
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | f0_i2c1_hsi.overlay | 21 &clk_lse {
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| D | f3_i2c1_hsi.overlay | 21 &clk_lse {
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/ |
| D | clear_clocks.overlay | 34 &clk_lse {
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/ |
| D | clear_clocks.overlay | 27 &clk_lse {
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| /Zephyr-latest/include/zephyr/drivers/clock_control/ |
| D | stm32_clock_control.h | 315 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay)
317 #define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
319 #define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass)
320 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), st_stm32_lse_clock, okay)
322 #define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
323 #define STM32_LSE_DRIVING DT_PROP(DT_NODELABEL(clk_lse), driving_capability)
324 #define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass)
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