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/Zephyr-Core-3.4.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/
Dtest_stm32_clock_configuration_i2c.c4 * SPDX-License-Identifier: Apache-2.0
28 static void i2c_set_clock(const struct stm32_pclken *clk) in i2c_set_clock() argument
35 (clock_control_subsys_t) clk, in i2c_set_clock()
40 /* Test clock source */ in i2c_set_clock()
43 if (clk->bus == STM32_SRC_HSI) { in i2c_set_clock()
47 } else if (clk->bus == STM32_SRC_SYSCLK) { in i2c_set_clock()
52 zassert_true(0, "Unexpected domain clk (0x%x)", dev_actual_clk_src); in i2c_set_clock()
55 /* Test status of the used clk source */ in i2c_set_clock()
57 (clock_control_subsys_t)clk); in i2c_set_clock()
58 zassert_true((status == CLOCK_CONTROL_STATUS_ON), "I2C1 clk src must to be on"); in i2c_set_clock()
[all …]
Dtest_stm32_clock_configuration_lptim.c4 * SPDX-License-Identifier: Apache-2.0
46 TC_PRINT("LPTIM1 source clock configured\n"); in ZTEST()
48 /* Test clock source */ in ZTEST()
60 zassert_true(0, "Unexpected domain clk (%d)", dev_actual_clk_src); in ZTEST()
63 /* Test get_rate(srce clk) */ in ZTEST()
67 zassert_true((r == 0), "Could not get LPTIM1 clk srce freq"); in ZTEST()
74 TC_PRINT("LPTIM1 clock source rate: %d Hz\n", dev_dt_clk_freq); in ZTEST()
83 zassert_true((r == 0), "Could not get LPTIM1 clk freq"); in ZTEST()
90 TC_PRINT("LPTIM1 clock source rate: %d Hz\n", dev_dt_clk_freq); in ZTEST()
96 zassert_true((r == 0), "Could not disable LPTIM1 gating clk"); in ZTEST()
[all …]
Dtest_stm32_clock_configuration_adc.c4 * SPDX-License-Identifier: Apache-2.0
35 #define PERIPHCLK_ADC (-1)
37 #define GET_ADC_SOURCE() (-1);
47 #define ADC_SOURCE_PLL (-1)
83 TC_PRINT("ADC1 source clock configured\n"); in ZTEST()
85 /* Test clock source */ in ZTEST()
86 zassert_true((ADC_SOURCE_PLL != -1), "Invalid ADC_SOURCE_PLL defined for target."); in ZTEST()
98 zassert_true(0, "Unexpected src clk (%d)", dev_actual_clk_src); in ZTEST()
101 /* Test status of the used clk source */ in ZTEST()
104 zassert_true((status == CLOCK_CONTROL_STATUS_ON), "ADC1 clk src must to be on"); in ZTEST()
[all …]
Dtest_stm32_clock_configuration_i2s.c4 * SPDX-License-Identifier: Apache-2.0
44 /* Test clock source */ in ZTEST()
52 zassert_true(0, "Unexpected domain clk (0x%x)", dev_actual_clk_src); in ZTEST()
55 /* Test get_rate(srce clk) */ in ZTEST()
59 zassert_true((r == 0), "Could not get I2S clk srce freq"); in ZTEST()
63 "Expected freq: %d Hz. Actual clk: %d Hz", in ZTEST()
66 TC_PRINT("I2S2 clock source rate: %d Hz\n", dev_dt_clk_freq); in ZTEST()
68 /* Test clock_off(gating clk) */ in ZTEST()
71 zassert_true((r == 0), "Could not disable I2S gating clk"); in ZTEST()
73 zassert_true(!__HAL_RCC_SPI2_IS_CLK_ENABLED(), "I2S2 gating clk should be off"); in ZTEST()
[all …]
/Zephyr-Core-3.4.0/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/
Dtest_stm32_clock_configuration.c4 * SPDX-License-Identifier: Apache-2.0
53 /* Test clock_on(domain source) */ in ZTEST()
57 zassert_true((r == 0), "Could not configure SPI domain clk"); in ZTEST()
58 TC_PRINT("SPI1 domain clk configured\n"); in ZTEST()
60 /* Test clk source */ in ZTEST()
72 zassert_true(1, "Unexpected clk src (0x%x)", spi1_actual_domain_clk); in ZTEST()
75 /* Test get_rate(source clk) */ in ZTEST()
79 zassert_true((r == 0), "Could not get SPI clk freq"); in ZTEST()
83 "Expected SPI clk: %d. Actual: %d", in ZTEST()
96 "Expected SPI clk freq: %d. Actual: %d", in ZTEST()
[all …]
/Zephyr-Core-3.4.0/dts/bindings/watchdog/
Dnxp,kinetis-wdog32.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-wdog32"
20 clk-source:
23 description: Watchdog counter clock source
25 clk-divider:
/Zephyr-Core-3.4.0/dts/bindings/adc/
Dnxp,kinetis-adc12.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-adc12"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
17 clk-source:
20 description: converter clock source
22 clk-divider:
27 alternate-voltage-reference:
29 description: use alternate voltage reference source
31 sample-time:
36 "#io-channel-cells":
[all …]
Dnxp,lpc-lpadc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,lpc-lpadc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
17 clk-divider:
22 clk-source:
25 description: source to attach the ADC clock to
27 voltage-ref:
34 - 0
35 - 1
36 - 2
[all …]
Dnxp,kinetis-adc16.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-adc16"
8 include: ["adc-controller.yaml", "pinctrl-device.yaml"]
14 channel-mux-b:
22 periodic-trigger:
26 "#io-channel-cells":
29 clk-source:
31 description: use alternate clock reference source
33 long-sample:
36 - 0
[all …]
/Zephyr-Core-3.4.0/dts/bindings/clock/
Dst,stm32g0-hsi-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
8 It also produces a HSISYS secondary clk which can be used as system clock
9 source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
12 - 1 ==> HSISYS = 16MHZ
13 - 2 ==> HSISYS = 8MHZ
14 - 4 ==> HSISYS = 4MHZ
15 - 8 ==> HSISYS = 2MHZ
16 - 16 ==> HSISYS = 1MHZ
17 - 32 ==> HSISYS = 0.5MHz
18 - 64 ==> HSISYS = 0.25MHZ
[all …]
Drenesas,smartbond-sys-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,smartbond-sys-clk"
9 - name: base.yaml
10 property-allowlist:
11 - status
12 - compatible
15 clock-src:
18 System clock source.
Drenesas,smartbond-lp-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,smartbond-lp-clk"
9 - name: base.yaml
10 property-allowlist:
11 - status
12 - compatible
15 clock-src:
18 Low power clock source.
/Zephyr-Core-3.4.0/dts/bindings/can/
Dnxp,flexcan.yaml2 # SPDX-License-Identifier: Apache-2.0
13 interrupt-names = "warning", "error", "wake-up", "mb-0-15";
15 clk-source = <1>;
17 sample-point = <875>;
18 bus-speed = <125000>;
19 pinctrl-0 = <&pinmux_flexcan0>;
20 pinctrl-names = "default";
22 can-transceiver {
23 max-bitrate = <1000000>;
29 include: ["can-controller.yaml", "pinctrl-device.yaml"]
[all …]
/Zephyr-Core-3.4.0/dts/arm/nxp/
Dnxp_rt6xx_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,cortex-m33f";
26 #address-cells = <1>;
[all …]
Dnxp_rt5xx_common.dtsi2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
21 #address-cells = <1>;
22 #size-cells = <0>;
[all …]
Dnxp_lpc55S6x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
13 #include <arm/armv8-m.dtsi>
21 zephyr,flash-controller = &iap;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
Dnxp_ke1xf.dtsi2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/kinetis_pcc.h>
10 #include <zephyr/dt-bindings/clock/kinetis_scg.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
20 zephyr,flash-controller = &ftfe;
24 #address-cells = <1>;
[all …]
/Zephyr-Core-3.4.0/dts/bindings/iio/adc/
Dnxp,vf610-adc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,vf610-adc"
8 include: adc-controller.yaml
17 clk-source:
21 Select adc clock source: 0 clock from IPG, 1 clock from IPG divided 2, 2 async clock
23 clk-divider:
30 "#io-channel-cells":
49 io-channel-cells:
50 - input
/Zephyr-Core-3.4.0/dts/bindings/timer/
Datmel,sam-tc.yaml1 # SPDX-License-Identifier: Apache-2.0
5 compatible: "atmel,sam-tc"
8 - name: base.yaml
9 - name: pinctrl-device.yaml
25 Valid range: 0 - 2
27 clk:
30 Clock source selection as defined by TCCLKS bit-field of TC_CMR
36 If set to true the `clk` property is ignored. Instead the TC module is
40 reg-cmr:
47 properties like channel-num, pinctrl-0 this allows e.g. to configure
[all …]
Dnxp,lpc-ctimer.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,lpc-ctimer"
17 clk-source:
/Zephyr-Core-3.4.0/dts/bindings/rtc/
Dnxp,kinetis-lptmr.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-lptmr"
14 clock-frequency:
20 clk-source:
23 description: Prescaler clock source (0 to 3)
25 input-pin:
29 active-low:
31 description: Pulse counter input pin is active-low
/Zephyr-Core-3.4.0/samples/boards/stm32/power_mgmt/serial_wakeup/boards/
Dstm32l562e_dk.overlay5 zephyr,shell-uart = &lpuart1;
14 /* Comment out this line to use HSI as clk source */
19 pinctrl-0 = <&lpuart1_rx_pb10 &lpuart1_tx_pb11>;
20 pinctrl-1 = <&analog_pb10 &analog_pb11>;
21 pinctrl-names = "default", "sleep";
26 current-speed = <9600>;
28 wakeup-source;
34 pinctrl-1 = <&analog_pa9 &analog_pa10>;
35 pinctrl-names = "default", "sleep";
37 /* Uncomment out this line to use usart1 as wakeup source */
[all …]
/Zephyr-Core-3.4.0/tests/drivers/adc/adc_dma/boards/
Dfrdm_k64f.overlay4 * SPDX-License-Identifier: Apache-2.0
7 clk-source = <0>;
8 hw-trigger-src = <4>;
9 continuous-convert;
10 high-speed;
11 periodic-trigger;
15 dma-buf-addr-alignment = <4>;
Dfrdm_k82f.overlay4 * SPDX-License-Identifier: Apache-2.0
7 clk-source = <0>;
8 hw-trigger-src = <4>;
9 continuous-convert;
10 high-speed;
11 periodic-trigger;
15 dma-buf-addr-alignment = <4>;
/Zephyr-Core-3.4.0/dts/bindings/spi/
Despressif,esp32-spi.yaml3 compatible: "espressif,esp32-spi"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 half-duplex:
20 Enable half-duplex communication mode.
24 dummy-comp:
31 Enable 3-wire mode
35 dma-enabled:
39 dma-clk:
[all …]

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