Searched +full:check +full:- +full:uart +full:- +full:files (Results 1 – 25 of 95) sorted by relevance
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| /Zephyr-latest/.github/workflows/ |
| D | bsim-tests.yaml | 6 - ".github/workflows/bsim-tests.yaml"
7 - ".github/workflows/bsim-tests-publish.yaml"
8 - "west.yml"
9 - "subsys/bluetooth/**"
10 - "tests/bsim/**"
11 - "boards/nordic/nrf5*/*dt*"
12 - "dts/*/nordic/**"
13 - "tests/bluetooth/common/testlib/**"
14 - "samples/bluetooth/**"
15 - "boards/native/**"
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| /Zephyr-latest/samples/subsys/shell/fs/ |
| D | README.rst | 1 .. zephyr:code-sample:: shell-fs
3 :relevant-api: file_system_api
15 A board with LittleFS file system support and UART console
25 .. zephyr-app-commands::
26 :zephyr-app: samples/subsys/shell/fs
33 You have several options to control this. You can check them with:
35 .. code-block:: console
37 zephyr/zephyr.exe -help
39 Check the :ref:`native_sim UART documentation <native_ptty_uart>` for information on how to connect
40 to the UART.
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| /Zephyr-latest/samples/subsys/tracing/ |
| D | README.rst | 1 .. zephyr:code-sample:: tracing
13 Depends of the boards which you are using, choose one of .conf files for use tracing subsys.
15 Usage for UART Tracing Backend
18 Build a UART-tracing image with:
20 .. zephyr-app-commands::
21 :zephyr-app: samples/subsys/tracing
29 .. zephyr-app-commands::
30 :zephyr-app: samples/subsys/tracing
37 You may need to set "zephyr,tracing-uart" property under the chosen node in your devicetree.
40 After the application has run for a while, check the trace output file.
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| /Zephyr-latest/scripts/utils/ |
| D | pinctrl_nrf_migrate.py | 4 # SPDX-License-Identifier: Apache-2.0
10 This script can be used to automatically migrate the Devicetree files of
11 nRF-based boards using the old <signal>-pin properties to select peripheral
13 file by removing old pin-related properties replacing them with pinctrl states.
14 A board-pinctrl.dtsi file will be generated containing the configuration for
15 all pinctrl states. Note that script will also work on files that have been
20 Devicetree files will be converted correctly. **ADJUSTED/GENERATED FILES
28 -i path/to/board.dts
29 [--no-backup]
30 [--skip-nrf-check]
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| /Zephyr-latest/doc/contribute/documentation/ |
| D | guidelines.rst | 15 view this content either in its raw form as .rst markup files, or (with
24 .. _Sphinx extensions: http://www.sphinx-doc.org/en/stable/contents.html
26 .. _Sphinx Inline Markup: http://sphinx-doc.org/markup/inline.html#inline-markup
30 Sphinx-defined directives and roles used to create the documentation
42 the first non-white space in the preceding line. For example::
50 .. code-block::
66 * Third section heading level (h4) use ``-``
84 For bullet lists, place an asterisk (``*``) or hyphen (``-``) at
113 #. This is a second-level list under the first item (also
143 Multi-column lists
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| /Zephyr-latest/boards/snps/nsim/arc_v/doc/ |
| D | index.rst | 6 This platform can be used to run Zephyr RTOS on the widest possible range of Synopsys RISC-V proces…
10 * RISC-V processor core, which implements riscv32 ISA
11 * Virtual serial console (a standard ``ns16550`` UART model)
15 * ``nsim_arc_v/rmx100`` - Synopsys RISC-V RMX100 core
20 files in :zephyr_file:`boards/snps/nsim/arc_v/support/` directory to understand
33 To run single-core Zephyr RTOS applications in simulation on this board,
40 there might be exceptions from that, especially for newly added targets. You can check supported
43 I.e. for the ``nsim_arc_v/rmx100`` board we can check :zephyr_file:`boards/snps/nsim/arc_v/nsim_arc…
47 * **zephyr** - implies RISC-V GNU toolchain from Zephyr SDK. You can find more information about
49 * **cross-compile** - implies RISC-V GNU cross toolchain, which is not a part of Zephyr SDK. Note t…
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| /Zephyr-latest/boards/espressif/esp8684_devkitm/doc/ |
| D | index.rst | 6 The ESP8684-DevKitM is an entry-level development board based on ESP8684-MINI-1, a general-purpose
7 module with 1 MB/2 MB/4 MB SPI flash. This board integrates complete Wi-Fi and Bluetooth LE functio…
8 For more information, check `ESP8684-DevKitM User Guide`_
13 ESP32-C2 (ESP8684 core) is a low-cost, Wi-Fi 4 & Bluetooth 5 (LE) chip. Its unique design
14 makes the chip smaller and yet more powerful than ESP8266. ESP32-C2 is built around a RISC-V
15 32-bit, single-core processor, with 272 KB of SRAM (16 KB dedicated to cache) and 576 KB of ROM.
16 ESP32-C2 has been designed to target simple, high-volume, and low-data-rate IoT applications,
17 such as smart plugs and smart light bulbs. ESP32-C2 offers easy and robust wireless connectivity,
18 which makes it the go-to solution for developing simple, user-friendly and reliable
19 smart-home devices. For more information, check `ESP8684 Datasheet`_.
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| /Zephyr-latest/tests/lib/cpp/cxx/src/ |
| D | main.cpp | 4 * SPDX-License-Identifier: Apache-2.0
8 * This is mainly a parse test that verifies that Zephyr header files
74 #include <zephyr/drivers/uart.h>
77 #include <zephyr/drivers/video-controls.h>
99 /* Check that BUILD_ASSERT compiles. */
103 /* Check that ARRAY_SIZE compiles. */
106 /* Check that SYS_INIT() compiles. */
114 /* Check that global static object constructors are called. */
123 * Check that dynamic memory allocation (usually, the C library heap) is
130 zassert_equal(static_init_dynamic_foo->get_foo(), 87654321); in ZTEST()
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| /Zephyr-latest/ |
| D | MAINTAINERS.yml | 35 # files:
36 # List of paths and/or glob patterns giving the files in the area,
39 # If a path or glob pattern ends in a '/', it matches all files within
45 # files-regex:
50 # Can be combined with a 'files' key.
52 # Note: Prefer plain 'files' patterns where possible. get_maintainer.py
53 # will check that they match some file, but won't check regexes
56 # files-exclude:
57 # Like 'files', but any matching files will be excluded from the area.
59 # files-regex-exclude:
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| /Zephyr-latest/samples/subsys/mgmt/updatehub/ |
| D | README.rst | 1 .. zephyr:code-sample:: updatehub-fota
2 :name: UpdateHub embedded Firmware Over-The-Air (FOTA) update
3 :relevant-api: updatehub
5 Perform Firmware Over-The-Air (FOTA) updates using UpdateHub.
10 UpdateHub is an enterprise-grade solution which makes it simple to remotely
12 Firmware Over-the-Air (FOTA) updates with maximum security and efficiency,
33 :zephyr:board:`Freedom-K64F <frdm_k64f>` kit using the ethernet connectivity. The
36 * The sample provides overlay files to enable other technologies like WIFI,
52 Zephyr sub-systems and it uses CoAP over UDP.
62 .. code-block:: console
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| /Zephyr-latest/boards/intel/socfpga_std/cyclonev_socdk/doc/ |
| D | index.rst | 37 * J26: Short pins 1-2
38 * J27: Short pins 2-3
39 * J28: Short pins 1-2
40 * J29: Short pins 2-3
41 * J30: Short pins 1-2
48 * SW3: ON-OFF-ON-OFF-ON-ON
49 * SW4: OFF-OFF-ON-ON
51 Other switches are user switches, their position is application-specific.
58 ….intel.com/content/www/us/en/software-kit/684215/intel-quartus-prime-lite-edition-design-software-…
66 .. code-block:: console
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| /Zephyr-latest/doc/build/dts/ |
| D | bindings-syntax.rst | 1 .. _dt-bindings-file-syntax:
7 files are YAML files. A :ref:`simple example <dt-bindings-simple-example>` was
17 The top level of a bindings file maps keys to values. The top-level keys look
20 .. code-block:: yaml
24 This is the Vendomatic company's foo-device.
29 See https://yaml-multiline.info/ for formatting help.
35 compatible: "manufacturer,foo-device"
41 child-binding:
50 # SPI memory chip, use 'on-bus:' to say what type of bus, like this.
53 on-bus: spi
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| /Zephyr-latest/cmake/modules/ |
| D | extensions.cmake | 1 # SPDX-License-Identifier: Apache-2.0
14 # 1. Zephyr-aware extensions
21 # 2. Kconfig-aware extensions
23 # 3. CMake-generic extensions
44 # 1. Zephyr-aware extensions
49 # "zephyr". zephyr is a catch-all CMake library for source files that
51 # compiler flags that all zephyr source files use.
52 # [0] https://cmake.org/cmake/help/latest/manual/cmake-buildsystem.7.html
66 # As a very high-level introduction here are two call graphs that are
72 # zephyr_library_compile_options() --> target_compile_options()
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| /Zephyr-latest/boards/snps/nsim/arc_classic/doc/ |
| D | index.rst | 13 * Virtual serial console (a standard ``ns16550`` UART model)
19 There are multiple supported sub-configurations for that platform. Some but not all of currently
22 * ``nsim/nsim_em`` - ARC EM core v4.0 with two register banks, FastIRQ's, MPUv2, DSP options and
23 XY-memory
24 * ``nsim/nsim_em7d_v22`` - ARC EM core v3.0 with one register bank and FastIRQ's
25 * ``nsim/nsim_em11d`` - ARC EM core v4.0 with one register bank, no FastIRQ's, MPUv2, DSP options a…
26 XY-memory
27 * ``nsim/nsim_sem`` - ARC EM core v4.0 with secure features (thus "SEM", i.e. Secure EM) and MPUv4
28 * ``nsim/nsim_hs`` - ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
29 * ``nsim/nsim_hs/smp`` - Dual-core ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
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| /Zephyr-latest/boards/espressif/esp32c6_devkitc/doc/ |
| D | index.rst | 6 ESP32-C6-DevKitC is an entry-level development board based on ESP32-C6-WROOM-1(U),
7 a general-purpose module with a 8 MB SPI flash. This board integrates complete Wi-Fi,
8 Bluetooth LE, Zigbee, and Thread functions. For more information, check `ESP32-C6-DevKitC`_.
13 ESP32-C6 is Espressif's first Wi-Fi 6 SoC integrating 2.4 GHz Wi-Fi 6, Bluetooth 5.3 (LE) and the
14 802.15.4 protocol. ESP32-C6 achieves an industry-leading RF performance, with reliable security
16 It consists of a high-performance (HP) 32-bit RISC-V processor, which can be clocked up to 160 MHz,
17 and a low-power (LP) 32-bit RISC-V processor, which can be clocked up to 20 MHz.
20 ESP32-C6-DevKitC is an entry-level development board based on ESP32-C6-WROOM-1(U),
21 a general-purpose module with a 8 MB SPI flash.
24 Developers can either connect peripherals with jumper wires or mount ESP32-C6-DevKitC on
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| /Zephyr-latest/boards/espressif/esp32s2_saola/doc/ |
| D | index.rst | 6 ESP32-S2-Saola is a small-sized ESP32-S2 based development board produced by Espressif.
8 Developers can either connect peripherals with jumper wires or mount ESP32-S2-Saola on a breadboard.
9 For more information, check `ESP32-S3-DevKitC`_.
14 ESP32-S2 is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, designed to be s…
15 cost-effective, with a high performance and a rich set of IO capabilities.
19 - RSA-3072-based secure boot
20 - AES-XTS-256-based flash encryption
21 - Protected private key and device secrets from software access
22 - Cryptographic accelerators for enhanced performance
23 - Protection against physical fault injection attacks
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| /Zephyr-latest/boards/espressif/esp32s2_devkitc/doc/ |
| D | index.rst | 6 ESP32-S2-DevKitC is an entry-level development board. This board integrates complete Wi-Fi function…
8 Developers can either connect peripherals with jumper wires or mount ESP32-S2-DevKitC on a breadboa…
9 For more information, check `ESP32-S2-DevKitC`_.
14 ESP32-S2 is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, designed to be s…
15 cost-effective, with a high performance and a rich set of IO capabilities.
19 - RSA-3072-based secure boot
20 - AES-XTS-256-based flash encryption
21 - Protected private key and device secrets from software access
22 - Cryptographic accelerators for enhanced performance
23 - Protection against physical fault injection attacks
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| /Zephyr-latest/boards/espressif/esp32c3_devkitc/doc/ |
| D | index.rst | 6 ESP32-C3-DevKitC-02 is an entry-level development board based on ESP32-C3-WROOM-02,
7 a general-purpose module with 4 MB SPI flash. This board integrates complete Wi-Fi and Bluetooth® L…
8 For more information, check `ESP32-C3-DevKitC`_.
13 ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC,
14 based on the open-source RISC-V architecture. It strikes the right balance of power,
15 I/O capabilities and security, thus offering the optimal cost-effective
17 The availability of Wi-Fi and Bluetooth 5 (LE) connectivity not only makes the device configuration…
18 but it also facilitates a variety of use-cases based on dual connectivity.
22 - 32-bit core RISC-V microcontroller with a maximum clock speed of 160 MHz
23 - 400 KB of internal RAM
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| /Zephyr-latest/boards/espressif/esp32c3_devkitm/doc/ |
| D | index.rst | 6 ESP32-C3-DevKitM is an entry-level development board based on ESP32-C3-MINI-1,
7 a module named for its small size. This board integrates complete Wi-Fi and Bluetooth® Low Energy f…
8 For more information, check `ESP32-C3-DevKitM`_.
13 ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC,
14 based on the open-source RISC-V architecture. It strikes the right balance of power,
15 I/O capabilities and security, thus offering the optimal cost-effective
17 The availability of Wi-Fi and Bluetooth 5 (LE) connectivity not only makes the device configuration…
18 but it also facilitates a variety of use-cases based on dual connectivity.
22 - 32-bit core RISC-V microcontroller with a maximum clock speed of 160 MHz
23 - 400 KB of internal RAM
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| /Zephyr-latest/boards/we/orthosie1ev/doc/ |
| D | index.rst | 6 Orthosie-I-EV is an entry-level development board based on Orthosie-I,
7 a module named for its small size. This board integrates complete Wi-Fi and Bluetooth® Low Energy f…
8 For more information, check `Orthosie-I Website`_.
13 ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC,
14 based on the open-source RISC-V architecture. It strikes the right balance of power,
15 I/O capabilities and security, thus offering the optimal cost-effective
17 The availability of Wi-Fi and Bluetooth 5 (LE) connectivity not only makes the device configuration…
18 but it also facilitates a variety of use-cases based on dual connectivity.
22 - 32-bit core RISC-V microcontroller with a maximum clock speed of 160 MHz
23 - 400 KB of internal RAM
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| /Zephyr-latest/doc/releases/ |
| D | release-notes-1.5.rst | 7 1.5.0. This is the first release to follow the 3-month release cadence.
13 - TCP Support
14 - Integration of the Paho MQTT Library support with QoS
15 - Flash Filesystem Support
16 - Integration of the mbedTLS library for encryption
17 - Improved BR/EDR support (for L2CAP, in particular).
18 - Support for the Altera Nios II/f soft CPU architecture
25 - Added nano_fifo_put_list() APIs, which allows queuing a list of elements
27 - Removed unused memory pool structure field.
28 - Enhanced memory pool code.
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| /Zephyr-latest/boards/waveshare/esp32s3_touch_lcd_1_28/doc/ |
| D | index.rst | 6 The ESP32-S3-Touch-LCD-1.28 is an ESP32S3 development board from Waveshare with a round LCD,
7 suitable to build watches or similar projects. This board integrates complete Wi-Fi and Bluetooth
13 ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi
14 and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor
15 (Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband,
18 ESP32-S3-Touch-LCD-1.28 includes the following features:
20 - Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz
21 - Additional vector instructions support for AI acceleration
22 - 2MB of SRAM
23 - 16MB of FLASH
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| /Zephyr-latest/boards/espressif/esp32s3_devkitc/doc/ |
| D | index.rst | 6 The ESP32-S3-DevKitC is an entry-level development board equipped with either ESP32-S3-WROOM-1
7 or ESP32-S3-WROOM-1U, a module named for its small size. This board integrates complete Wi-Fi
8 and Bluetooth Low Energy functions. For more information, check `ESP32-S3-DevKitC`_.
13 ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi
14 and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor
15 (Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband,
18 ESP32-S3-DevKitC includes the following features:
20 - Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz
21 - Additional vector instructions support for AI acceleration
22 - 512KB of SRAM
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| /Zephyr-latest/boards/espressif/esp32s3_devkitm/doc/ |
| D | index.rst | 6 The ESP32-S3-DevKitM is an entry-level development board equipped with either ESP32-S3-MINI-1
7 or ESP32-S3-MINI-1U, a module named for its small size. This board integrates complete Wi-Fi
8 and Bluetooth Low Energy functions. For more information, check `ESP32-S3-DevKitM User Guide`_.
13 ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi
14 and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor
15 (Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband,
18 ESP32-S3-DevKitM includes the following features:
20 - Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz
21 - Additional vector instructions support for AI acceleration
22 - 512KB of SRAM
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| /Zephyr-latest/boards/luatos/esp32s3_luatos_core/doc/ |
| D | index.rst | 3 ESP32S3-Luatos-Core
9 The ESP32S3-Luatos-Core development board is a compact board based on Espressif ESP32-S3.
10 The board comes equipped with a 2.4GHz antenna and supports both Wi-Fi and Bluetooth functionalitie…
11 For more information, check `ESP32S3-Luatos-Core`_ (chinese)
20 ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi
21 and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor
22 (Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband,
25 ESP32S3-Luatos-Core includes the following features:
27 - Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz
28 - Additional vector instructions support for AI acceleration
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