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/trusted-firmware-m-latest/platform/ext/target/arm/rse/common/native_drivers/
Dmhu_v3_x.h71 * \brief MHUv3 channel types
74 /* Doorbell channel */
76 /* Channel type count */
117 * \param[in] ch_type MHU channel type \ref mhu_v3_x_channel_type_t
127 * \brief Clears the doorbell channel
130 * \param[in] channel Channel number
131 * \param[in] mask Mask to be used when clearing the channel
136 uint32_t channel, uint32_t mask);
139 * \brief Write value to a doorbell channel
142 * \param[in] channel Doorbell channel number
[all …]
Dmhu_v2_x.h103 * \brief Sends the value over a channel.
106 * \param[in] channel Channel to send the value over.
109 * Sends the value over a channel.
114 * \note This function doesn't check if channel is implemented.
117 uint32_t channel, uint32_t val);
120 * \brief Polls sender channel status.
123 * \param[in] channel Channel to poll the status of.
126 * Polls sender channel status.
131 * \note This function doesn't check if channel is implemented.
134 uint32_t channel, uint32_t *value);
[all …]
Dmhu_v3_x.c37 /* Offset: 0x020 (R/ ) Postbox Doorbell Channel Configuration 0 */
41 /* Offset: 0x030 (R/ ) Postbox FIFO Channel Configuration 0 */
45 /* Offset: 0x040 (R/ ) Postbox Fast Channel Configuration 0 */
54 * Offset: 0x400 (R/ ) Postbox Doorbell Channel Interrupt Status n, where
59 * Offset: 0x410 (R/ ) Postbox FIFO Channel <n> Interrupt Status n, where n
77 * \brief Postbox doorbell channel window page structure
80 /* Offset: 0x000 (R/ ) Postbox Doorbell Channel Window Status */
84 /* Offset: 0x00C ( /W) Postbox Doorbell Channel Window Set */
86 /* Offset: 0x010 (R/ ) Postbox Doorbell Channel Window Interrupt Status */
88 /* Offset: 0x014 ( /W) Postbox Doorbell Channel Window Interrupt Clear */
[all …]
Dmhu_v2_x.c34 /* Offset: 0x00 (R/ ) Channel Status */
40 /* Offset: 0x0C ( /W) Channel Set */
42 /* Offset: 0x10 (R/ ) Channel Interrupt Status (Reserved in 2.0) */
44 /* Offset: 0x14 ( /W) Channel Interrupt Clear (Reserved in 2.0) */
46 /* Offset: 0x18 (R/W) Channel Interrupt Enable (Reserved in 2.0) */
53 /* Offset: 0x000 ( / ) Sender Channel Window 0 -123 */
71 /* Offset: 0xFA0 (R/W) Channel Combined Interrupt Stat (Reserved in 2.0) */
88 /* Offset: 0x00 (R/ ) Channel Status */
90 /* Offset: 0x04 (R/ ) Channel Status Masked */
92 /* Offset: 0x08 ( /W) Channel Clear */
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/corstone1000/Native_Driver/
Dmhu_v2_x.h103 * \brief Sends the value over a channel.
106 * \param[in] channel Channel to send the value over.
109 * Sends the value over a channel.
114 * \note This function doesn't check if channel is implemented.
117 uint32_t channel, uint32_t val);
120 * \brief Polls sender channel status.
123 * \param[in] channel Channel to poll the status of.
126 * Polls sender channel status.
131 * \note This function doesn't check if channel is implemented.
134 uint32_t channel, uint32_t *value);
[all …]
Dmhu_v2_x.c34 /* Offset: 0x00 (R/ ) Channel Status */
40 /* Offset: 0x0C ( /W) Channel Set */
42 /* Offset: 0x10 (R/ ) Channel Interrupt Status (Reserved in 2.0) */
44 /* Offset: 0x14 ( /W) Channel Interrupt Clear (Reserved in 2.0) */
46 /* Offset: 0x18 (R/W) Channel Interrupt Enable (Reserved in 2.0) */
53 /* Offset: 0x000 ( / ) Sender Channel Window 0 -123 */
71 /* Offset: 0xFA0 (R/W) Channel Combined Interrupt Stat (Reserved in 2.0) */
88 /* Offset: 0x00 (R/ ) Channel Status */
90 /* Offset: 0x04 (R/ ) Channel Status Masked */
92 /* Offset: 0x08 ( /W) Channel Clear */
[all …]
/trusted-firmware-m-latest/platform/ext/target/nuvoton/m2351/bsp/Library/StdDriver/src/
Dbpwm.c29 * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
98 * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
103 * existing frequency of other channel.
189 * @brief Stop BPWM generation immediately by clear channel enable bit
195 * @details This function is used to stop BPWM generation immediately by clear channel enable bit.
205 * @brief Enable selected channel to trigger ADC
209 * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
219 * @details This function is used to enable selected channel to trigger ADC
236 * @brief Disable selected channel to trigger ADC
240 * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~3
[all …]
Depwm.c29 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
97 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
102 * existing frequency of other channel.
159 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
160 * Bit 0 is channel 0, bit 1 is channel 1...
174 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
175 * Bit 0 is channel 0, bit 1 is channel 1...
192 * @brief Stop EPWM generation immediately by clear channel enable bit
196 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
197 * Bit 0 is channel 0, bit 1 is channel 1...
[all …]
Dpdma.c31 * @param[in] u32Mask Channel enable bits.
71 * @param[in] u32Ch The selected channel
80 * @details This function set the selected channel data width and transfer count.
92 * @param[in] u32Ch The selected channel
112 * @param[in] u32Ch The selected channel
124 * @details This function set the selected channel source/destination address and attribute.
138 * @param[in] u32Ch The selected channel
195 * @details This function set the selected channel transfer mode. Include peripheral setting.
245 * @param[in] u32Ch The selected channel
261 * @details This function set the selected channel burst type and size.
[all …]
/trusted-firmware-m-latest/platform/ext/target/cypress/psoc64/Device/Source/gcc/
Dstartup_psoc64_ns.S105 .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
106 .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
107 .long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
108 .long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
109 .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
110 .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
111 .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
112 .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
113 .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
114 .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/musca_b1/Native_Driver/
Dmhu_v2_x.h105 * \brief Sends the value over a channel.
108 * \param[in] channel Channel to send the value over.
111 * Sends the value over a channel.
116 * \note This function doesn't check if channel is implemented.
119 uint32_t channel, uint32_t val);
122 * \brief Clears the channel after the value is send over it.
125 * \param[in] channel Channel to clear.
127 * Clears the channel after the value is send over it.
132 * \note This function doesn't check if channel is implemented.
135 uint32_t channel);
[all …]
Dmhu_v2_x.c34 /* Offset: 0x00 (R/ ) Channel Status */
40 /* Offset: 0x0C ( /W) Channel Set */
42 /* Offset: 0x10 (R/ ) Channel Interrupt Status (Reserved in 2.0) */
44 /* Offset: 0x14 ( /W) Channel Interrupt Clear (Reserved in 2.0) */
46 /* Offset: 0x18 (R/W) Channel Interrupt Enable (Reserved in 2.0) */
53 /* Offset: 0x000 ( / ) Sender Channel Window 0 -123 */
71 /* Offset: 0xFA0 (R/W) Channel Combined Interrupt Stat (Reserved in 2.0) */
88 /* Offset: 0x00 (R/ ) Channel Status */
90 /* Offset: 0x04 (R/ ) Channel Status Masked */
92 /* Offset: 0x08 ( /W) Channel Clear */
[all …]
/trusted-firmware-m-latest/platform/ext/target/cypress/psoc64/Device/Source/armclang/
Dstartup_psoc64_ns.s114 DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0
115 DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1
116 DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2
117 DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3
118 DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0
119 DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1
120 DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2
121 DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3
122 DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4
123 DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5
[all …]
/trusted-firmware-m-latest/platform/ext/target/cypress/psoc64/Device/Source/iar/
Dstartup_psoc64_ns.s120 DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0
121 DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1
122 DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2
123 DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3
124 DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0
125 DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1
126 DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2
127 DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3
128 DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4
129 DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5
[all …]
/trusted-firmware-m-latest/platform/ext/target/nuvoton/m2354/bsp/Library/StdDriver/src/
Dbpwm.c29 * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
99 * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
104 * existing frequency of other channel.
190 * @brief Stop BPWM generation immediately by clear channel enable bit
196 * @details This function is used to stop BPWM generation immediately by clear channel enable bit.
206 * @brief Enable selected channel to trigger ADC
210 * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
220 * @details This function is used to enable selected channel to trigger ADC
237 * @brief Disable selected channel to trigger ADC
241 * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~3
[all …]
Depwm.c29 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
98 * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
103 * existing frequency of other channel.
160 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
161 * Bit 0 is channel 0, bit 1 is channel 1...
175 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
176 * Bit 0 is channel 0, bit 1 is channel 1...
193 * @brief Stop EPWM generation immediately by clear channel enable bit
197 * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
198 * Bit 0 is channel 0, bit 1 is channel 1...
[all …]
Dpdma.c31 * @param[in] u32Mask Channel enable bits.
71 * @param[in] u32Ch The selected channel
80 * @details This function set the selected channel data width and transfer count.
92 * @param[in] u32Ch The selected channel
112 * @param[in] u32Ch The selected channel
132 * @param[in] u32Ch The selected channel
144 * @details This function set the selected channel source/destination address and attribute.
158 * @param[in] u32Ch The selected channel
227 * @details This function set the selected channel transfer mode. Include peripheral setting.
277 * @param[in] u32Ch The selected channel
[all …]
/trusted-firmware-m-latest/platform/ext/target/nuvoton/m2354/bsp/Device/Nuvoton/M2354/Include/
Dpdma_reg.h31 …set: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70 Descriptor Table Control Register of PDMA Channel 0~7
36 …* | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA fi…
89 * Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74 Source Address Register of PDMA Channel 0~7
97 …* Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78 Destination Address Register of PDMA Channel 0~7
105 …x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C First Scatter-Gather Descriptor Table Offset of PDMA Channel 0~7
122 …0x20/0x30/0x40/0x50/0x60/0x70] Descriptor Table Control Register of PDMA Channel 0~7 …
123 …0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74] Source Address Register of PDMA Channel 0~7 …
124 …0x18/0x28/0x38/0x48/0x58/0x68/0x78] Destination Address Register of PDMA Channel 0~7 …
133 … * Offset: 0x500/0x508/0x510/0x518/0x520/0x528 Stride Transfer Count Register of PDMA Channel 0~5
140 … * Offset: 0x504/0x50C/0x514/0x51C/0x524/0x52C Address Stride Offset Register of PDMA Channel 0~5
[all …]
/trusted-firmware-m-latest/platform/ext/target/stm/common/stm32h5xx/hal/Src/
Dstm32h5xx_hal_dma.c51 …For a given channel, enable and configure the peripheral to be connected to the DMA Channel (excep…
56 …For a given channel, use HAL_DMA_Init function to program the required configuration for normal tr…
59 (+) Request : Specifies the DMA channel request
63 (+) BlkHWRequest : Specifies the Block hardware request mode for DMA channel
66 (+) Direction : Specifies the transfer direction for DMA channel
69 (+) SrcInc : Specifies the source increment mode for the DMA channel
72 (+) DestInc : Specifies the destination increment mode for the DMA channel
75 (+) SrcDataWidth : Specifies the source data width for the DMA channel
78 (+) DestDataWidth : Specifies the destination data width for the DMA channel
81 (+) Priority : Specifies the priority for the DMA channel
[all …]
/trusted-firmware-m-latest/platform/ext/target/stm/common/stm32u5xx/hal/Src/
Dstm32u5xx_hal_dma.c52 …For a given channel, enable and configure the peripheral to be connected to the DMA Channel (excep…
57 …For a given channel, use HAL_DMA_Init function to program the required configuration for normal tr…
60 (+) Request : Specifies the DMA channel request
64 (+) BlkHWRequest : Specifies the Block hardware request mode for DMA channel
67 (+) Direction : Specifies the transfer direction for DMA channel
70 (+) SrcInc : Specifies the source increment mode for the DMA channel
73 (+) DestInc : Specifies the destination increment mode for the DMA channel
76 (+) SrcDataWidth : Specifies the source data width for the DMA channel
79 (+) DestDataWidth : Specifies the destination data width for the DMA channel
82 (+) Priority : Specifies the priority for the DMA channel
[all …]
/trusted-firmware-m-latest/platform/ext/target/nuvoton/m2351/bsp/Device/Nuvoton/M2351/Include/
Dpdma_reg.h30 …set: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70 Descriptor Table Control Register of PDMA Channel 0~7
35 …* | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA fi…
88 * Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74 Source Address Register of PDMA Channel 0~7
96 …* Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78 Destination Address Register of PDMA Channel 0~7
104 …x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C First Scatter-Gather Descriptor Table Offset of PDMA Channel 0~7
121 …0x20/0x30/0x40/0x50/0x60/0x70] Descriptor Table Control Register of PDMA Channel 0~7 …
122 …0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74] Source Address Register of PDMA Channel 0~7 …
123 …0x18/0x28/0x38/0x48/0x58/0x68/0x78] Destination Address Register of PDMA Channel 0~7 …
132 … * Offset: 0x500/0x508/0x510/0x518/0x520/0x528 Stride Transfer Count Register of PDMA Channel 0~5
139 … * Offset: 0x504/0x50C/0x514/0x51C/0x524/0x52C Address Stride Offset Register of PDMA Channel 0~5
[all …]
/trusted-firmware-m-latest/platform/ext/target/arm/drivers/dma/dma350/
Ddma350_lib_unprivileged.h29 * \brief Clear a status bit of the dma channel
31 * \param[in] channel DMA350 channel number
37 enum dma350_lib_error_t dma350_clear_done_irq_unpriv(uint8_t channel);
42 * \param[in] channel DMA350 channel number
52 enum dma350_lib_error_t dma350_memcpy_unpriv(uint8_t channel, const void* src,
60 * \param[in] channel DMA350 channel number
70 enum dma350_lib_error_t dma350_memmove_unpriv(uint8_t channel, const void* src,
81 * \param[in] channel DMA350 channel number
102 enum dma350_lib_error_t dma350_draw_from_canvas_unpriv(uint8_t channel,
116 * \param[in] channel DMA350 channel number
[all …]
Ddma350_drv.h243 * \brief Set DMA350 DMA Channel to secure.
246 * \param[in] channel Id of the channel to be updated
251 * Operation will fail if channel is enabled.
254 uint8_t channel);
257 * \brief Set DMA350 DMA Channel to non-secure.
260 * \param[in] channel Id of the channel to be updated
265 * Operation will fail if channel is enabled.
268 uint8_t channel);
271 * \brief Set DMA350 DMA Channel to privileged.
274 * \param[in] channel Id of the channel to be updated
[all …]
/trusted-firmware-m-latest/platform/ext/target/nuvoton/m2354/bsp/Library/StdDriver/inc/
Depwm.h29 #define EPWM_CHANNEL_NUM (6UL) /*!< EPWM channel number */
30 #define EPWM_CH_0_MASK (0x1UL) /*!< EPWM channel 0 mask \hideinitiali…
31 #define EPWM_CH_1_MASK (0x2UL) /*!< EPWM channel 1 mask \hideinitiali…
32 #define EPWM_CH_2_MASK (0x4UL) /*!< EPWM channel 2 mask \hideinitiali…
33 #define EPWM_CH_3_MASK (0x8UL) /*!< EPWM channel 3 mask \hideinitiali…
34 #define EPWM_CH_4_MASK (0x10UL) /*!< EPWM channel 4 mask \hideinitiali…
35 #define EPWM_CH_5_MASK (0x20UL) /*!< EPWM channel 5 mask \hideinitiali…
69 … (0UL) /*!< EPWM trigger ADC while counter of even channel matches zero poin…
70 …D (1UL) /*!< EPWM trigger ADC while counter of even channel matches period po…
71 …PERIOD (2UL) /*!< EPWM trigger ADC while counter of even channel matches zero or p…
[all …]
/trusted-firmware-m-latest/platform/ext/target/nuvoton/m2351/bsp/Library/StdDriver/inc/
Depwm.h29 #define EPWM_CHANNEL_NUM (6UL) /*!< EPWM channel number */
30 #define EPWM_CH_0_MASK (0x1UL) /*!< EPWM channel 0 mask \hideinitiali…
31 #define EPWM_CH_1_MASK (0x2UL) /*!< EPWM channel 1 mask \hideinitiali…
32 #define EPWM_CH_2_MASK (0x4UL) /*!< EPWM channel 2 mask \hideinitiali…
33 #define EPWM_CH_3_MASK (0x8UL) /*!< EPWM channel 3 mask \hideinitiali…
34 #define EPWM_CH_4_MASK (0x10UL) /*!< EPWM channel 4 mask \hideinitiali…
35 #define EPWM_CH_5_MASK (0x20UL) /*!< EPWM channel 5 mask \hideinitiali…
69 … (0UL) /*!< EPWM trigger ADC while counter of even channel matches zero poin…
70 …D (1UL) /*!< EPWM trigger ADC while counter of even channel matches period po…
71 …PERIOD (2UL) /*!< EPWM trigger ADC while counter of even channel matches zero or p…
[all …]

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