| /Zephyr-latest/soc/nxp/imx/imx8m/m7/ |
| D | mpu_regions.c | 24 * Memory with Device type, not executable, not shareable, non-cacheable.
32 * Memory with Normal type, not shareable, non-cacheable
40 * Memory with Normal type, not shareable, cacheable
48 * Memory with Normal type, not shareable, non-cacheable
56 * Memory with Normal type, not shareable, non-cacheable
63 * Non-cacheable area is provided in DDR memory, the DDR region [0x80000000 ~ 0x81000000]
68 * space 0x80000000 ~ 0xBFFFFFFF to be non-cacheable. Then MPU region 6 set the text and
69 * data section to be cacheable if the program running on DDR. The cacheable area base
74 * Memory with Normal type, not shareable, non-cacheable
81 /* If run on DDR, configure text and data section to be cacheable */
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| /Zephyr-latest/doc/kernel/memory_management/ |
| D | shared_multi_heap.rst | 8 attributes (cacheable, non-cacheable, etc...).
31 // Fill the struct with the data for cacheable memory
41 // Add another cacheable region
50 // Add a non-cacheable region
69 // Allocate 4K from cacheable memory
72 // Allocate 4K from non-cacheable memory
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| /Zephyr-latest/tests/lib/shared_multi_heap/src/ |
| D | main.c | 155 * Request a small cacheable chunk. It should be allocated in the in ZTEST()
165 * Request another small cacheable chunk. It should be allocated in the in ZTEST()
166 * smaller cacheable region RES0 in ZTEST()
175 * Request a big cacheable chunk. It should be allocated in the in ZTEST()
176 * bigger cacheable region RES2 in ZTEST()
185 * Request a non-cacheable chunk. It should be allocated in the in ZTEST()
186 * non-cacheable region RES1 in ZTEST()
195 * Request again a non-cacheable chunk. It should be allocated in the in ZTEST()
196 * non-cacheable region RES1 in ZTEST()
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| /Zephyr-latest/tests/subsys/mem_mgmt/mem_attr_heap/src/ |
| D | main.c | 38 * Allocate 0x100 bytes of cacheable memory. in ZTEST()
52 * Allocate 0x100 bytes of non-cacheable memory. in ZTEST()
80 * Allocate 0x100 bytes of cacheable and DMA memory. in ZTEST()
100 * Allocate memory too big to fit into the first cacheable memory in ZTEST()
108 * (bigger) cacheable memory region in ZTEST()
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_gicv3_priv.h | 17 #define GIC_BASER_CACHE_NCACHEABLE 0x1UL /* Non-cacheable */
18 #define GIC_BASER_CACHE_RAWT 0x2UL /* Cacheable R-allocate, W-through */
19 #define GIC_BASER_CACHE_RAWB 0x3UL /* Cacheable R-allocate, W-back */
20 #define GIC_BASER_CACHE_WAWT 0x4UL /* Cacheable W-allocate, W-through */
21 #define GIC_BASER_CACHE_WAWB 0x5UL /* Cacheable W-allocate, W-back */
22 #define GIC_BASER_CACHE_RAWAWT 0x6UL /* Cacheable R-allocate, W-allocate, W-through */
23 #define GIC_BASER_CACHE_RAWAWB 0x7UL /* Cacheable R-allocate, W-allocate, W-back */
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| /Zephyr-latest/soc/nordic/common/ |
| D | dmm.c | 92 /* Buffer is contained within non-cacheable region - use it as it is. */ in is_user_buffer_correctly_preallocated()
97 /* If buffer is in cacheable region it must be aligned to data cache line size. */ in is_user_buffer_correctly_preallocated()
145 * if it is located in cacheable region. in dmm_buffer_out_prepare()
164 /* Check if device memory region is cacheable in dmm_buffer_out_prepare()
218 * if it is located in cacheable region. in dmm_buffer_in_prepare()
234 /* Check if device memory region is cacheable in dmm_buffer_in_prepare()
257 /* Check if device memory region is cacheable in dmm_buffer_in_release()
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| D | dmm.h | 28 /* Determine if memory region is cacheable. */
35 * Cache line alignment is required if region is cacheable and data cache is enabled.
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_pca_series.c | 421 * @brief read all cacheable physical registers from device and update them
554 LOG_ERR("can not update non-cacheable reg type %d", reg_type); in gpio_pca_series_reg_cache_update()
843 LOG_WRN("skip reg %d: not present or non-cacheable", reg_type); in gpio_pca_series_cache_test()
1809 * - non-cacheable
1812 * - cacheable
1815 * - cacheable
1818 * - cacheable if present
1821 * - non-cacheable
1824 * - cacheable if present
1827 * - cacheable if present
[all …]
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| /Zephyr-latest/arch/arm/core/mmu/ |
| D | arm_mmu_priv.h | 91 uint32_t cacheable : 1; member
128 uint32_t cacheable : 1; member
139 uint32_t cacheable : 1; member
192 uint32_t cacheable : 1; member
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| D | arm_mmu.c | 70 * cacheable, read / write and non-executable
79 /* Mark text segment cacheable, read only and executable */
95 /* Mark rodata segment cacheable, read only and non-executable */
294 perms_attrs.cacheable = 0; in arm_mmu_convert_attr_flags()
304 perms_attrs.cacheable = 0; in arm_mmu_convert_attr_flags()
337 perms_attrs.cacheable = ARM_MMU_C_CACHE_ATTRS_WB_WA; in arm_mmu_convert_attr_flags()
340 perms_attrs.cacheable = ARM_MMU_C_CACHE_ATTRS_WT_nWA; in arm_mmu_convert_attr_flags()
343 perms_attrs.cacheable = ARM_MMU_C_CACHE_ATTRS_WB_nWA; in arm_mmu_convert_attr_flags()
420 l1_page_table.entries[l1_index].l1_section_1m.cacheable = perms_attrs.cacheable; in arm_mmu_l1_map_section()
483 perms_attrs.cacheable = l1_page_table.entries[l1_index].l1_section_1m.cacheable; in arm_mmu_remap_l1_section_to_l2_table()
[all …]
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| /Zephyr-latest/include/zephyr/multi_heap/ |
| D | shared_multi_heap.h | 34 * of memory regions with different capabilities / attributes (cacheable,
35 * non-cacheable, etc...).
70 /** cacheable */
73 /** non-cacheable */
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| /Zephyr-latest/include/zephyr/arch/arm64/ |
| D | arm_mem.h | 22 /** ARM64 Specific flags: normal memory with Non-cacheable */
|
| /Zephyr-latest/dts/bindings/spi/ |
| D | nxp,imx-flexspi.yaml | 23 ahb-cacheable:
26 Enable AHB cacheable read access by setting register field
|
| /Zephyr-latest/arch/arc/core/mpu/ |
| D | arc_mpu_v6_internal.h | 43 * 0x0: (Default) Code is cacheable in all levels of the cache hierarchy
44 * 0x1: Code is not cacheable in any level of the cache hierarchy
48 * 0x0: (Default) Data is cacheable in all levels of the cache hierarchy
49 * 0x1: Data is not cacheable in any level of the cache hierarchy
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| /Zephyr-latest/doc/services/mem_mgmt/ |
| D | index.rst | 14 For example, to mark a memory region in the devicetree as non-volatile, cacheable,
153 // Allocate 0x100 bytes of cacheable memory from `mem_cacheable`
156 // Allocate 0x200 bytes of non-cacheable memory aligned to 32 bytes
160 // Allocate 0x100 bytes of cacheable and dma-able memory from `mem_cacheable_dma`
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| /Zephyr-latest/soc/intel/intel_adsp/common/include/ |
| D | cpu_init.h | 17 #define ATOMCTL_WT_RCW BIT(2) /* RCW Transaction for Writethrough Cacheable Memory */
18 #define ATOMCTL_WB_RCW BIT(4) /* RCW Transaction for Writeback Cacheable Memory */
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| /Zephyr-latest/include/zephyr/mem_mgmt/ |
| D | mem_attr.h | 86 * (for example the buffer is cacheable / non-cacheable or belongs to RAM /
|
| /Zephyr-latest/lib/heap/ |
| D | Kconfig | 133 different capabilities / attributes (cacheable, non-cacheable,
|
| /Zephyr-latest/include/zephyr/dt-bindings/memory-attr/ |
| D | memory-attr.h | 20 #define DT_MEM_CACHEABLE BIT(0) /* cacheable */
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| /Zephyr-latest/include/zephyr/arch/arm64/cortex_r/ |
| D | arm_mpu.h | 88 /* Read/Write Allocation Configurations for Cacheable Memory */
97 #define NORMAL_O_NON_C 0x40U /* Normal, Outer Non-Cacheable */
101 #define NORMAL_I_NON_C 0x04U /* Normal, Inner Non-Cacheable */
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| /Zephyr-latest/boards/nxp/mimxrt1050_evk/ |
| D | mimxrt1050_evk_mimxrt1052_hyperflash.dts | 24 ahb-cacheable;
|
| /Zephyr-latest/boards/nxp/mimxrt1060_evk/ |
| D | mimxrt1060_evk_mimxrt1062_hyperflash.dts | 22 ahb-cacheable;
|
| /Zephyr-latest/soc/andestech/ae350/ |
| D | pma.c | 37 /* non-cacheable attributes (bufferable or not) */
39 /* cacheable attributes (write-through/back, no/read/write/RW-allocate) */
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| /Zephyr-latest/arch/arm/include/cortex_m/ |
| D | kernel_arch_func.h | 52 * as Application Memory or No-Cacheable SRAM area. in arch_kernel_init()
|
| /Zephyr-latest/include/zephyr/arch/xtensa/ |
| D | mpu.h | 170 * cacheable vs non-cacheable, shareable vs non-shareable.
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