Searched full:busses (Results 1 – 7 of 7) sorted by relevance
84 On parallel data busses, if bus-width is used to specify the number of126 clock lane on hardware lane 0. This property is valid for serial busses138 lane. This property is valid for serial busses only (e.g. MIPI CSI-2).144 Number of data lines actively used, only valid for parallel busses.
57 Number of data lines actively used, valid for the parallel busses.
141 communication with MAC ENET controller. Other busses - like SPI
277 The ARC CPU can be configured to have two busses;
194 /** Scan all available PCI host controllers and sub-busses */
1724 * :github:`21772` - Adding I2C devices to device tree with the same address on different busses gen…
3077 …ing I2C devices SX1509B to Devicetree with the same address on different busses generates FATAL ER…
